14 files changed, 441 insertions, 77 deletions

diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index 1719c66..9cfdb0f 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -29,6 +29,7 @@ LIB	= $(obj)lib$(CPU).a
 START	= start.o
 COBJS-y	:= cpu.o
 COBJS-y	+= traps.o
+COBJS-y += common.o
 COBJS-y += cpu_init.o
 COBJS-y += fixed_sdram.o
 COBJS-y += i2c.o
diff --git a/arch/powerpc/cpu/mpc512x/common.c b/arch/powerpc/cpu/mpc512x/common.c
new file mode 100644
index 0000000..180d323
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/common.c
@@ -0,0 +1,25 @@
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+
+#if defined(CONFIG_SYS_POST_WORD_ADDR)
+# define _POST_ADDR	(CONFIG_SYS_POST_WORD_ADDR)
+#else
+#error echo "No POST word address defined"
+#endif
+
+void post_word_store(ulong a)
+{
+	volatile void *save_addr = (volatile void *)(_POST_ADDR);
+
+	out_be32(save_addr, a);
+}
+
+ulong post_word_load(void)
+{
+	volatile void *save_addr = (volatile void *)(_POST_ADDR);
+
+	return in_be32(save_addr);
+}
+#endif  /* CONFIG_POST || CONFIG_LOGBUFFER */
diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c
index 9361161..f8d19a0 100644
--- a/arch/powerpc/cpu/mpc512x/diu.c
+++ b/arch/powerpc/cpu/mpc512x/diu.c
@@ -34,6 +34,8 @@
 #include <video_fb.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_FSL_DIU_LOGO_BMP
 extern unsigned int FSL_Logo_BMP[];
 #else
@@ -65,10 +67,11 @@ void diu_set_pixel_clock(unsigned int pixclock)
 char *valid_bmp(char *addr)
 {
 	unsigned long h_addr;
+	bd_t *bd = gd->bd;
 
 	h_addr = simple_strtoul(addr, NULL, 16);
-	if (h_addr < CONFIG_SYS_FLASH_BASE ||
-			h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) {
+	if (h_addr < bd->bi_flashstart ||
+	    h_addr >= (bd->bi_flashstart + bd->bi_flashsize - 1)) {
 		printf("bmp addr %lx is not a valid flash address\n", h_addr);
 		return 0;
 	} else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
@@ -84,8 +87,13 @@ int mpc5121_diu_init(void)
 	char *bmp = NULL;
 	char *bmp_env;
 
+#if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES)
+	xres = CONFIG_VIDEO_XRES;
+	yres = CONFIG_VIDEO_YRES;
+#else
 	xres = 1024;
 	yres = 768;
+#endif
 	pixel_format = 0x88883316;
 
 	debug("mpc5121_diu_init\n");
diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
index 442b5fc..550cbd0 100644
--- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c
+++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
@@ -78,7 +78,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 			u32 *dram_init_seq, int seq_sz)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize = CONFIG_SYS_MAX_RAM_SIZE;
 	u32 msize_log2 = __ilog2(msize);
 	u32 i;
 
@@ -91,7 +91,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 	}
 
 	/* Initialize IO Control */
-	out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+	out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
 
 	/* Initialize DDR Local Window */
 	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
@@ -148,5 +148,10 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 	out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
 	out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
 
+	msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+	/* Fix DDR Local Window for new size */
+	out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
+	sync_law(&im->sysconf.ddrlaw.ar);
+
 	return msize;
 }
diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c
index ec2f41b..cb5bbf0 100644
--- a/arch/powerpc/cpu/mpc512x/serial.c
+++ b/arch/powerpc/cpu/mpc512x/serial.c
@@ -32,14 +32,16 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <serial.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_PSC_CONSOLE)
+#if defined(CONFIG_PSC_CONSOLE) || defined(CONFIG_SERIAL_MULTI)
 
 static void fifo_init (volatile psc512x_t *psc)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 tfsize, rfsize;
 
 	/* reset Rx & Tx fifo slice */
 	out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
@@ -49,8 +51,65 @@ static void fifo_init (volatile psc512x_t *psc)
 	out_be32(&psc->rfintmask, 0);
 	out_be32(&psc->tfintmask, 0);
 
-	out_be32(&psc->tfsize, CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16));
-	out_be32(&psc->rfsize, CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16));
+#if defined(CONFIG_SERIAL_MULTI)
+	switch (((u32)psc & 0xf00) >> 8) {
+	case 0:
+		tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16);
+		rfsize = FIFOC_PSC0_RX_SIZE | (FIFOC_PSC0_RX_ADDR << 16);
+		break;
+	case 1:
+		tfsize = FIFOC_PSC1_TX_SIZE | (FIFOC_PSC1_TX_ADDR << 16);
+		rfsize = FIFOC_PSC1_RX_SIZE | (FIFOC_PSC1_RX_ADDR << 16);
+		break;
+	case 2:
+		tfsize = FIFOC_PSC2_TX_SIZE | (FIFOC_PSC2_TX_ADDR << 16);
+		rfsize = FIFOC_PSC2_RX_SIZE | (FIFOC_PSC2_RX_ADDR << 16);
+		break;
+	case 3:
+		tfsize = FIFOC_PSC3_TX_SIZE | (FIFOC_PSC3_TX_ADDR << 16);
+		rfsize = FIFOC_PSC3_RX_SIZE | (FIFOC_PSC3_RX_ADDR << 16);
+		break;
+	case 4:
+		tfsize = FIFOC_PSC4_TX_SIZE | (FIFOC_PSC4_TX_ADDR << 16);
+		rfsize = FIFOC_PSC4_RX_SIZE | (FIFOC_PSC4_RX_ADDR << 16);
+		break;
+	case 5:
+		tfsize = FIFOC_PSC5_TX_SIZE | (FIFOC_PSC5_TX_ADDR << 16);
+		rfsize = FIFOC_PSC5_RX_SIZE | (FIFOC_PSC5_RX_ADDR << 16);
+		break;
+	case 6:
+		tfsize = FIFOC_PSC6_TX_SIZE | (FIFOC_PSC6_TX_ADDR << 16);
+		rfsize = FIFOC_PSC6_RX_SIZE | (FIFOC_PSC6_RX_ADDR << 16);
+		break;
+	case 7:
+		tfsize = FIFOC_PSC7_TX_SIZE | (FIFOC_PSC7_TX_ADDR << 16);
+		rfsize = FIFOC_PSC7_RX_SIZE | (FIFOC_PSC7_RX_ADDR << 16);
+		break;
+	case 8:
+		tfsize = FIFOC_PSC8_TX_SIZE | (FIFOC_PSC8_TX_ADDR << 16);
+		rfsize = FIFOC_PSC8_RX_SIZE | (FIFOC_PSC8_RX_ADDR << 16);
+		break;
+	case 9:
+		tfsize = FIFOC_PSC9_TX_SIZE | (FIFOC_PSC9_TX_ADDR << 16);
+		rfsize = FIFOC_PSC9_RX_SIZE | (FIFOC_PSC9_RX_ADDR << 16);
+		break;
+	case 10:
+		tfsize = FIFOC_PSC10_TX_SIZE | (FIFOC_PSC10_TX_ADDR << 16);
+		rfsize = FIFOC_PSC10_RX_SIZE | (FIFOC_PSC10_RX_ADDR << 16);
+		break;
+	case 11:
+		tfsize = FIFOC_PSC11_TX_SIZE | (FIFOC_PSC11_TX_ADDR << 16);
+		rfsize = FIFOC_PSC11_RX_SIZE | (FIFOC_PSC11_RX_ADDR << 16);
+		break;
+	default:
+		return;
+	}
+#else
+	tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
+	rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
+#endif
+	out_be32(&psc->tfsize, tfsize);
+	out_be32(&psc->rfsize, rfsize);
 
 	/* enable Tx & Rx FIFO slice */
 	out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
@@ -60,24 +119,47 @@ static void fifo_init (volatile psc512x_t *psc)
 	__asm__ volatile ("sync");
 }
 
-void serial_setbrg(void)
+void serial_setbrg_dev(unsigned int idx)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 	unsigned long baseclk, div;
+	unsigned long baudrate;
+	char buf[16];
+	char *br_env;
+
+	baudrate = gd->baudrate;
+	if (idx != CONFIG_PSC_CONSOLE) {
+		/* Allows setting baudrate for other serial devices
+		 * on PSCx using environment. If not specified, use
+		 * the same baudrate as for console.
+		 */
+		sprintf(buf, "psc%d_baudrate", idx);
+		br_env = getenv(buf);
+		if (br_env)
+			baudrate = simple_strtoul(br_env, NULL, 10);
+
+		debug("%s: idx %d, baudrate %d\n", __func__, idx, baudrate);
+	}
 
-	/* calculate dividor for setting PSC CTUR and CTLR registers */
+	/* calculate divisor for setting PSC CTUR and CTLR registers */
 	baseclk = (gd->ips_clk + 8) / 16;
-	div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
+	div = (baseclk + (baudrate / 2)) / baudrate;
 
 	out_8(&psc->ctur, (div >> 8) & 0xff);
 	out_8(&psc->ctlr,  div & 0xff); /* set baudrate */
 }
 
-int serial_init(void)
+int serial_init_dev(unsigned int idx)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+#if defined(CONFIG_SERIAL_MULTI)
+	u32 reg;
+
+	reg = in_be32(&im->clk.sccr[0]);
+	out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx));
+#endif
 
 	fifo_init (psc);
 
@@ -100,7 +182,7 @@ int serial_init(void)
 	out_8(&psc->mode, PSC_MODE_1_STOPBIT);
 
 	/* set baudrate */
-	serial_setbrg();
+	serial_setbrg_dev(idx);
 
 	/* disable all interrupts */
 	out_be16(&psc->psc_imr, 0);
@@ -113,13 +195,27 @@ int serial_init(void)
 	return 0;
 }
 
-void serial_putc (const char c)
+int serial_uninit_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+	u32 reg;
+
+	out_8(&psc->command, PSC_RX_DISABLE | PSC_TX_DISABLE);
+	reg = in_be32(&im->clk.sccr[0]);
+	reg &= ~CLOCK_SCCR1_PSC_EN(idx);
+	out_be32(&im->clk.sccr[0], reg);
+
+	return 0;
+}
+
+void serial_putc_dev(unsigned int idx, const char c)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	if (c == '\n')
-		serial_putc ('\r');
+		serial_putc_dev(idx, '\r');
 
 	/* Wait for last character to go. */
 	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
@@ -128,10 +224,10 @@ void serial_putc (const char c)
 	out_8(&psc->tfdata_8, c);
 }
 
-void serial_putc_raw (const char c)
+void serial_putc_raw_dev(unsigned int idx, const char c)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	/* Wait for last character to go. */
 	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
@@ -140,18 +236,16 @@ void serial_putc_raw (const char c)
 	out_8(&psc->tfdata_8, c);
 }
 
-
-void serial_puts (const char *s)
+void serial_puts_dev(unsigned int idx, const char *s)
 {
-	while (*s) {
-		serial_putc (*s++);
-	}
+	while (*s)
+		serial_putc_dev(idx, *s++);
 }
 
-int serial_getc (void)
+int serial_getc_dev(unsigned int idx)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	/* Wait for a character to arrive. */
 	while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
@@ -160,18 +254,18 @@ int serial_getc (void)
 	return in_8(&psc->rfdata_8);
 }
 
-int serial_tstc (void)
+int serial_tstc_dev(unsigned int idx)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
 }
 
-void serial_setrts(int s)
+void serial_setrts_dev(unsigned int idx, int s)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	if (s) {
 		/* Assert RTS (become LOW) */
@@ -183,11 +277,214 @@ void serial_setrts(int s)
 	}
 }
 
-int serial_getcts(void)
+int serial_getcts_dev(unsigned int idx)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	return (in_8(&psc->ip) & 0x1) ? 0 : 1;
 }
+#endif /* CONFIG_PSC_CONSOLE || CONFIG_SERIAL_MULTI */
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \
+	int serial##port##_init(void) \
+	{ \
+		return serial_init_dev(port); \
+	} \
+	int serial##port##_uninit(void) \
+	{ \
+		return serial_uninit_dev(port); \
+	} \
+	void serial##port##_setbrg(void) \
+	{ \
+		serial_setbrg_dev(port); \
+	} \
+	int serial##port##_getc(void) \
+	{ \
+		return serial_getc_dev(port); \
+	} \
+	int serial##port##_tstc(void) \
+	{ \
+		return serial_tstc_dev(port); \
+	} \
+	void serial##port##_putc(const char c) \
+	{ \
+		serial_putc_dev(port, c); \
+	} \
+	void serial##port##_puts(const char *s) \
+	{ \
+		serial_puts_dev(port, s); \
+	}
+
+#define INIT_PSC_SERIAL_STRUCTURE(port, name, bus) { \
+	name, \
+	bus, \
+	serial##port##_init, \
+	serial##port##_uninit, \
+	serial##port##_setbrg, \
+	serial##port##_getc, \
+	serial##port##_tstc, \
+	serial##port##_putc, \
+	serial##port##_puts, \
+}
+
+#if defined(CONFIG_SYS_PSC1)
+DECLARE_PSC_SERIAL_FUNCTIONS(1);
+struct serial_device serial1_device =
+INIT_PSC_SERIAL_STRUCTURE(1, "psc1", "UART1");
+#endif
+
+#if defined(CONFIG_SYS_PSC3)
+DECLARE_PSC_SERIAL_FUNCTIONS(3);
+struct serial_device serial3_device =
+INIT_PSC_SERIAL_STRUCTURE(3, "psc3", "UART3");
+#endif
+
+#if defined(CONFIG_SYS_PSC4)
+DECLARE_PSC_SERIAL_FUNCTIONS(4);
+struct serial_device serial4_device =
+INIT_PSC_SERIAL_STRUCTURE(4, "psc4", "UART4");
+#endif
+
+#if defined(CONFIG_SYS_PSC6)
+DECLARE_PSC_SERIAL_FUNCTIONS(6);
+struct serial_device serial6_device =
+INIT_PSC_SERIAL_STRUCTURE(6, "psc6", "UART6");
+#endif
+
+#else
+
+void serial_setbrg(void)
+{
+	serial_setbrg_dev(CONFIG_PSC_CONSOLE);
+}
+
+int serial_init(void)
+{
+	return serial_init_dev(CONFIG_PSC_CONSOLE);
+}
+
+void serial_putc(const char c)
+{
+	serial_putc_dev(CONFIG_PSC_CONSOLE, c);
+}
+
+void serial_putc_raw(const char c)
+{
+	serial_putc_raw_dev(CONFIG_PSC_CONSOLE, c);
+}
+
+void serial_puts(const char *s)
+{
+	serial_puts_dev(CONFIG_PSC_CONSOLE, s);
+}
+
+int serial_getc(void)
+{
+	return serial_getc_dev(CONFIG_PSC_CONSOLE);
+}
+
+int serial_tstc(void)
+{
+	return serial_tstc_dev(CONFIG_PSC_CONSOLE);
+}
+
+void serial_setrts(int s)
+{
+	return serial_setrts_dev(CONFIG_PSC_CONSOLE, s);
+}
+
+int serial_getcts(void)
+{
+	return serial_getcts_dev(CONFIG_PSC_CONSOLE);
+}
 #endif /* CONFIG_PSC_CONSOLE */
+
+#if defined(CONFIG_SERIAL_MULTI)
+#include <stdio_dev.h>
+/*
+ * Routines for communication with serial devices over PSC
+ */
+/* Bitfield for initialized PSCs */
+static unsigned int initialized;
+
+struct stdio_dev *open_port(int num, int baudrate)
+{
+	struct stdio_dev *port;
+	char env_var[16];
+	char env_val[10];
+	char name[7];
+
+	if (num < 0 || num > 11)
+		return NULL;
+
+	sprintf(name, "psc%d", num);
+	port = stdio_get_by_name(name);
+	if (!port)
+		return NULL;
+
+	if (!test_bit(num, &initialized)) {
+		sprintf(env_var, "psc%d_baudrate", num);
+		sprintf(env_val, "%d", baudrate);
+		setenv(env_var, env_val);
+
+		if (port->start())
+			return NULL;
+
+		set_bit(num, &initialized);
+	}
+
+	return port;
+}
+
+int close_port(int num)
+{
+	struct stdio_dev *port;
+	int ret;
+	char name[7];
+
+	if (num < 0 || num > 11)
+		return -1;
+
+	sprintf(name, "psc%d", num);
+	port = stdio_get_by_name(name);
+	if (!port)
+		return -1;
+
+	ret = port->stop();
+	clear_bit(num, &initialized);
+
+	return ret;
+}
+
+int write_port(struct stdio_dev *port, char *buf)
+{
+	if (!port || !buf)
+		return -1;
+
+	port->puts(buf);
+
+	return 0;
+}
+
+int read_port(struct stdio_dev *port, char *buf, int size)
+{
+	int cnt = 0;
+
+	if (!port || !buf)
+		return -1;
+
+	if (!size)
+		return 0;
+
+	while (port->tstc()) {
+		buf[cnt++] = port->getc();
+		if (cnt > size)
+			break;
+	}
+
+	return cnt;
+}
+#endif /* CONFIG_SERIAL_MULTI */
diff --git a/arch/powerpc/cpu/mpc5xxx/serial.c b/arch/powerpc/cpu/mpc5xxx/serial.c
index 59a877a..0127065 100644
--- a/arch/powerpc/cpu/mpc5xxx/serial.c
+++ b/arch/powerpc/cpu/mpc5xxx/serial.c
@@ -340,6 +340,7 @@ struct serial_device serial0_device =
 	"serial0",
 	"UART0",
 	serial0_init,
+	NULL,
 	serial0_setbrg,
 	serial0_getc,
 	serial0_tstc,
@@ -352,6 +353,7 @@ struct serial_device serial1_device =
 	"serial1",
 	"UART1",
 	serial1_init,
+	NULL,
 	serial1_setbrg,
 	serial1_getc,
 	serial1_tstc,
diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c
index 64033fe..fecfc80 100644
--- a/arch/powerpc/cpu/mpc83xx/serdes.c
+++ b/arch/powerpc/cpu/mpc83xx/serdes.c
@@ -15,7 +15,7 @@
 #include <config.h>
 #include <common.h>
 #include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
 
 /* SerDes registers */
 #define FSL_SRDSCR0_OFFS		0x0
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 0cc6e03..fddeb2f 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
  * (C) Copyright 2002, 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
@@ -44,21 +44,19 @@ int checkcpu (void)
 	uint major, minor;
 	struct cpu_type *cpu;
 	char buf1[32], buf2[32];
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_CORENET
-	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
-		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
-#else
+#endif /* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
 	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
 		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#endif
 #else
 #ifdef CONFIG_FSL_CORENET
-	u32 ddr_sync = 0;
+	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
 #else
 	u32 ddr_ratio = 0;
-#endif
+#endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
 	int i;
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e0126d3..e578b29 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -180,54 +180,54 @@ void cpu_init_f (void)
 	 * has been determined
 	 */
 #if defined(CONFIG_SYS_OR0_REMAP)
-	memctl->or0 = CONFIG_SYS_OR0_REMAP;
+	out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
 #endif
 #if defined(CONFIG_SYS_OR1_REMAP)
-	memctl->or1 = CONFIG_SYS_OR1_REMAP;
+	out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
 #endif
 
 	/* now restrict to preliminary range */
 	/* if cs1 is already set via debugger, leave cs0/cs1 alone */
 	if (! memctl->br1 & 1) {
 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
-		memctl->br0 = CONFIG_SYS_BR0_PRELIM;
-		memctl->or0 = CONFIG_SYS_OR0_PRELIM;
+		out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
+		out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
-		memctl->or1 = CONFIG_SYS_OR1_PRELIM;
-		memctl->br1 = CONFIG_SYS_BR1_PRELIM;
+		out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
+		out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
 #endif
 	}
 
 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
-	memctl->or2 = CONFIG_SYS_OR2_PRELIM;
-	memctl->br2 = CONFIG_SYS_BR2_PRELIM;
+	out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
+	out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
-	memctl->or3 = CONFIG_SYS_OR3_PRELIM;
-	memctl->br3 = CONFIG_SYS_BR3_PRELIM;
+	out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
+	out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
-	memctl->or4 = CONFIG_SYS_OR4_PRELIM;
-	memctl->br4 = CONFIG_SYS_BR4_PRELIM;
+	out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
+	out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
-	memctl->or5 = CONFIG_SYS_OR5_PRELIM;
-	memctl->br5 = CONFIG_SYS_BR5_PRELIM;
+	out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
+	out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
-	memctl->or6 = CONFIG_SYS_OR6_PRELIM;
-	memctl->br6 = CONFIG_SYS_BR6_PRELIM;
+	out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
+	out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
-	memctl->or7 = CONFIG_SYS_OR7_PRELIM;
-	memctl->br7 = CONFIG_SYS_BR7_PRELIM;
+	out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
+	out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
 #endif
 
 #if defined(CONFIG_CPM2)
@@ -260,6 +260,10 @@ void cpu_init_f (void)
 
 int cpu_init_r(void)
 {
+#ifdef CONFIG_SYS_LBC_LCRR
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+#endif
+
 	puts ("L2:    ");
 
 #if defined(CONFIG_L2_CACHE)
@@ -383,6 +387,17 @@ int cpu_init_r(void)
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif
+
+#ifdef CONFIG_SYS_LBC_LCRR
+	/*
+	 * Modify the CLKDIV field of LCRR register to improve the writing
+	 * speed for NOR flash.
+	 */
+	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
+	__raw_readl(&lbc->lcrr);
+	isync();
+#endif
+
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 268edbc..8132115 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao@motorola.com)
@@ -71,22 +71,30 @@ void get_sys_info (sys_info_t * sysInfo)
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
 	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
+	uint ratio[4];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	uint mem_pll_rat;
 
 	sysInfo->freqSystemBus = sysclk;
 	sysInfo->freqDDRBus = sysclk;
-	freqCC_PLL[0] = sysclk;
-	freqCC_PLL[1] = sysclk;
-	freqCC_PLL[2] = sysclk;
-	freqCC_PLL[3] = sysclk;
 
 	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
-	freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
-	freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
-	freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
-	freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+	if (mem_pll_rat > 2)
+		sysInfo->freqDDRBus *= mem_pll_rat;
+	else
+		sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
 
+	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
+	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
+	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
+	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+	for (i = 0; i < 4; i++) {
+		if (ratio[i] > 4)
+			freqCC_PLL[i] = sysclk * ratio[i];
+		else
+			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
+	}
 	rcw_tmp = in_be32(&gur->rcwsr[3]);
 	for (i = 0; i < cpu_numcores(); i++) {
 		u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c
index 664db65..9514c66 100644
--- a/arch/powerpc/cpu/mpc8xx/serial.c
+++ b/arch/powerpc/cpu/mpc8xx/serial.c
@@ -392,6 +392,7 @@ struct serial_device serial_smc_device =
 	"serial_smc",
 	"SMC",
 	smc_init,
+	NULL,
 	smc_setbrg,
 	smc_getc,
 	smc_tstc,
@@ -662,6 +663,7 @@ struct serial_device serial_scc_device =
 	"serial_scc",
 	"SCC",
 	scc_init,
+	NULL,
 	scc_setbrg,
 	scc_getc,
 	scc_tstc,
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 03f9c43..4a282bc 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -198,6 +198,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 	pre_pd_exit_mclk = act_pd_exit_mclk;
 	taxpd_mclk = 8;
 	tmrd_mclk = 4;
+	/* set the turnaround time */
+	trwt_mclk = 1;
 #else /* CONFIG_FSL_DDR2 */
 	/*
 	 * (tXARD and tXARDS). Empirical?
diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
index 9b7181d..85995ca 100644
--- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
+++ b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
@@ -176,15 +176,14 @@ static struct pci_info pci_config_info[] =
 			 (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
 	},
 	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
-			 (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
-			 (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
-			 (1 << 0x18) | (1 << 0x1c),
+		.cfg =   (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
+			 (1 << 0xd) | (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
+			 (1 << 0x18) | (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
 	},
 	[LAW_TRGT_IF_PCIE_3] = {
-		.cfg =   (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
-			 (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
-			 (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
+		.cfg =   (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
+			 (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | (1 << 0x15) |
+			 (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | (1 << 0x1c),
 	},
 };
 #elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c
index 8de6542..e6ab570 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c
@@ -822,6 +822,7 @@ struct serial_device serial0_device =
 	"serial0",
 	"UART0",
 	serial0_init,
+	NULL,
 	serial0_setbrg,
 	serial0_getc,
 	serial0_tstc,
@@ -834,6 +835,7 @@ struct serial_device serial1_device =
 	"serial1",
 	"UART1",
 	serial1_init,
+	NULL,
 	serial1_setbrg,
 	serial1_getc,
 	serial1_tstc,