diff options
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c | 79 |
1 files changed, 74 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index cb6a6f0..7e72f5f 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -1,17 +1,31 @@ /* - * Copyright (C) 2008 Freescale Semicondutor, Inc. + * Copyright 2008,2010 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #include <config.h> #include <common.h> #include <asm/io.h> #include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> /* PORDEVSR register */ #define GUTS_PORDEVSR_OFFS 0xc @@ -52,6 +66,61 @@ #define FSL_SRDSCR3_LANEE_SGMII 0x00000000 #define FSL_SRDSCR3_LANEE_SATA 0x00150005 + +#define SRDS1_MAX_LANES 8 +#define SRDS2_MAX_LANES 2 + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x1] = {SATA1, SATA2}, + [0x3] = {SATA1, NONE}, + [0x4] = {SGMII_TSEC1, SGMII_TSEC3}, + [0x6] = {SGMII_TSEC1, NONE}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int i; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + + u32 srds2_cfg = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> + GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT; + + debug("%s: dev = %d\n", __FUNCTION__, device); + debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg); + debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_cfg); + + if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg); + return 0; + } + + if (srds2_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_cfg); + return 0; + } + + for (i = 0; i < SRDS1_MAX_LANES; i++) { + if (serdes1_cfg_tbl[srds1_cfg][i] == device) + return 1; + } + for (i = 0; i < SRDS2_MAX_LANES; i++) { + if (serdes2_cfg_tbl[srds2_cfg][i] == device) + return 1; + } + + return 0; +} + void fsl_serdes_init(void) { void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |