summaryrefslogtreecommitdiff
path: root/arch/powerpc/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r--arch/powerpc/cpu/mpc83xx/Makefile4
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c8
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S4
3 files changed, 13 insertions, 3 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index c345dd6..cf91162 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -38,9 +38,7 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
# Stub implementations of cache management functions for USB
obj-y += cache.o
-ifdef CONFIG_SYS_FSL_DDR2
-obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o
-else
+ifndef CONFIG_SYS_FSL_DDRC_GEN2
obj-y += spd_sdram.o
endif
obj-$(CONFIG_SYS_FSL_DDR2) += law.o
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 1a58a19..46ae80c 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -86,6 +86,14 @@ void get_sys_info(sys_info_t *sys_info)
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+ /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
+ * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
+ * it uses 6.
+ */
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+ if (SVR_MAJ(get_svr()) >= 2)
+ mem_pll_rat *= 2;
+#endif
if (mem_pll_rat > 2)
sys_info->freq_ddrbus *= mem_pll_rat;
else
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 6a81fa7..db84d10 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -886,7 +886,11 @@ delete_ccsr_l2_tlb:
erratum_set_dcsr 0xb0008 0x00900000
erratum_set_dcsr 0xb0e40 0xe00a0000
erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+#ifdef CONFIG_RAMBOOT_PBL
+ erratum_set_ccsr 0x10f00 0x495e5000
+#else
erratum_set_ccsr 0x10f00 0x415e5000
+#endif
erratum_set_ccsr 0x11f00 0x415e5000
/* Make temp mapping uncacheable again, if it was initially */