diff options
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 1 | ||||
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/start.S | 28 | ||||
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/u-boot.lds | 13 |
3 files changed, 26 insertions, 16 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 9634deb..95df1d9 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -416,7 +416,6 @@ static void test(void); static void DQS_calibration_process(void); #endif #endif -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); static unsigned char spd_read(uchar chip, uint addr) { diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 0e75794..2218508 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -48,21 +48,23 @@ *------------------------------------------------------------------------------- */ -/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards - * +/* + * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards * - * The processor starts at 0xfffffffc and the code is executed - * from flash/rom. - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memorymap. + * The following description only applies to the NOR flash style booting. + * NAND booting is different. For more details about NAND booting on 4xx + * take a look at doc/README.nand-boot-ppc440. * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 + * The CPU starts at address 0xfffffffc (last word in the address space). + * The U-Boot image therefore has to be located in the "upper" area of the + * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for + * the boot chip-select (CS0) is quite big and covers this area. On the + * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will + * reconfigure this CS0 (and other chip-selects as well when configured + * this way) in the boot process to the "correct" values matching the + * board layout. */ + #include <asm-offsets.h> #include <config.h> #include <asm/ppc4xx.h> @@ -265,7 +267,7 @@ /* NOTREACHED - board_init_f() does not return */ #endif -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD) /* * 4xx RAM-booting U-Boot image is started from offset 0 */ diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index dac0e5b..656f59a 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -23,8 +23,12 @@ #include "config.h" /* CONFIG_BOARDDIR */ #ifndef RESET_VECTOR_ADDRESS +#ifdef CONFIG_RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS +#else #define RESET_VECTOR_ADDRESS 0xfffffffc #endif +#endif OUTPUT_ARCH(powerpc) @@ -55,13 +59,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : @@ -100,7 +105,11 @@ SECTIONS * start.o, since the first shadow TLB only covers 4k * of address space. */ +#ifdef CONFIG_INIT_TLB + CONFIG_INIT_TLB (.bootpg) +#else CONFIG_BOARDDIR/init.o (.bootpg) +#endif } :text = 0xffff #endif |