diff options
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx/start.S')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/start.S | 108 |
1 files changed, 0 insertions, 108 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 3b0e364..7aef43b 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -806,114 +806,6 @@ _start: #endif /* CONFIG_440 */ /*****************************************************************************/ -#ifdef CONFIG_IOP480 - /*----------------------------------------------------------------------- */ - /* Set up some machine state registers. */ - /*----------------------------------------------------------------------- */ - addi r0,r0,0x0000 /* initialize r0 to zero */ - mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */ - mttcr r0 /* timer control register */ - mtexier r0 /* disable all interrupts */ - addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ - ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ - mtdbsr r4 /* clear/reset the dbsr */ - mtexisr r4 /* clear all pending interrupts */ - addis r4,r0,0x8000 - mtexier r4 /* enable critical exceptions */ - addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ - ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ - mtiocr r4 /* since bit not used) & DRC to latch */ - /* data bus on rising edge of CAS */ - /*----------------------------------------------------------------------- */ - /* Clear XER. */ - /*----------------------------------------------------------------------- */ - mtxer r0 - /*----------------------------------------------------------------------- */ - /* Invalidate i-cache and d-cache TAG arrays. */ - /*----------------------------------------------------------------------- */ - addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ - addi r4,0,1024 /* 1/4 of I-cache */ -..cloop: - iccci 0,r3 - iccci r4,r3 - dccci 0,r3 - addic. r3,r3,-16 /* move back one cache line */ - bne ..cloop /* loop back to do rest until r3 = 0 */ - - /* */ - /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ - /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ - /* */ - - /* first copy IOP480 register base address into r3 */ - addis r3,0,0x5000 /* IOP480 register base address hi */ -/* ori r3,r3,0x0000 / IOP480 register base address lo */ - -#ifdef CONFIG_ADCIOP - /* use r4 as the working variable */ - /* turn on CS3 (LOCCTL.7) */ - lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ - andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ - stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ -#endif - -#ifdef CONFIG_DASA_SIM - /* use r4 as the working variable */ - /* turn on MA17 (LOCCTL.7) */ - lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ - ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ - stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ -#endif - - /* turn on MA16..13 (LCS0BRD.12 = 0) */ - lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ - andi. r4,r4,0xefff /* make bit 12 = 0 */ - stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ - - /* make sure above stores all comlete before going on */ - sync - - /* last thing, set local init status done bit (DEVINIT.31) */ - lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ - oris r4,r4,0x8000 /* make bit 31 = 1 */ - stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ - - /* clear all pending interrupts and disable all interrupts */ - li r4,-1 /* set p1 to 0xffffffff */ - stw r4,0x1b0(r3) /* clear all pending interrupts */ - stw r4,0x1b8(r3) /* clear all pending interrupts */ - li r4,0 /* set r4 to 0 */ - stw r4,0x1b4(r3) /* disable all interrupts */ - stw r4,0x1bc(r3) /* disable all interrupts */ - - /* make sure above stores all comlete before going on */ - sync - - /* Set-up icache cacheability. */ - lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h - ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l - mticcr r1 - isync - - /* Set-up dcache cacheability. */ - lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h - ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l - mtdccr r1 - - addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h - ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */ - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - GET_GOT /* initialize GOT access */ - - bl board_init_f /* run first part of init code (from Flash) */ - /* NOTREACHED - board_init_f() does not return */ - -#endif /* CONFIG_IOP480 */ - -/*****************************************************************************/ #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_405) |