diff options
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 6 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 48 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 221 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/p2041_ids.c (renamed from arch/powerpc/cpu/mpc85xx/p2040_ids.c) | 0 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/p2041_serdes.c (renamed from arch/powerpc/cpu/mpc85xx/p2040_serdes.c) | 26 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/portals.c | 6 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 15 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 11 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/tlb.c | 29 |
10 files changed, 323 insertions, 58 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 8a0a8e9..7026bca 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -78,8 +78,8 @@ COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments -COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o -COBJS-$(CONFIG_PPC_P2041) += p2040_ids.o +COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o +COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o @@ -111,7 +111,7 @@ COBJS-$(CONFIG_P1024) += p1021_serdes.o COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o -COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o +COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 53f0887..22fa461 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -46,7 +46,6 @@ int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; - uint fam; uint ver; uint major, minor; struct cpu_type *cpu; @@ -94,30 +93,25 @@ int checkcpu (void) printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); - fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); - if (PVR_FAM(PVR_85xx)) { - switch(PVR_MEM(pvr)) { - case 0x1: - case 0x2: - puts("E500"); - break; - case 0x3: - puts("E500MC"); - break; - case 0x4: - puts("E5500"); - break; - default: - puts("Unknown"); - break; - } - } else { + switch(ver) { + case PVR_VER_E500_V1: + case PVR_VER_E500_V2: + puts("E500"); + break; + case PVR_VER_E500MC: + puts("E500MC"); + break; + case PVR_VER_E5500: + puts("E5500"); + break; + default: puts("Unknown"); + break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); @@ -358,7 +352,7 @@ phys_size_t initdram(int board_type) lbc_sdram_init(); #endif - puts("DDR: "); + debug("DDR: "); return dram_size; } #endif /* CONFIG_SYS_RAMBOOT */ @@ -374,6 +368,8 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); +void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); + static void dump_spd_ddr_reg(void) { int i, j, k, m; @@ -460,19 +456,9 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; - phys_addr_t rpn = 0; int ddr_esel; - ptr = vstart; - - while (ptr < (vstart + size)) { - ddr_esel = find_tlb_idx((void *)ptr, 1); - if (ddr_esel != -1) { - read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); - disable_tlb(ddr_esel); - } - ptr += TSIZE_TO_BYTES(tsize); - } + clear_ddr_tlbs_phys(p_addr, size>>20); /* Setup new tlb to cover the physical address */ setup_ddr_tlbs_phys(p_addr, size>>20); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b3da970..6aca166 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -222,6 +222,10 @@ static void corenet_tb_init(void) void cpu_init_f (void) { extern void m8560_cpm_reset (void); +#ifdef CONFIG_SYS_DCSRBAR_PHYS + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + #ifdef CONFIG_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); uint svr = get_svr(); @@ -262,6 +266,13 @@ void cpu_init_f (void) /* Invalidate the CPC before DDR gets enabled */ invalidate_cpc(); + + #ifdef CONFIG_SYS_DCSRBAR_PHYS + /* set DCSRCR so that DCSR space is 1G */ + setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); + in_be32(&gur->dcsrcr); +#endif + } /* Implement a dummy function for those platforms w/o SERDES */ @@ -381,6 +392,12 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) { + puts("N/A\n"); + goto skip_l2; + } + u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ @@ -401,6 +418,8 @@ int cpu_init_r(void) ; printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); } + +skip_l2: #else puts("disabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 97d3928..8f13cd8 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -33,6 +33,7 @@ #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif +#include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */ DECLARE_GLOBAL_DATA_PTR; @@ -227,6 +228,12 @@ static inline void ft_fixup_l2cache(void *blob) u32 *ph; u32 l2cfg0 = mfspr(SPRN_L2CFG0); u32 size, line_size, num_ways, num_sets; + int has_l2 = 1; + + /* P2040/P2040E has no L2, so dont set any L2 props */ + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) + has_l2 = 0; size = (l2cfg0 & 0x3fff) * 64 * 1024; num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; @@ -249,21 +256,22 @@ static inline void ft_fixup_l2cache(void *blob) goto next; } + if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING - { u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) fdt_setprop_cell(blob, l2_off, "cache-stash-id", (*reg * 2) + 32 + 1); - } #endif - fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); - fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); - fdt_setprop_cell(blob, l2_off, "cache-size", size); - fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); - fdt_setprop_cell(blob, l2_off, "cache-level", 2); - fdt_setprop(blob, l2_off, "compatible", "cache", 6); + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, l2_off, "cache-block-size", + line_size); + fdt_setprop_cell(blob, l2_off, "cache-size", size); + fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); + fdt_setprop_cell(blob, l2_off, "cache-level", 2); + fdt_setprop(blob, l2_off, "compatible", "cache", 6); + } if (l3_off < 0) { ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); @@ -406,6 +414,126 @@ static void ft_fixup_qe_snum(void *blob) } #endif +/** + * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree + * + * The binding for an Fman firmware node is documented in + * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains + * the actual Fman firmware binary data. The operating system is expected to + * be able to parse the binary data to determine any attributes it needs. + */ +#ifdef CONFIG_SYS_DPAA_FMAN +void fdt_fixup_fman_firmware(void *blob) +{ + int rc, fmnode, fwnode = -1; + uint32_t phandle; + struct qe_firmware *fmanfw; + const struct qe_header *hdr; + unsigned int length; + uint32_t crc; + const char *p; + + /* The first Fman we find will contain the actual firmware. */ + fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); + if (fmnode < 0) + /* Exit silently if there are no Fman devices */ + return; + + /* If we already have a firmware node, then also exit silently. */ + if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) + return; + + /* If the environment variable is not set, then exit silently */ + p = getenv("fman_ucode"); + if (!p) + return; + + fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 0); + if (!fmanfw) + return; + + hdr = &fmanfw->header; + length = be32_to_cpu(hdr->length); + + /* Verify the firmware. */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Data at %p is not an Fman firmware\n", fmanfw); + return; + } + + if (length > CONFIG_SYS_FMAN_FW_LENGTH) { + printf("Fman firmware at %p is too large (size=%u)\n", + fmanfw, length); + return; + } + + length -= sizeof(u32); /* Subtract the size of the CRC */ + crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); + if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { + printf("Fman firmware at %p has invalid CRC\n", fmanfw); + return; + } + + /* Increase the size of the fdt to make room for the node. */ + rc = fdt_increase_size(blob, fmanfw->header.length); + if (rc < 0) { + printf("Unable to make room for Fman firmware: %s\n", + fdt_strerror(rc)); + return; + } + + /* Create the firmware node. */ + fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); + if (fwnode < 0) { + char s[64]; + fdt_get_path(blob, fmnode, s, sizeof(s)); + printf("Could not add firmware node to %s: %s\n", s, + fdt_strerror(fwnode)); + return; + } + rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware"); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add compatible property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + phandle = fdt_alloc_phandle(blob); + rc = fdt_setprop_cell(blob, fwnode, "linux,phandle", phandle); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add phandle property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add firmware property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + /* Find all other Fman nodes and point them to the firmware node. */ + while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) { + rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fmnode, s, sizeof(s)); + printf("Could not add pointer property to node %s: %s\n", + s, fdt_strerror(rc)); + return; + } + } +} +#else +#define fdt_fixup_fman_firmware(x) +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -445,6 +573,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) ft_fixup_qe_snum(blob); #endif + fdt_fixup_fman_firmware(blob); + #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); @@ -505,4 +635,79 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", "timer-frequency", gd->bus_clk/2, 1); + + do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", + "clock_freq", gd->bus_clk, 1); +} + +/* + * For some CCSR devices, we only have the virtual address, not the physical + * address. This is because we map CCSR as a whole, so we typically don't need + * a macro for the physical address of any device within CCSR. In this case, + * we calculate the physical address of that device using it's the difference + * between the virtual address of the device and the virtual address of the + * beginning of CCSR. + */ +#define CCSR_VIRT_TO_PHYS(x) \ + (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) + +/* + * Verify the device tree + * + * This function compares several CONFIG_xxx macros that contain physical + * addresses with the corresponding nodes in the device tree, to see if + * the physical addresses are all correct. For example, if + * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address + * of the first UART. We convert this to a physical address and compare + * that with the physical address of the first ns16550-compatible node + * in the device tree. If they don't match, then we display a warning. + * + * Returns 1 on success, 0 on failure + */ +int ft_verify_fdt(void *fdt) +{ + uint64_t ccsr = 0; + int aliases; + int off; + + /* First check the CCSR base address */ + off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); + if (off > 0) + ccsr = fdt_get_base_address(fdt, off); + + if (!ccsr) { + printf("Warning: could not determine base CCSR address in " + "device tree\n"); + /* No point in checking anything else */ + return 0; + } + + if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) { + printf("Warning: U-Boot configured CCSR at address %llx,\n" + "but the device tree has it at %llx\n", + (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr); + /* No point in checking anything else */ + return 0; + } + + /* + * Get the 'aliases' node. If there isn't one, then there's nothing + * left to do. + */ + aliases = fdt_path_offset(fdt, "/aliases"); + if (aliases > 0) { +#ifdef CONFIG_SYS_NS16550_COM1 + if (!fdt_verify_alias_address(fdt, aliases, "serial0", + CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) + return 0; +#endif + +#ifdef CONFIG_SYS_NS16550_COM2 + if (!fdt_verify_alias_address(fdt, aliases, "serial1", + CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) + return 0; +#endif + } + + return 1; } diff --git a/arch/powerpc/cpu/mpc85xx/p2040_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 112ea56..112ea56 100644 --- a/arch/powerpc/cpu/mpc85xx/p2040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c index 83bc82f..f68f281 100644 --- a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -37,8 +37,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, - PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, - NONE, NONE, NONE, NONE, NONE, NONE, }, + PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, }, [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, NONE, NONE, }, @@ -53,8 +53,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE, - NONE, NONE, NONE, NONE, NONE, }, + SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1, + XAUI_FM1, NONE, NONE, NONE, NONE, }, [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, @@ -68,19 +68,35 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { enum srds_prtcl serdes_get_prtcl(int cfg, int lane) { + enum srds_prtcl prtcl; + u32 svr = get_svr(); + u32 ver = SVR_SOC_VER(svr); + if (!serdes_lane_enabled(lane)) return NONE; - return serdes_cfg_tbl[cfg][lane]; + prtcl = serdes_cfg_tbl[cfg][lane]; + + /* P2040[e] does not support XAUI */ + if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + prtcl = NONE; + + return prtcl; } int is_serdes_prtcl_valid(u32 prtcl) { int i; + u32 svr = get_svr(); + u32 ver = SVR_SOC_VER(svr); if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) return 0; + /* P2040[e] does not support XAUI */ + if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + return 0; + for (i = 0; i < SRDS_MAX_LANES; i++) { if (serdes_cfg_tbl[prtcl][i] != NONE) return 1; diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index c014163..ecaa30d 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -151,8 +151,10 @@ static int fdt_qportal(void *blob, int off, int id, char *name, dev_handle = fdt_get_phandle(blob, dev_off); if (dev_handle <= 0) { dev_handle = fdt_alloc_phandle(blob); - fdt_setprop_cell(blob, dev_off, - "linux,phandle", dev_handle); + ret = fdt_create_phandle(blob, dev_off, + dev_handle); + if (ret < 0) + return ret; } ret = fdt_setprop(blob, childoff, "dev-handle", diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 56a853e..6678ed4 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * Kumar Gala <kumar.gala@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -144,6 +144,18 @@ __secondary_start_page: #endif #ifdef CONFIG_BACKSIDE_L2_CACHE + /* skip L2 setup on P2040/P2040E as they have no L2 */ + mfspr r2,SPRN_SVR + lis r3,SVR_P2040@h + ori r3,r3,SVR_P2040@l + cmpw r2,r3 + beq 3f + + lis r3,SVR_P2040_E@h + ori r3,r3,SVR_P2040_E@l + cmpw r2,r3 + beq 3f + /* Enable/invalidate the L2 cache */ msync lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h @@ -169,6 +181,7 @@ __secondary_start_page: andis. r1,r3,L2CSR0_L2E@h beq 2b #endif +3: #define EPAPR_MAGIC (0x45504150) #define ENTRY_ADDR_UPPER 0 diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 5777493..878a3d6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -31,7 +31,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc85xx.h> -#include <timestamp.h> #include <version.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ @@ -42,10 +41,6 @@ #include <asm/cache.h> #include <asm/mmu.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #undef MSR_KERNEL #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ @@ -399,9 +394,7 @@ _start: .long 0x27051956 /* U-BOOT Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 .globl _start_cont @@ -683,6 +676,8 @@ mck_return: /* Cache functions. */ +.globl flush_icache +flush_icache: .globl invalidate_icache invalidate_icache: mfspr r0,L1CSR1 diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 295f175..01a3561 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -300,4 +300,33 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) return setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); } + +/* Invalidate the DDR TLBs for the requested size */ +void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) +{ + u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + u64 memsize = (u64)memsize_in_meg << 20; + + ptr = vstart; + + while (ptr < (vstart + memsize)) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } +} + +void clear_ddr_tlbs(unsigned int memsize_in_meg) +{ + clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); +} + + #endif /* !CONFIG_NAND_SPL */ |