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-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile14
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c7
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c32
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c12
-rw-r--r--arch/powerpc/cpu/mpc85xx/p1010_serdes.c75
-rw-r--r--arch/powerpc/cpu/mpc85xx/p1023_serdes.c53
-rw-r--r--arch/powerpc/cpu/mpc85xx/p3041_ids.c10
-rw-r--r--arch/powerpc/cpu/mpc85xx/p4080_ids.c8
-rw-r--r--arch/powerpc/cpu/mpc85xx/p5020_ids.c10
-rw-r--r--arch/powerpc/cpu/mpc85xx/portals.c32
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c48
-rw-r--r--arch/powerpc/cpu/mpc85xx/tlb.c4
12 files changed, 261 insertions, 44 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index cbb0fc6..d61d34c 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -55,9 +55,13 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o
COBJS-$(CONFIG_P1012) += ddr-gen3.o
COBJS-$(CONFIG_P1013) += ddr-gen3.o
COBJS-$(CONFIG_P1014) += ddr-gen3.o
+COBJS-$(CONFIG_P1015) += ddr-gen3.o
+COBJS-$(CONFIG_P1016) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
+COBJS-$(CONFIG_P1024) += ddr-gen3.o
+COBJS-$(CONFIG_P1025) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
@@ -69,7 +73,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_CORENET) += liodn.o
COBJS-$(CONFIG_MP) += mp.o
COBJS-$(CONFIG_PCI) += pci.o
-COBJS-$(CONFIG_FSL_CORENET) += portals.o
+COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
@@ -87,12 +91,20 @@ COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o
COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o
COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
+COBJS-$(CONFIG_P1010) += p1010_serdes.o
COBJS-$(CONFIG_P1011) += p1021_serdes.o
COBJS-$(CONFIG_P1012) += p1021_serdes.o
COBJS-$(CONFIG_P1013) += p1022_serdes.o
+COBJS-$(CONFIG_P1014) += p1010_serdes.o
+COBJS-$(CONFIG_P1015) += p1021_serdes.o
+COBJS-$(CONFIG_P1016) += p1021_serdes.o
+COBJS-$(CONFIG_P1017) += p1023_serdes.o
COBJS-$(CONFIG_P1020) += p1021_serdes.o
COBJS-$(CONFIG_P1021) += p1021_serdes.o
COBJS-$(CONFIG_P1022) += p1022_serdes.o
+COBJS-$(CONFIG_P1023) += p1023_serdes.o
+COBJS-$(CONFIG_P1024) += p1021_serdes.o
+COBJS-$(CONFIG_P1025) += p1021_serdes.o
COBJS-$(CONFIG_P2010) += p2020_serdes.o
COBJS-$(CONFIG_P2020) += p2020_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1aad2ba..49ea6cc 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -33,6 +33,7 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/mmu.h>
+#include <asm/fsl_ifc.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
#include <post.h>
@@ -280,7 +281,8 @@ int cpu_mmc_init(bd_t *bis)
/*
* Print out the state of various machine registers.
- * Currently prints out LAWs, BR0/OR0, and TLBs
+ * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
+ * parameters for IFC and TLBs
*/
void mpc85xx_reginfo(void)
{
@@ -289,6 +291,9 @@ void mpc85xx_reginfo(void)
#if defined(CONFIG_FSL_LBC)
print_lbc_regs();
#endif
+#ifdef CONFIG_FSL_IFC
+ print_ifc_regs();
+#endif
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 8ece970..5642cd7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,10 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include "mp.h"
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include <nand.h>
+#include <errno.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -384,12 +388,6 @@ int cpu_init_r(void)
enable_cpc();
-#ifdef CONFIG_QE
- uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
- qe_init(qe_base);
- qe_reset();
-#endif
-
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
@@ -449,3 +447,25 @@ int sata_initialize(void)
return 1;
}
#endif
+
+void cpu_secondary_init_r(void)
+{
+#ifdef CONFIG_QE
+ uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+ int ret;
+ size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+
+ /* load QE firmware from NAND flash to DDR first */
+ ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+ &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+
+ if (ret && ret == -EUCLEAN) {
+ printf ("NAND read for QE firmware at offset %x failed %d\n",
+ CONFIG_SYS_QE_FW_IN_NAND, ret);
+ }
+#endif
+ qe_init(qe_base);
+ qe_reset();
+#endif
+}
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 00fa752..642f6c5 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -338,6 +338,9 @@ void fdt_add_enet_stashing(void *fdt)
do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
+ do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
+ do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
+ do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
}
#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
@@ -483,4 +486,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_SYS_SRIO
ft_srio_setup(blob);
#endif
+
+ /*
+ * system-clock = CCB clock/2
+ * Here gd->bus_clk = CCB clock
+ * We are using the system clock as 1588 Timer reference
+ * clock source select
+ */
+ do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
+ "timer-frequency", gd->bus_clk/2, 1);
}
diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
new file mode 100644
index 0000000..e8a0387
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 4
+#define SRDS2_MAX_LANES 2
+
+static u32 serdes1_prtcl_map, serdes2_prtcl_map;
+
+static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x00] = {NONE, NONE, NONE, NONE},
+ [0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
+ [0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3},
+ [0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3},
+};
+
+static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
+ [0x00] = {NONE, NONE},
+ [0x01] = {SATA1, SATA2},
+ [0x02] = {SATA1, SATA2},
+ [0x03] = {PCIE1, PCIE2},
+};
+
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ int ret = (1 << device) & serdes1_prtcl_map;
+
+ if (ret)
+ return ret;
+
+ return (1 << device) & serdes2_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+
+ if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
+ serdes2_prtcl_map |= (1 << lane_prtcl);
+ }
+}
diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
new file mode 100644
index 0000000..c8ab5d6
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 4
+
+static u32 serdes1_prtcl_map;
+
+static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x00] = {PCIE1, PCIE2, NONE, NONE},
+ [0x01] = {PCIE1, PCIE2, PCIE3, NONE},
+ [0x02] = {PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC2},
+ [0x03] = {PCIE1, PCIE2, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2},
+};
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ int ret = (1 << device) & serdes1_prtcl_map;
+ return ret;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+
+}
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
index febbee9..1255898 100644
--- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -52,10 +52,10 @@ struct liodn_id_table liodn_tbl[] = {
SET_SATA_LIODN(1, 127),
SET_SATA_LIODN(2, 128),
- SET_PCI_LIODN(1, 193),
- SET_PCI_LIODN(2, 194),
- SET_PCI_LIODN(3, 195),
- SET_PCI_LIODN(4, 196),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
index df25048..fd155c8 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -44,9 +44,9 @@ struct liodn_id_table liodn_tbl[] = {
SET_SDHC_LIODN(1, 156),
- SET_PCI_LIODN(1, 193),
- SET_PCI_LIODN(2, 194),
- SET_PCI_LIODN(3, 195),
+ SET_PCI_LIODN("fsl,p4080-pcie", 1, 193),
+ SET_PCI_LIODN("fsl,p4080-pcie", 2, 194),
+ SET_PCI_LIODN("fsl,p4080-pcie", 3, 195),
SET_DMA_LIODN(1, 196),
SET_DMA_LIODN(2, 197),
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
index febbee9..1255898 100644
--- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -52,10 +52,10 @@ struct liodn_id_table liodn_tbl[] = {
SET_SATA_LIODN(1, 127),
SET_SATA_LIODN(2, 128),
- SET_PCI_LIODN(1, 193),
- SET_PCI_LIODN(2, 194),
- SET_PCI_LIODN(3, 195),
- SET_PCI_LIODN(4, 196),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index 01aec6e..e8d53bb 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -30,18 +30,13 @@
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
-static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR;
+static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
void setup_portals(void)
{
+#ifdef CONFIG_FSL_CORENET
int i;
- /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
-#ifdef CONFIG_PHYS_64BIT
- out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
-#endif
- out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-
for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
u8 sdest = qp_info[i].sdest;
u16 fliodn = qp_info[i].fliodn;
@@ -53,6 +48,13 @@ void setup_portals(void)
/* set frame liodn */
out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
}
+#endif
+
+ /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
+#ifdef CONFIG_PHYS_64BIT
+ out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+#endif
+ out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
}
/* Update portal containter to match LAW setup of portal in phy map */
@@ -118,9 +120,12 @@ void fdt_portal(void *blob, const char *compat, const char *container,
static int fdt_qportal(void *blob, int off, int id, char *name,
enum fsl_dpaa_dev dev, int create)
{
- int childoff, dev_off, num, ret = 0;
+ int childoff, dev_off, ret = 0;
uint32_t dev_handle;
+#ifdef CONFIG_FSL_CORENET
+ int num;
u32 liodns[2];
+#endif
childoff = fdt_subnode_offset(blob, off, name);
if (create) {
@@ -154,9 +159,11 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
if (ret < 0)
return ret;
+#ifdef CONFIG_FSL_CORENET
num = get_dpaa_liodn(dev, &liodns[0], id);
ret = fdt_setprop(blob, childoff, "fsl,liodn",
&liodns[0], sizeof(u32) * num);
+#endif
} else {
return childoff;
}
@@ -184,7 +191,9 @@ void fdt_fixup_qportals(void *blob)
off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
while (off != -FDT_ERR_NOTFOUND) {
+#ifdef CONFIG_FSL_CORENET
u32 liodns[2];
+#endif
const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
int j, i = *ci;
@@ -192,6 +201,7 @@ void fdt_fixup_qportals(void *blob)
if (err < 0)
goto err;
+#ifdef CONFIG_FSL_CORENET
liodns[0] = qp_info[i].dliodn;
liodns[1] = qp_info[i].fliodn;
@@ -199,6 +209,7 @@ void fdt_fixup_qportals(void *blob)
&liodns, sizeof(u32) * 2);
if (err < 0)
goto err;
+#endif
i++;
@@ -207,6 +218,7 @@ void fdt_fixup_qportals(void *blob)
if (err < 0)
goto err;
+#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SYS_DPAA_PME
err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
if (err < 0)
@@ -214,6 +226,8 @@ void fdt_fixup_qportals(void *blob)
#else
fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
#endif
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
char name[] = "fman@0";
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..e530494 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -107,25 +107,45 @@ void get_sys_info (sys_info_t * sysInfo)
#define PME_CLK_SEL 0x80000000
#define FM1_CLK_SEL 0x40000000
#define FM2_CLK_SEL 0x20000000
+#define HWA_ASYNC_DIV 0x04000000
+#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
+#define HWA_CC_PLL 1
+#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
+#define HWA_CC_PLL 2
+#else
+#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
+#endif
rcw_tmp = in_be32(&gur->rcwsr[7]);
#ifdef CONFIG_SYS_DPAA_PME
- if (rcw_tmp & PME_CLK_SEL)
- sysInfo->freqPME = freqCC_PLL[2] / 2;
- else
+ if (rcw_tmp & PME_CLK_SEL) {
+ if (rcw_tmp & HWA_ASYNC_DIV)
+ sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
+ else
+ sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
+ } else {
sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+ }
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
- if (rcw_tmp & FM1_CLK_SEL)
- sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
- else
+ if (rcw_tmp & FM1_CLK_SEL) {
+ if (rcw_tmp & HWA_ASYNC_DIV)
+ sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
+ else
+ sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
+ } else {
sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+ }
#if (CONFIG_SYS_NUM_FMAN) == 2
- if (rcw_tmp & FM2_CLK_SEL)
- sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
- else
+ if (rcw_tmp & FM2_CLK_SEL) {
+ if (rcw_tmp & HWA_ASYNC_DIV)
+ sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
+ else
+ sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
+ } else {
sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+ }
#endif
#endif
@@ -162,7 +182,6 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
#endif
-#endif
#ifdef CONFIG_QE
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
@@ -170,6 +189,12 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#ifdef CONFIG_SYS_DPAA_FMAN
+ sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
+#endif
+
+#endif /* CONFIG_FSL_CORENET */
+
#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
@@ -254,7 +279,8 @@ int get_clocks (void)
gd->i2c2_clk = gd->i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
-#ifdef CONFIG_MPC8569
+#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
+ defined(CONFIG_P1014)
gd->sdhc_clk = gd->bus_clk;
#else
gd->sdhc_clk = gd->bus_clk / 2;
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 31143ba..295f175 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -55,6 +55,7 @@ void init_tlbs(void)
return ;
}
+#ifndef CONFIG_NAND_SPL
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
phys_addr_t *rpn)
{
@@ -73,7 +74,6 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
#endif
}
-#ifndef CONFIG_NAND_SPL
void print_tlbcam(void)
{
int i;
generated by cgit v1.1 at 2024-12-04 20:51:18 +0000