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-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c16
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c51
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c28
3 files changed, 58 insertions, 37 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 0cc6e03..fddeb2f 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
@@ -44,21 +44,19 @@ int checkcpu (void)
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_CORENET
- u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
- >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
-#else
+#endif /* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#endif
#else
#ifdef CONFIG_FSL_CORENET
- u32 ddr_sync = 0;
+ u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+ >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
#else
u32 ddr_ratio = 0;
-#endif
+#endif /* CONFIG_FSL_CORENET */
#endif /* CONFIG_DDR_CLK_FREQ */
int i;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e0126d3..e578b29 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -180,54 +180,54 @@ void cpu_init_f (void)
* has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
- memctl->or0 = CONFIG_SYS_OR0_REMAP;
+ out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
- memctl->or1 = CONFIG_SYS_OR1_REMAP;
+ out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
#endif
/* now restrict to preliminary range */
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (! memctl->br1 & 1) {
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
- memctl->br0 = CONFIG_SYS_BR0_PRELIM;
- memctl->or0 = CONFIG_SYS_OR0_PRELIM;
+ out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
+ out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
- memctl->or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->br1 = CONFIG_SYS_BR1_PRELIM;
+ out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
+ out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
#endif
}
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
- memctl->or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->br2 = CONFIG_SYS_BR2_PRELIM;
+ out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
+ out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- memctl->or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->br3 = CONFIG_SYS_BR3_PRELIM;
+ out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
+ out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
- memctl->or4 = CONFIG_SYS_OR4_PRELIM;
- memctl->br4 = CONFIG_SYS_BR4_PRELIM;
+ out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
+ out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
- memctl->or5 = CONFIG_SYS_OR5_PRELIM;
- memctl->br5 = CONFIG_SYS_BR5_PRELIM;
+ out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
+ out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
- memctl->or6 = CONFIG_SYS_OR6_PRELIM;
- memctl->br6 = CONFIG_SYS_BR6_PRELIM;
+ out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
+ out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
- memctl->or7 = CONFIG_SYS_OR7_PRELIM;
- memctl->br7 = CONFIG_SYS_BR7_PRELIM;
+ out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
+ out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
#endif
#if defined(CONFIG_CPM2)
@@ -260,6 +260,10 @@ void cpu_init_f (void)
int cpu_init_r(void)
{
+#ifdef CONFIG_SYS_LBC_LCRR
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+#endif
+
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)
@@ -383,6 +387,17 @@ int cpu_init_r(void)
#if defined(CONFIG_MP)
setup_mp();
#endif
+
+#ifdef CONFIG_SYS_LBC_LCRR
+ /*
+ * Modify the CLKDIV field of LCRR register to improve the writing
+ * speed for NOR flash.
+ */
+ clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
+ __raw_readl(&lbc->lcrr);
+ isync();
+#endif
+
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 268edbc..8132115 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
@@ -71,22 +71,30 @@ void get_sys_info (sys_info_t * sysInfo)
[14] = 4, /* CC4 PPL / 4 */
};
uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
+ uint ratio[4];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ uint mem_pll_rat;
sysInfo->freqSystemBus = sysclk;
sysInfo->freqDDRBus = sysclk;
- freqCC_PLL[0] = sysclk;
- freqCC_PLL[1] = sysclk;
- freqCC_PLL[2] = sysclk;
- freqCC_PLL[3] = sysclk;
sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
- freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
- freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
- freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
- freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+ mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+ if (mem_pll_rat > 2)
+ sysInfo->freqDDRBus *= mem_pll_rat;
+ else
+ sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
+ ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
+ ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
+ ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
+ ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+ for (i = 0; i < 4; i++) {
+ if (ratio[i] > 4)
+ freqCC_PLL[i] = sysclk * ratio[i];
+ else
+ freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
+ }
rcw_tmp = in_be32(&gur->rcwsr[3]);
for (i = 0; i < cpu_numcores(); i++) {
u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
generated by cgit v1.1 at 2024-11-30 07:26:25 +0000