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-rw-r--r--arch/mips/config.mk5
-rw-r--r--arch/mips/cpu/mips32/incaip/Makefile9
-rw-r--r--arch/mips/cpu/mips32/incaip/asc_serial.c300
-rw-r--r--arch/mips/cpu/mips32/incaip/asc_serial.h177
-rw-r--r--arch/mips/cpu/mips32/incaip/config.mk8
-rw-r--r--arch/mips/cpu/mips32/incaip/incaip_clock.c100
-rw-r--r--arch/mips/cpu/mips32/incaip/incaip_wdt.S55
-rw-r--r--arch/mips/cpu/mips32/interrupts.c5
-rw-r--r--arch/mips/cpu/mips64/interrupts.c5
-rw-r--r--arch/mips/cpu/u-boot.lds57
-rw-r--r--arch/mips/cpu/xburst/Makefile9
-rw-r--r--arch/mips/cpu/xburst/config.mk16
-rw-r--r--arch/mips/cpu/xburst/cpu.c136
-rw-r--r--arch/mips/cpu/xburst/jz4740.c235
-rw-r--r--arch/mips/cpu/xburst/jz_serial.c118
-rw-r--r--arch/mips/cpu/xburst/start.S179
-rw-r--r--arch/mips/cpu/xburst/timer.c149
-rw-r--r--arch/mips/include/asm/inca-ip.h2430
-rw-r--r--arch/mips/include/asm/u-boot-mips.h2
-rw-r--r--arch/mips/include/asm/u-boot.h9
-rw-r--r--arch/mips/lib/Makefile4
-rw-r--r--arch/mips/lib/board.c9
-rw-r--r--arch/mips/lib/io.c12
23 files changed, 70 insertions, 3959 deletions
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 1899f51..f4a234a 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -27,6 +27,8 @@ ENDIANNESS ?= -EB
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
+__HAVE_ARCH_GENERIC_BOARD := y
+
#
# From Linux arch/mips/Makefile
#
@@ -52,4 +54,5 @@ PLATFORM_CPPFLAGS += -msoft-float
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections -pie
-OBJCOPYFLAGS += --remove-section=.dynsym
+OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got
+OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn
diff --git a/arch/mips/cpu/mips32/incaip/Makefile b/arch/mips/cpu/mips32/incaip/Makefile
deleted file mode 100644
index 7341a4a..0000000
--- a/arch/mips/cpu/mips32/incaip/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = incaip_wdt.o
-obj-y += incaip_clock.o asc_serial.o
diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c
deleted file mode 100644
index 6f0e4f2..0000000
--- a/arch/mips/cpu/mips32/incaip/asc_serial.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * (INCA) ASC UART support
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/inca-ip.h>
-#include <serial.h>
-#include <linux/compiler.h>
-#include "asc_serial.h"
-
-
-#define SET_BIT(reg, mask) reg |= (mask)
-#define CLEAR_BIT(reg, mask) reg &= (~mask)
-#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
-#define SET_BITS(reg, mask) SET_BIT(reg, mask)
-#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
-
-extern uint incaip_get_fpiclk(void);
-
-static int serial_setopt (void);
-
-/* pointer to ASC register base address */
-static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
-
-/******************************************************************************
-*
-* serial_init - initialize a INCAASC channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-static int asc_serial_init(void)
-{
- /* we have to set PMU.EN13 bit to enable an ASC device*/
- INCAASC_PMU_ENABLE(13);
-
- /* and we have to set CLC register*/
- CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
- SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
-
- /* initialy we are in async mode */
- pAsc->asc_con = ASCCON_M_8ASYNC;
-
- /* select input port */
- pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
-
- /* TXFIFO's filling level */
- SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
- ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
- /* enable TXFIFO */
- SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
-
- /* RXFIFO's filling level */
- SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
- ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
- /* enable RXFIFO */
- SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
-
- /* enable error signals */
- SET_BIT(pAsc->asc_con, ASCCON_FEN);
- SET_BIT(pAsc->asc_con, ASCCON_OEN);
-
- /* acknowledge ASC interrupts */
- ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
-
- /* disable ASC interrupts */
- ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
-
- /* set FIFOs into the transparent mode */
- SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
- SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
-
- /* set baud rate */
- serial_setbrg();
-
- /* set the options */
- serial_setopt();
-
- return 0;
-}
-
-static void asc_serial_setbrg(void)
-{
- ulong uiReloadValue, fdv;
- ulong f_ASC;
-
- f_ASC = incaip_get_fpiclk();
-
-#ifndef INCAASC_USE_FDV
- fdv = 2;
- uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
- fdv = INCAASC_FDV_HIGH_BAUDRATE;
- uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
-#endif /* INCAASC_USE_FDV */
-
- if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
- {
-#ifndef INCAASC_USE_FDV
- fdv = 3;
- uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
- fdv = INCAASC_FDV_LOW_BAUDRATE;
- uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
-#endif /* INCAASC_USE_FDV */
-
- if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
- {
- return; /* can't impossibly generate that baud rate */
- }
- }
-
- /* Disable Baud Rate Generator; BG should only be written when R=0 */
- CLEAR_BIT(pAsc->asc_con, ASCCON_R);
-
-#ifndef INCAASC_USE_FDV
- /*
- * Disable Fractional Divider (FDE)
- * Divide clock by reload-value + constant (BRS)
- */
- /* FDE = 0 */
- CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
-
- if ( fdv == 2 )
- CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */
- else
- SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
-
-#else /* INCAASC_USE_FDV */
-
- /* Enable Fractional Divider */
- SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
-
- /* Set fractional divider value */
- pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
-
-#endif /* INCAASC_USE_FDV */
-
- /* Set reload value in BG */
- pAsc->asc_bg = uiReloadValue;
-
- /* Enable Baud Rate Generator */
- SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */
-}
-
-/*******************************************************************************
-*
-* serial_setopt - set the serial options
-*
-* Set the channel operating mode to that specified. Following options
-* are supported: CREAD, CSIZE, PARENB, and PARODD.
-*
-* Note, this routine disables the transmitter. The calling routine
-* may have to re-enable it.
-*
-* RETURNS:
-* Returns 0 to indicate success, otherwise -1 is returned
-*/
-
-static int serial_setopt (void)
-{
- ulong con;
-
- switch ( ASC_OPTIONS & ASCOPT_CSIZE )
- {
- /* 7-bit-data */
- case ASCOPT_CS7:
- con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */
- break;
-
- /* 8-bit-data */
- case ASCOPT_CS8:
- if ( ASC_OPTIONS & ASCOPT_PARENB )
- con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */
- else
- con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */
- break;
-
- /*
- * only 7 and 8-bit frames are supported
- * if we don't use IOCTL extensions
- */
- default:
- return -1;
- }
-
- if ( ASC_OPTIONS & ASCOPT_STOPB )
- SET_BIT(con, ASCCON_STP); /* 2 stop bits */
- else
- CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */
-
- if ( ASC_OPTIONS & ASCOPT_PARENB )
- SET_BIT(con, ASCCON_PEN); /* enable parity checking */
- else
- CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */
-
- if ( ASC_OPTIONS & ASCOPT_PARODD )
- SET_BIT(con, ASCCON_ODD); /* odd parity */
- else
- CLEAR_BIT(con, ASCCON_ODD); /* even parity */
-
- if ( ASC_OPTIONS & ASCOPT_CREAD )
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
-
- pAsc->asc_con |= con;
-
- return 0;
-}
-
-static void asc_serial_putc(const char c)
-{
- uint txFl = 0;
-
- if (c == '\n') serial_putc ('\r');
-
- /* check do we have a free space in the TX FIFO */
- /* get current filling level */
- do
- {
- txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
- }
- while ( txFl == INCAASC_TXFIFO_FULL );
-
- pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
-
- /* check for errors */
- if ( pAsc->asc_con & ASCCON_OE )
- {
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
- return;
- }
-}
-
-static int asc_serial_getc(void)
-{
- ulong symbol_mask;
- char c;
-
- while (!serial_tstc());
-
- symbol_mask =
- ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
-
- c = (char)(pAsc->asc_rbuf & symbol_mask);
-
- return c;
-}
-
-static int asc_serial_tstc(void)
-{
- int res = 1;
-
- if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
- {
- res = 0;
- }
- else if ( pAsc->asc_con & ASCCON_FE )
- {
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
- res = 0;
- }
- else if ( pAsc->asc_con & ASCCON_PE )
- {
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
- res = 0;
- }
- else if ( pAsc->asc_con & ASCCON_OE )
- {
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
- res = 0;
- }
-
- return res;
-}
-
-static struct serial_device asc_serial_drv = {
- .name = "asc_serial",
- .start = asc_serial_init,
- .stop = NULL,
- .setbrg = asc_serial_setbrg,
- .putc = asc_serial_putc,
- .puts = default_serial_puts,
- .getc = asc_serial_getc,
- .tstc = asc_serial_tstc,
-};
-
-void asc_serial_initialize(void)
-{
- serial_register(&asc_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &asc_serial_drv;
-}
diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.h b/arch/mips/cpu/mips32/incaip/asc_serial.h
deleted file mode 100644
index 7ffdcfa..0000000
--- a/arch/mips/cpu/mips32/incaip/asc_serial.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/* incaAscSio.h - (INCA) ASC UART tty driver header */
-
-#ifndef __INCincaAscSioh
-#define __INCincaAscSioh
-
-#include <asm/inca-ip.h>
-
-/* channel operating modes */
-#define ASCOPT_CSIZE 0x00000003
-#define ASCOPT_CS7 0x00000001
-#define ASCOPT_CS8 0x00000002
-#define ASCOPT_PARENB 0x00000004
-#define ASCOPT_STOPB 0x00000008
-#define ASCOPT_PARODD 0x00000010
-#define ASCOPT_CREAD 0x00000020
-
-#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
-
-/* ASC input select (0 or 1) */
-#define CONSOLE_TTY 0
-
-/* use fractional divider for baudrate settings */
-#define INCAASC_USE_FDV
-
-#ifdef INCAASC_USE_FDV
- #define INCAASC_FDV_LOW_BAUDRATE 71
- #define INCAASC_FDV_HIGH_BAUDRATE 453
-#endif /*INCAASC_USE_FDV*/
-
-
-#define INCAASC_TXFIFO_FL 1
-#define INCAASC_RXFIFO_FL 1
-#define INCAASC_TXFIFO_FULL 16
-
-/* interrupt lines masks for the ASC device interrupts*/
-/* change these macroses if it's necessary */
-#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */
-
-#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */
-#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */
-#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */
-#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/
-
-/* interrupt controller access macros */
-#define ASC_INTERRUPTS_ENABLE(X) \
- *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
-#define ASC_INTERRUPTS_DISABLE(X) \
- *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
-#define ASC_INTERRUPTS_CLEAR(X) \
- *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
-
-/* CLC register's bits and bitfields */
-#define ASCCLC_DISR 0x00000001
-#define ASCCLC_DISS 0x00000002
-#define ASCCLC_RMCMASK 0x0000FF00
-#define ASCCLC_RMCOFFSET 8
-
-/* CON register's bits and bitfields */
-#define ASCCON_MODEMASK 0x0007
- #define ASCCON_M_8SYNC 0x0
- #define ASCCON_M_8ASYNC 0x1
- #define ASCCON_M_8IRDAASYNC 0x2
- #define ASCCON_M_7ASYNCPAR 0x3
- #define ASCCON_M_9ASYNC 0x4
- #define ASCCON_M_8WAKEUPASYNC 0x5
- #define ASCCON_M_8ASYNCPAR 0x7
-#define ASCCON_STP 0x0008
-#define ASCCON_REN 0x0010
-#define ASCCON_PEN 0x0020
-#define ASCCON_FEN 0x0040
-#define ASCCON_OEN 0x0080
-#define ASCCON_PE 0x0100
-#define ASCCON_FE 0x0200
-#define ASCCON_OE 0x0400
-#define ASCCON_FDE 0x0800
-#define ASCCON_ODD 0x1000
-#define ASCCON_BRS 0x2000
-#define ASCCON_LB 0x4000
-#define ASCCON_R 0x8000
-
-/* WHBCON register's bits and bitfields */
-#define ASCWHBCON_CLRREN 0x0010
-#define ASCWHBCON_SETREN 0x0020
-#define ASCWHBCON_CLRPE 0x0100
-#define ASCWHBCON_CLRFE 0x0200
-#define ASCWHBCON_CLROE 0x0400
-#define ASCWHBCON_SETPE 0x0800
-#define ASCWHBCON_SETFE 0x1000
-#define ASCWHBCON_SETOE 0x2000
-
-/* ABCON register's bits and bitfields */
-#define ASCABCON_ABEN 0x0001
-#define ASCABCON_AUREN 0x0002
-#define ASCABCON_ABSTEN 0x0004
-#define ASCABCON_ABDETEN 0x0008
-#define ASCABCON_FCDETEN 0x0010
-#define ASCABCON_EMMASK 0x0300
- #define ASCABCON_EMOFF 8
- #define ASCABCON_EM_DISAB 0x0
- #define ASCABCON_EM_DURAB 0x1
- #define ASCABCON_EM_ALWAYS 0x2
-#define ASCABCON_TXINV 0x0400
-#define ASCABCON_RXINV 0x0800
-
-/* FDV register mask, offset and bitfields*/
-#define ASCFDV_VALUE_MASK 0x000001FF
-
-/* WHBABCON register's bits and bitfields */
-#define ASCWHBABCON_SETABEN 0x0001
-#define ASCWHBABCON_CLRABEN 0x0002
-
-/* ABSTAT register's bits and bitfields */
-#define ASCABSTAT_FCSDET 0x0001
-#define ASCABSTAT_FCCDET 0x0002
-#define ASCABSTAT_SCSDET 0x0004
-#define ASCABSTAT_SCCDET 0x0008
-#define ASCABSTAT_DETWAIT 0x0010
-
-/* WHBABSTAT register's bits and bitfields */
-#define ASCWHBABSTAT_CLRFCSDET 0x0001
-#define ASCWHBABSTAT_SETFCSDET 0x0002
-#define ASCWHBABSTAT_CLRFCCDET 0x0004
-#define ASCWHBABSTAT_SETFCCDET 0x0008
-#define ASCWHBABSTAT_CLRSCSDET 0x0010
-#define ASCWHBABSTAT_SETSCSDET 0x0020
-#define ASCWHBABSTAT_SETSCCDET 0x0040
-#define ASCWHBABSTAT_CLRSCCDET 0x0080
-#define ASCWHBABSTAT_CLRDETWAIT 0x0100
-#define ASCWHBABSTAT_SETDETWAIT 0x0200
-
-/* TXFCON register's bits and bitfields */
-#define ASCTXFCON_TXFEN 0x0001
-#define ASCTXFCON_TXFFLU 0x0002
-#define ASCTXFCON_TXTMEN 0x0004
-#define ASCTXFCON_TXFITLMASK 0x3F00
-#define ASCTXFCON_TXFITLOFF 8
-
-/* RXFCON register's bits and bitfields */
-#define ASCRXFCON_RXFEN 0x0001
-#define ASCRXFCON_RXFFLU 0x0002
-#define ASCRXFCON_RXTMEN 0x0004
-#define ASCRXFCON_RXFITLMASK 0x3F00
-#define ASCRXFCON_RXFITLOFF 8
-
-/* FSTAT register's bits and bitfields */
-#define ASCFSTAT_RXFFLMASK 0x003F
-#define ASCFSTAT_TXFFLMASK 0x3F00
-#define ASCFSTAT_TXFFLOFF 8
-
-#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
-
-typedef struct /* incaAsc_t */
-{
- volatile unsigned long asc_clc; /*0x0000*/
- volatile unsigned long asc_pisel; /*0x0004*/
- volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/
- volatile unsigned long asc_con; /*0x0010*/
- volatile unsigned long asc_bg; /*0x0014*/
- volatile unsigned long asc_fdv; /*0x0018*/
- volatile unsigned long asc_pmw; /* not used */ /*0x001C*/
- volatile unsigned long asc_tbuf; /*0x0020*/
- volatile unsigned long asc_rbuf; /*0x0024*/
- volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/
- volatile unsigned long asc_abcon; /*0x0030*/
- volatile unsigned long asc_abstat; /* not used */ /*0x0034*/
- volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/
- volatile unsigned long asc_rxfcon; /*0x0040*/
- volatile unsigned long asc_txfcon; /*0x0044*/
- volatile unsigned long asc_fstat; /*0x0048*/
- volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/
- volatile unsigned long asc_whbcon; /*0x0050*/
- volatile unsigned long asc_whbabcon; /*0x0054*/
- volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/
-
-} incaAsc_t;
-
-#endif /* __INCincaAscSioh */
diff --git a/arch/mips/cpu/mips32/incaip/config.mk b/arch/mips/cpu/mips32/incaip/config.mk
deleted file mode 100644
index 5c89129..0000000
--- a/arch/mips/cpu/mips32/incaip/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2011
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mtune=4kc
diff --git a/arch/mips/cpu/mips32/incaip/incaip_clock.c b/arch/mips/cpu/mips32/incaip/incaip_clock.c
deleted file mode 100644
index efada9f..0000000
--- a/arch/mips/cpu/mips32/incaip/incaip_clock.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/inca-ip.h>
-
-
-/*******************************************************************************
-*
-* get_cpuclk - returns the frequency of the CPU.
-*
-* Gets the value directly from the INCA-IP hardware.
-*
-* RETURNS:
-* 150.000.000 for 150 MHz
-* 133.333.333 for 133 MHz (= 400MHz/3)
-* 100.000.000 for 100 MHz (= 400MHz/4)
-* NOTE:
-* This functions should be used by the hardware driver to get the correct
-* frequency of the CPU. Don't use the macros, which are set to init the CPU
-* frequency in the ROM code.
-*/
-uint incaip_get_cpuclk (void)
-{
- /*-------------------------------------------------------------------------*/
- /* CPU Clock Input Multiplexer (MUX I) */
- /* Multiplexer MUX I selects the maximum input clock to the CPU. */
- /*-------------------------------------------------------------------------*/
- if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) &
- INCA_IP_CGU_CGU_MUXCR_MUXI) {
- /* MUX I set to 150 MHz clock */
- return 150000000;
- } else {
- /* MUX I set to 100/133 MHz clock */
- if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) {
- /* Division value is 1/3, maximum CPU operating */
- /* frequency is 133.3 MHz */
- return 133333333;
- } else {
- /* Division value is 1/4, maximum CPU operating */
- /* frequency is 100 MHz */
- return 100000000;
- }
- }
-}
-
-/*******************************************************************************
-*
-* get_fpiclk - returns the frequency of the FPI bus.
-*
-* Gets the value directly from the INCA-IP hardware.
-*
-* RETURNS: Frquency in Hz
-*
-* NOTE:
-* This functions should be used by the hardware driver to get the correct
-* frequency of the CPU. Don't use the macros, which are set to init the CPU
-* frequency in the ROM code.
-* The calculation for the
-*/
-uint incaip_get_fpiclk (void)
-{
- uint clkCPU;
-
- clkCPU = incaip_get_cpuclk ();
-
- switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) {
- case 0x4:
- return clkCPU >> 1; /* devided by 2 */
- break;
- case 0x8:
- return clkCPU >> 2; /* devided by 4 */
- break;
- default:
- return clkCPU;
- break;
- }
-}
-
-int incaip_set_cpuclk (void)
-{
- extern void ebu_init(long);
- extern void cgu_init(long);
- extern void sdram_init(long);
- char tmp[64];
- ulong cpuclk;
-
- if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) {
- cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
- cgu_init (cpuclk);
- ebu_init (cpuclk);
- sdram_init (cpuclk);
- }
-
- return 0;
-}
diff --git a/arch/mips/cpu/mips32/incaip/incaip_wdt.S b/arch/mips/cpu/mips32/incaip/incaip_wdt.S
deleted file mode 100644
index b15320a..0000000
--- a/arch/mips/cpu/mips32/incaip/incaip_wdt.S
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * INCA-IP Watchdog timer management code.
- *
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <config.h>
-#include <asm/regdef.h>
-
-
-#define WD_BASE 0xb8000000
-#define WD_CON0(value) 0x0020(value)
-#define WD_CON1(value) 0x0024(value)
-#define WD_DISABLE 0x00000008
-#define WD_ENABLE 0x00000000
-#define WD_WRITE_PW 0xFFFC00F8
-#define WD_WRITE_ENDINIT 0xFFFC00F3
-#define WD_WRITE_INIT 0xFFFC00F2
-
-
- .globl disable_incaip_wdt
-disable_incaip_wdt:
- li t0, WD_BASE
-
- /* Calculate password.
- */
- lw t2, WD_CON1(t0)
- and t2, 0xC
-
- lw t3, WD_CON0(t0)
- and t3, 0xFFFFFF01
-
- or t3, t2
- or t3, 0xF0
-
- sw t3, WD_CON0(t0) /* write password */
-
- /* Clear ENDINIT.
- */
- li t1, WD_WRITE_INIT
- sw t1, WD_CON0(t0)
-
-
- li t1, WD_DISABLE
- sw t1, WD_CON1(t0) /* disable watchdog */
- li t1, WD_WRITE_PW
- sw t1, WD_CON0(t0) /* write password */
- li t1, WD_WRITE_ENDINIT
- sw t1, WD_CON0(t0) /* end command */
-
- jr ra
- nop
diff --git a/arch/mips/cpu/mips32/interrupts.c b/arch/mips/cpu/mips32/interrupts.c
index a7e2ed0..275fcf5 100644
--- a/arch/mips/cpu/mips32/interrupts.c
+++ b/arch/mips/cpu/mips32/interrupts.c
@@ -7,6 +7,11 @@
#include <common.h>
+int interrupt_init(void)
+{
+ return 0;
+}
+
void enable_interrupts(void)
{
}
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c
index a7e2ed0..275fcf5 100644
--- a/arch/mips/cpu/mips64/interrupts.c
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -7,6 +7,11 @@
#include <common.h>
+int interrupt_init(void)
+{
+ return 0;
+}
+
void enable_interrupts(void)
{
}
diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds
index 16a9d6a..e504ea7 100644
--- a/arch/mips/cpu/u-boot.lds
+++ b/arch/mips/cpu/u-boot.lds
@@ -53,6 +53,7 @@ SECTIONS
. = ALIGN(4);
__image_copy_end = .;
+ __init_end = .;
.rel.dyn : {
__rel_dyn_start = .;
@@ -60,27 +61,7 @@ SECTIONS
__rel_dyn_end = .;
}
- .deadcode : {
- /*
- * Workaround for a binutils feature (or bug?).
- *
- * The GNU ld from binutils puts the dynamic relocation
- * entries into the .rel.dyn section. Sometimes it
- * allocates more dynamic relocation entries than it needs
- * and the unused slots are set to R_MIPS_NONE entries.
- *
- * However the size of the .rel.dyn section in the ELF
- * section header does not cover the unused entries, so
- * objcopy removes those during stripping.
- *
- * Create a small section here to avoid that.
- */
- LONG(0xffffffff);
- }
-
- .dynsym : {
- *(.dynsym)
- }
+ _end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
@@ -91,15 +72,39 @@ SECTIONS
__bss_end = .;
}
- /DISCARD/ : {
+ .dynsym _end : {
+ *(.dynsym)
+ }
+
+ .dynbss : {
*(.dynbss)
+ }
+
+ .dynstr : {
*(.dynstr)
+ }
+
+ .dynamic : {
*(.dynamic)
+ }
+
+ .plt : {
+ *(.plt)
+ }
+
+ .interp : {
*(.interp)
+ }
+
+ .gnu : {
+ *(.gnu*)
+ }
+
+ .MIPS.stubs : {
+ *(.MIPS.stubs)
+ }
+
+ .hash : {
*(.hash)
- *(.gnu.*)
- *(.plt)
- *(.got.plt)
- *(.rel.plt)
}
}
diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
deleted file mode 100644
index 57714d0..0000000
--- a/arch/mips/cpu/xburst/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = cpu.o timer.o jz_serial.o
-obj-$(CONFIG_JZ4740) += jz4740.o
diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk
deleted file mode 100644
index b8e53e5..0000000
--- a/arch/mips/cpu/xburst/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=mips32
-PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS += -m elf32btsmip
-else
-PLATFORM_LDFLAGS += -m elf32ltsmip
-endif
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
- -T $(srctree)/examples/standalone/mips.lds
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
deleted file mode 100644
index 1fdaa32..0000000
--- a/arch/mips/cpu/xburst/cpu.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- * (C) Copyright 2011
- * Xiangfu Liu <xiangfu@openmobilefree.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mipsregs.h>
-#include <asm/cacheops.h>
-#include <asm/reboot.h>
-#include <asm/io.h>
-#include <asm/jz4740.h>
-
-#define cache_op(op, addr) \
- __asm__ __volatile__( \
- ".set push\n" \
- ".set noreorder\n" \
- ".set mips3\n" \
- "cache %0, %1\n" \
- ".set pop\n" \
- : \
- : "i" (op), "R" (*(unsigned char *)(addr)))
-
-void __attribute__((weak)) _machine_restart(void)
-{
- struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
- struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
- u16 tmp;
-
- /* wdt_select_extalclk() */
- tmp = readw(&wdt->tcsr);
- tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN);
- tmp |= WDT_TCSR_EXT_EN;
- writew(tmp, &wdt->tcsr);
-
- /* wdt_select_clk_div64() */
- tmp = readw(&wdt->tcsr);
- tmp &= ~WDT_TCSR_PRESCALE_MASK;
- tmp |= WDT_TCSR_PRESCALE64,
- writew(tmp, &wdt->tcsr);
-
- writew(100, &wdt->tdr); /* wdt_set_data(100) */
- writew(0, &wdt->tcnt); /* wdt_set_count(0); */
- writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
- writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
-
- while (1)
- ;
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- _machine_restart();
-
- fprintf(stderr, "*** reset failed ***\n");
- return 0;
-}
-
-void flush_cache(ulong start_addr, ulong size)
-{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
-
- for (; addr <= aend; addr += lsize) {
- cache_op(HIT_WRITEBACK_INV_D, addr);
- cache_op(HIT_INVALIDATE_I, addr);
- }
-}
-
-void flush_dcache_range(ulong start_addr, ulong stop)
-{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (stop - 1) & ~(lsize - 1);
-
- for (; addr <= aend; addr += lsize)
- cache_op(HIT_WRITEBACK_INV_D, addr);
-}
-
-void invalidate_dcache_range(ulong start_addr, ulong stop)
-{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (stop - 1) & ~(lsize - 1);
-
- for (; addr <= aend; addr += lsize)
- cache_op(HIT_INVALIDATE_D, addr);
-}
-
-void flush_icache_all(void)
-{
- u32 addr, t = 0;
-
- __asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */
- __asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */
-
- for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
- addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(INDEX_STORE_TAG_I, addr);
- }
-
- /* invalidate btb */
- __asm__ __volatile__(
- ".set mips32\n\t"
- "mfc0 %0, $16, 7\n\t"
- "nop\n\t"
- "ori %0,2\n\t"
- "mtc0 %0, $16, 7\n\t"
- ".set mips2\n\t"
- :
- : "r" (t));
-}
-
-void flush_dcache_all(void)
-{
- u32 addr;
-
- for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
- addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(INDEX_WRITEBACK_INV_D, addr);
- }
-
- __asm__ __volatile__("sync");
-}
-
-void flush_cache_all(void)
-{
- flush_dcache_all();
- flush_icache_all();
-}
diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
deleted file mode 100644
index 30f35bd..0000000
--- a/arch/mips/cpu/xburst/jz4740.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Jz4740 common routines
- * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/jz4740.h>
-
-void enable_interrupts(void)
-{
-}
-
-int disable_interrupts(void)
-{
- return 0;
-}
-
-/*
- * PLL output clock = EXTAL * NF / (NR * NO)
- * NF = FD + 2, NR = RD + 2
- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
- */
-void pll_init(void)
-{
- struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
-
- register unsigned int cfcr, plcr1;
- int n2FR[33] = {
- 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
- 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
- 9
- };
- int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
- int nf, pllout2;
-
- cfcr = CPM_CPCCR_CLKOEN |
- CPM_CPCCR_PCS |
- (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
- (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
- (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
- (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
- (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
-
- pllout2 = (cfcr & CPM_CPCCR_PCS) ?
- CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
-
- /* Init USB Host clock, pllout2 must be n*48MHz */
- writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
-
- nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
- plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
- (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
- (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
- (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
- CPM_CPPCR_PLLEN; /* enable PLL */
-
- /* init PLL */
- writel(cfcr, &cpm->cpccr);
- writel(plcr1, &cpm->cppcr);
-}
-
-void sdram_init(void)
-{
- struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
-
- register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
-
- unsigned int cas_latency_sdmr[2] = {
- EMC_SDMR_CAS_2,
- EMC_SDMR_CAS_3,
- };
-
- unsigned int cas_latency_dmcr[2] = {
- 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
- 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
- };
-
- int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
-
- cpu_clk = CONFIG_SYS_CPU_SPEED;
- mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
-
- writel(0, &emc->bcr); /* Disable bus release */
- writew(0, &emc->rtcsr); /* Disable clock for counting */
-
- /* Fault DMCR value for mode register setting*/
-#define SDRAM_ROW0 11
-#define SDRAM_COL0 8
-#define SDRAM_BANK40 0
-
- dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
- ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
- (SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
- (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
- EMC_DMCR_EPIN |
- cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
-
- /* Basic DMCR value */
- dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
- ((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
- (SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
- (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
- EMC_DMCR_EPIN |
- cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
-
- /* SDRAM timimg */
- ns = 1000000000 / mem_clk;
- tmp = SDRAM_TRAS / ns;
- if (tmp < 4)
- tmp = 4;
- if (tmp > 11)
- tmp = 11;
- dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
- tmp = SDRAM_RCD / ns;
-
- if (tmp > 3)
- tmp = 3;
- dmcr |= tmp << EMC_DMCR_RCD_BIT;
- tmp = SDRAM_TPC / ns;
-
- if (tmp > 7)
- tmp = 7;
- dmcr |= tmp << EMC_DMCR_TPC_BIT;
- tmp = SDRAM_TRWL / ns;
-
- if (tmp > 3)
- tmp = 3;
- dmcr |= tmp << EMC_DMCR_TRWL_BIT;
- tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
-
- if (tmp > 14)
- tmp = 14;
- dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
-
- /* SDRAM mode value */
- sdmode = EMC_SDMR_BT_SEQ |
- EMC_SDMR_OM_NORMAL |
- EMC_SDMR_BL_4 |
- cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
-
- /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
- writel(dmcr, &emc->dmcr);
- writeb(0, JZ4740_EMC_SDMR0 | sdmode);
-
- /* Wait for precharge, > 200us */
- tmp = (cpu_clk / 1000000) * 1000;
- while (tmp--)
- ;
-
- /* Stage 2. Enable auto-refresh */
- writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr);
-
- tmp = SDRAM_TREF / ns;
- tmp = tmp / 64 + 1;
- if (tmp > 0xff)
- tmp = 0xff;
- writew(tmp, &emc->rtcor);
- writew(0, &emc->rtcnt);
- /* Divisor is 64, CKO/64 */
- writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
-
- /* Wait for number of auto-refresh cycles */
- tmp = (cpu_clk / 1000000) * 1000;
- while (tmp--)
- ;
-
- /* Stage 3. Mode Register Set */
- writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
- writeb(0, JZ4740_EMC_SDMR0 | sdmode);
-
- /* Set back to basic DMCR value */
- writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
-
- /* everything is ok now */
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void calc_clocks(void)
-{
- unsigned int pllout;
- unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
-
- pllout = __cpm_get_pllout();
-
- gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
- gd->arch.sys_clk = pllout / div[__cpm_get_hdiv()];
- gd->arch.per_clk = pllout / div[__cpm_get_pdiv()];
- gd->mem_clk = pllout / div[__cpm_get_mdiv()];
- gd->arch.dev_clk = CONFIG_SYS_EXTAL;
-}
-
-void rtc_init(void)
-{
- struct jz4740_rtc *rtc = (struct jz4740_rtc *)JZ4740_RTC_BASE;
-
- while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
- ;
- writel(readl(&rtc->rcr) | RTC_RCR_AE, &rtc->rcr); /* enable alarm */
-
- while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
- ;
- writel(0x00007fff, &rtc->rgr); /* type value */
-
- while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
- ;
- writel(0x0000ffe0, &rtc->hwfcr); /* Power on delay 2s */
-
- while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
- ;
- writel(0x00000fe0, &rtc->hrcr); /* reset delay 125ms */
-}
-
-/* U-Boot common routines */
-phys_size_t initdram(int board_type)
-{
- struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
- u32 dmcr;
- u32 rows, cols, dw, banks;
- ulong size;
-
- dmcr = readl(&emc->dmcr);
- rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
- cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
- dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
- banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
-
- size = (1 << (rows + cols)) * dw * banks;
-
- return size;
-}
diff --git a/arch/mips/cpu/xburst/jz_serial.c b/arch/mips/cpu/xburst/jz_serial.c
deleted file mode 100644
index 9184223..0000000
--- a/arch/mips/cpu/xburst/jz_serial.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Jz4740 UART support
- * Copyright (c) 2011
- * Qi Hardware, Xiangfu Liu <xiangfu@sharism.cc>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/jz4740.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-/*
- * serial_init - initialize a channel
- *
- * This routine initializes the number of data bits, parity
- * and set the selected baud rate. Interrupts are disabled.
- * Set the modem control signals if the option is selected.
- *
- * RETURNS: N/A
- */
-struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE;
-
-static int jz_serial_init(void)
-{
- /* Disable port interrupts while changing hardware */
- writeb(0, &uart->dlhr_ier);
-
- /* Disable UART unit function */
- writeb(~UART_FCR_UUE, &uart->iir_fcr);
-
- /* Set both receiver and transmitter in UART mode (not SIR) */
- writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr);
-
- /*
- * Set databits, stopbits and parity.
- * (8-bit data, 1 stopbit, no parity)
- */
- writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr);
-
- /* Set baud rate */
- serial_setbrg();
-
- /* Enable UART unit, enable and clear FIFO */
- writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
- &uart->iir_fcr);
-
- return 0;
-}
-
-static void jz_serial_setbrg(void)
-{
- u32 baud_div, tmp;
-
- baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
-
- tmp = readb(&uart->lcr);
- tmp |= UART_LCR_DLAB;
- writeb(tmp, &uart->lcr);
-
- writeb((baud_div >> 8) & 0xff, &uart->dlhr_ier);
- writeb(baud_div & 0xff, &uart->rbr_thr_dllr);
-
- tmp &= ~UART_LCR_DLAB;
- writeb(tmp, &uart->lcr);
-}
-
-static int jz_serial_tstc(void)
-{
- if (readb(&uart->lsr) & UART_LSR_DR)
- return 1;
-
- return 0;
-}
-
-static void jz_serial_putc(const char c)
-{
- if (c == '\n')
- serial_putc('\r');
-
- /* Wait for fifo to shift out some bytes */
- while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60))
- ;
-
- writeb((u8)c, &uart->rbr_thr_dllr);
-}
-
-static int jz_serial_getc(void)
-{
- while (!serial_tstc())
- ;
-
- return readb(&uart->rbr_thr_dllr);
-}
-
-static struct serial_device jz_serial_drv = {
- .name = "jz_serial",
- .start = jz_serial_init,
- .stop = NULL,
- .setbrg = jz_serial_setbrg,
- .putc = jz_serial_putc,
- .puts = default_serial_puts,
- .getc = jz_serial_getc,
- .tstc = jz_serial_tstc,
-};
-
-void jz_serial_initialize(void)
-{
- serial_register(&jz_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &jz_serial_drv;
-}
diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
deleted file mode 100644
index 10dffb4..0000000
--- a/arch/mips/cpu/xburst/start.S
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Startup Code for MIPS32 XBURST CPU-core
- *
- * Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
- .set noreorder
-
- .globl _start
- .text
-_start:
- /* Initialize $gp */
- bal 1f
- nop
- .word _gp
-1:
- lw gp, 0(ra)
-
- /* Set up temporary stack */
- li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-
- la t9, board_init_f
- jr t9
- nop
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * a0 = addr_sp
- * a1 = gd
- * a2 = destination address
- */
- .globl relocate_code
- .ent relocate_code
-relocate_code:
- move sp, a0 # set new stack pointer
-
- move s0, a1 # save gd in s0
- move s2, a2 # save destination address in s2
-
- li t0, CONFIG_SYS_MONITOR_BASE
- sub s1, s2, t0 # s1 <-- relocation offset
-
- la t3, in_ram
- lw t2, -12(t3) # t2 <-- __image_copy_end
- move t1, a2
-
- add gp, s1 # adjust gp
-
- /*
- * t0 = source address
- * t1 = target address
- * t2 = source end address
- */
-1:
- lw t3, 0(t0)
- sw t3, 0(t1)
- addu t0, 4
- blt t0, t2, 1b
- addu t1, 4
-
- /* If caches were enabled, we would have to flush them here. */
-
- /* flush d-cache */
- li t0, KSEG0
- addi t1, t0, CONFIG_SYS_DCACHE_SIZE
-2:
- cache INDEX_WRITEBACK_INV_D, 0(t0)
- bne t0, t1, 2b
- addi t0, CONFIG_SYS_CACHELINE_SIZE
-
- sync
-
- /* flush i-cache */
- li t0, KSEG0
- addi t1, t0, CONFIG_SYS_ICACHE_SIZE
-3:
- cache INDEX_INVALIDATE_I, 0(t0)
- bne t0, t1, 3b
- addi t0, CONFIG_SYS_CACHELINE_SIZE
-
- /* Invalidate BTB */
- mfc0 t0, CP0_CONFIG, 7
- nop
- ori t0, 2
- mtc0 t0, CP0_CONFIG, 7
- nop
-
- /* Jump to where we've relocated ourselves */
- addi t0, s2, in_ram - _start
- jr t0
- nop
-
- .word __rel_dyn_end
- .word __rel_dyn_start
- .word __image_copy_end
- .word _GLOBAL_OFFSET_TABLE_
- .word num_got_entries
-
-in_ram:
- /*
- * Now we want to update GOT.
- *
- * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
- * generated by GNU ld. Skip these reserved entries from relocation.
- */
- lw t3, -4(t0) # t3 <-- num_got_entries
- lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
- add t8, s1 # t8 now holds relocated _G_O_T_
- addi t8, t8, 8 # skipping first two entries
- li t2, 2
-1:
- lw t1, 0(t8)
- beqz t1, 2f
- add t1, s1
- sw t1, 0(t8)
-2:
- addi t2, 1
- blt t2, t3, 1b
- addi t8, 4
-
- /* Update dynamic relocations */
- lw t1, -16(t0) # t1 <-- __rel_dyn_start
- lw t2, -20(t0) # t2 <-- __rel_dyn_end
-
- b 2f # skip first reserved entry
- addi t1, 8
-
-1:
- lw t8, -4(t1) # t8 <-- relocation info
-
- li t3, 3
- bne t8, t3, 2f # skip non R_MIPS_REL32 entries
- nop
-
- lw t3, -8(t1) # t3 <-- location to fix up in FLASH
-
- lw t8, 0(t3) # t8 <-- original pointer
- add t8, s1 # t8 <-- adjusted pointer
-
- add t3, s1 # t3 <-- location to fix up in RAM
- sw t8, 0(t3)
-
-2:
- blt t1, t2, 1b
- addi t1, 8 # each rel.dyn entry is 8 bytes
-
- /*
- * Clear BSS
- *
- * GOT is now relocated. Thus __bss_start and __bss_end can be
- * accessed directly via $gp.
- */
- la t1, __bss_start # t1 <-- __bss_start
- la t2, __bss_end # t2 <-- __bss_end
-
-1:
- sw zero, 0(t1)
- blt t1, t2, 1b
- addi t1, 4
-
- move a0, s0 # a0 <-- gd
- la t9, board_init_r
- jr t9
- move a1, s2
-
- .end relocate_code
diff --git a/arch/mips/cpu/xburst/timer.c b/arch/mips/cpu/xburst/timer.c
deleted file mode 100644
index 79f34f0..0000000
--- a/arch/mips/cpu/xburst/timer.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * Copyright (c) 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-
-#include <asm/jz4740.h>
-
-#define TIMER_CHAN 0
-#define TIMER_FDATA 0xffff /* Timer full data value */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
-
-void reset_timer_masked(void)
-{
- /* reset time */
- gd->arch.lastinc = readl(&tcu->tcnt0);
- gd->arch.tbl = 0;
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = readl(&tcu->tcnt0);
-
- if (gd->arch.lastinc <= now)
- gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */
- else {
- /* we have an overflow ... */
- gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc;
- }
-
- gd->arch.lastinc = now;
-
- return gd->arch.tbl;
-}
-
-void udelay_masked(unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- /* normalize */
- if (usec >= 1000) {
- tmo = usec / 1000;
- tmo *= CONFIG_SYS_HZ;
- tmo /= 1000;
- } else {
- if (usec > 1) {
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= 1000*1000;
- } else
- tmo = 1;
- }
-
- endtime = get_timer_masked() + tmo;
-
- do {
- ulong now = get_timer_masked();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-int timer_init(void)
-{
- writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
-
- writel(0, &tcu->tcnt0);
- writel(0, &tcu->tdhr0);
- writel(TIMER_FDATA, &tcu->tdfr0);
-
- /* mask irqs */
- writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);
- writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
- writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */
-
- gd->arch.lastinc = 0;
- gd->arch.tbl = 0;
-
- return 0;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
- gd->arch.tbl = t;
-}
-
-void __udelay(unsigned long usec)
-{
- ulong tmo, tmp;
-
- /* normalize */
- if (usec >= 1000) {
- tmo = usec / 1000;
- tmo *= CONFIG_SYS_HZ;
- tmo /= 1000;
- } else {
- if (usec >= 1) {
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= 1000 * 1000;
- } else
- tmo = 1;
- }
-
- /* check for rollover during this delay */
- tmp = get_timer(0);
- if ((tmp + tmo) < tmp)
- reset_timer_masked(); /* timer would roll over */
- else
- tmo += tmp;
-
- while (get_timer_masked() < tmo)
- ;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/mips/include/asm/inca-ip.h b/arch/mips/include/asm/inca-ip.h
deleted file mode 100644
index 5f03e2a..0000000
--- a/arch/mips/include/asm/inca-ip.h
+++ /dev/null
@@ -1,2430 +0,0 @@
-/******************************************************************************
- Copyright (c) 2002, Infineon Technologies. All rights reserved.
-
- No Warranty
- Because the program is licensed free of charge, there is no warranty for
- the program, to the extent permitted by applicable law. Except when
- otherwise stated in writing the copyright holders and/or other parties
- provide the program "as is" without warranty of any kind, either
- expressed or implied, including, but not limited to, the implied
- warranties of merchantability and fitness for a particular purpose. The
- entire risk as to the quality and performance of the program is with
- you. should the program prove defective, you assume the cost of all
- necessary servicing, repair or correction.
-
- In no event unless required by applicable law or agreed to in writing
- will any copyright holder, or any other party who may modify and/or
- redistribute the program as permitted above, be liable to you for
- damages, including any general, special, incidental or consequential
- damages arising out of the use or inability to use the program
- (including but not limited to loss of data or data being rendered
- inaccurate or losses sustained by you or third parties or a failure of
- the program to operate with any other programs), even if such holder or
- other party has been advised of the possibility of such damages.
-******************************************************************************/
-
-
-/***********************************************************************/
-/* Module : WDT register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_WDT (0xB8000000)
-/***********************************************************************/
-
-
-/***Reset Status Register Power On***/
-#define INCA_IP_WDT_RST_SR ((volatile u32*)(INCA_IP_WDT+ 0x0014))
-
-/***Reset Request Register***/
-#define INCA_IP_WDT_RST_REQ ((volatile u32*)(INCA_IP_WDT+ 0x0010))
-#define INCA_IP_WDT_RST_REQ_SWBOOT (1 << 24)
-#define INCA_IP_WDT_RST_REQ_SWCFG (1 << 16)
-#define INCA_IP_WDT_RST_REQ_RRPHY (1 << 5)
-#define INCA_IP_WDT_RST_REQ_RRHSP (1 << 4)
-#define INCA_IP_WDT_RST_REQ_RRFPI (1 << 3)
-#define INCA_IP_WDT_RST_REQ_RREXT (1 << 2)
-#define INCA_IP_WDT_RST_REQ_RRDSP (1 << 1)
-#define INCA_IP_WDT_RST_REQ_RRCPU (1 << 0)
-
-/***NMI Status Register***/
-#define INCA_IP_WDT_NMISR ((volatile u32*)(INCA_IP_WDT+ 0x002C))
-#define INCA_IP_WDT_NMISR_NMIWDT (1 << 2)
-#define INCA_IP_WDT_NMISR_NMIPLL (1 << 1)
-#define INCA_IP_WDT_NMISR_NMIEXT (1 << 0)
-
-/***Manufacturer Identification Register***/
-#define INCA_IP_WDT_MANID ((volatile u32*)(INCA_IP_WDT+ 0x0070))
-#define INCA_IP_WDT_MANID_MANUF (value) (((( 1 << 11) - 1) & (value)) << 5)
-
-/***Chip Identification Register***/
-#define INCA_IP_WDT_CHIPID ((volatile u32*)(INCA_IP_WDT+ 0x0074))
-#define INCA_IP_WDT_CHIPID_VERSION (value) (((( 1 << 4) - 1) & (value)) << 28)
-#define INCA_IP_WDT_CHIPID_PART_NUMBER (value) (((( 1 << 16) - 1) & (value)) << 12)
-#define INCA_IP_WDT_CHIPID_MANID (value) (((( 1 << 11) - 1) & (value)) << 1)
-
-/***Redesign Tracing Identification Register***/
-#define INCA_IP_WDT_RTID ((volatile u32*)(INCA_IP_WDT+ 0x0078))
-#define INCA_IP_WDT_RTID_LC (1 << 15)
-#define INCA_IP_WDT_RTID_RIX (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Watchdog Timer Control Register 0***/
-#define INCA_IP_WDT_WDT_CON0 ((volatile u32*)(INCA_IP_WDT+ 0x0020))
-
-/***Watchdog Timer Control Register 1***/
-#define INCA_IP_WDT_WDT_CON1 ((volatile u32*)(INCA_IP_WDT+ 0x0024))
-#define INCA_IP_WDT_WDT_CON1_WDTDR (1 << 3)
-#define INCA_IP_WDT_WDT_CON1_WDTIR (1 << 2)
-
-/***Watchdog Timer Status Register***/
-#define INCA_IP_WDT_WDT_SR ((volatile u32*)(INCA_IP_WDT+ 0x0028))
-#define INCA_IP_WDT_WDT_SR_WDTTIM (value) (((( 1 << 16) - 1) & (value)) << 16)
-#define INCA_IP_WDT_WDT_SR_WDTPR (1 << 5)
-#define INCA_IP_WDT_WDT_SR_WDTTO (1 << 4)
-#define INCA_IP_WDT_WDT_SR_WDTDS (1 << 3)
-#define INCA_IP_WDT_WDT_SR_WDTIS (1 << 2)
-#define INCA_IP_WDT_WDT_SR_WDTOE (1 << 1)
-#define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0)
-
-/***********************************************************************/
-/* Module : CGU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_CGU (0xBF107000)
-/***********************************************************************/
-
-
-/***CGU PLL1 Control Register***/
-#define INCA_IP_CGU_CGU_PLL1CR ((volatile u32*)(INCA_IP_CGU+ 0x0008))
-#define INCA_IP_CGU_CGU_PLL1CR_SWRST (1 << 31)
-#define INCA_IP_CGU_CGU_PLL1CR_EN (1 << 30)
-#define INCA_IP_CGU_CGU_PLL1CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16)
-#define INCA_IP_CGU_CGU_PLL1CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***CGU PLL0 Control Register***/
-#define INCA_IP_CGU_CGU_PLL0CR ((volatile u32*)(INCA_IP_CGU+ 0x0000))
-#define INCA_IP_CGU_CGU_PLL0CR_SWRST (1 << 31)
-#define INCA_IP_CGU_CGU_PLL0CR_EN (1 << 30)
-#define INCA_IP_CGU_CGU_PLL0CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16)
-#define INCA_IP_CGU_CGU_PLL0CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***CGU PLL0 Status Register***/
-#define INCA_IP_CGU_CGU_PLL0SR ((volatile u32*)(INCA_IP_CGU+ 0x0004))
-#define INCA_IP_CGU_CGU_PLL0SR_LOCK (1 << 31)
-#define INCA_IP_CGU_CGU_PLL0SR_RCF (1 << 29)
-#define INCA_IP_CGU_CGU_PLL0SR_PLLBYP (1 << 15)
-
-/***CGU PLL1 Status Register***/
-#define INCA_IP_CGU_CGU_PLL1SR ((volatile u32*)(INCA_IP_CGU+ 0x000C))
-#define INCA_IP_CGU_CGU_PLL1SR_LOCK (1 << 31)
-#define INCA_IP_CGU_CGU_PLL1SR_RCF (1 << 29)
-#define INCA_IP_CGU_CGU_PLL1SR_PLLBYP (1 << 15)
-
-/***CGU Divider Control Register***/
-#define INCA_IP_CGU_CGU_DIVCR ((volatile u32*)(INCA_IP_CGU+ 0x0010))
-
-/***CGU Multiplexer Control Register***/
-#define INCA_IP_CGU_CGU_MUXCR ((volatile u32*)(INCA_IP_CGU+ 0x0014))
-#define INCA_IP_CGU_CGU_MUXCR_SWRST (1 << 31)
-#define INCA_IP_CGU_CGU_MUXCR_MUXII (1 << 1)
-#define INCA_IP_CGU_CGU_MUXCR_MUXI (1 << 0)
-
-/***CGU Fractional Divider Control Register***/
-#define INCA_IP_CGU_CGU_FDCR ((volatile u32*)(INCA_IP_CGU+ 0x0018))
-#define INCA_IP_CGU_CGU_FDCR_FDEN (1 << 31)
-#define INCA_IP_CGU_CGU_FDCR_INTEGER (value) (((( 1 << 12) - 1) & (value)) << 16)
-#define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : PMU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_PMU (0xBF102000)
-/***********************************************************************/
-
-
-/***PM Global Enable Register***/
-#define INCA_IP_PMU_PM_GEN ((volatile u32*)(INCA_IP_PMU+ 0x0000))
-#define INCA_IP_PMU_PM_GEN_EN16 (1 << 16)
-#define INCA_IP_PMU_PM_GEN_EN15 (1 << 15)
-#define INCA_IP_PMU_PM_GEN_EN14 (1 << 14)
-#define INCA_IP_PMU_PM_GEN_EN13 (1 << 13)
-#define INCA_IP_PMU_PM_GEN_EN12 (1 << 12)
-#define INCA_IP_PMU_PM_GEN_EN11 (1 << 11)
-#define INCA_IP_PMU_PM_GEN_EN10 (1 << 10)
-#define INCA_IP_PMU_PM_GEN_EN9 (1 << 9)
-#define INCA_IP_PMU_PM_GEN_EN8 (1 << 8)
-#define INCA_IP_PMU_PM_GEN_EN7 (1 << 7)
-#define INCA_IP_PMU_PM_GEN_EN6 (1 << 6)
-#define INCA_IP_PMU_PM_GEN_EN5 (1 << 5)
-#define INCA_IP_PMU_PM_GEN_EN4 (1 << 4)
-#define INCA_IP_PMU_PM_GEN_EN3 (1 << 3)
-#define INCA_IP_PMU_PM_GEN_EN2 (1 << 2)
-#define INCA_IP_PMU_PM_GEN_EN0 (1 << 0)
-
-/***PM Power Down Enable Register***/
-#define INCA_IP_PMU_PM_PDEN ((volatile u32*)(INCA_IP_PMU+ 0x0008))
-#define INCA_IP_PMU_PM_PDEN_EN16 (1 << 16)
-#define INCA_IP_PMU_PM_PDEN_EN15 (1 << 15)
-#define INCA_IP_PMU_PM_PDEN_EN14 (1 << 14)
-#define INCA_IP_PMU_PM_PDEN_EN13 (1 << 13)
-#define INCA_IP_PMU_PM_PDEN_EN12 (1 << 12)
-#define INCA_IP_PMU_PM_PDEN_EN11 (1 << 11)
-#define INCA_IP_PMU_PM_PDEN_EN10 (1 << 10)
-#define INCA_IP_PMU_PM_PDEN_EN9 (1 << 9)
-#define INCA_IP_PMU_PM_PDEN_EN8 (1 << 8)
-#define INCA_IP_PMU_PM_PDEN_EN7 (1 << 7)
-#define INCA_IP_PMU_PM_PDEN_EN5 (1 << 5)
-#define INCA_IP_PMU_PM_PDEN_EN4 (1 << 4)
-#define INCA_IP_PMU_PM_PDEN_EN3 (1 << 3)
-#define INCA_IP_PMU_PM_PDEN_EN2 (1 << 2)
-#define INCA_IP_PMU_PM_PDEN_EN0 (1 << 0)
-
-/***PM Wake-Up from Power Down Register***/
-#define INCA_IP_PMU_PM_WUP ((volatile u32*)(INCA_IP_PMU+ 0x0010))
-#define INCA_IP_PMU_PM_WUP_WUP16 (1 << 16)
-#define INCA_IP_PMU_PM_WUP_WUP15 (1 << 15)
-#define INCA_IP_PMU_PM_WUP_WUP14 (1 << 14)
-#define INCA_IP_PMU_PM_WUP_WUP13 (1 << 13)
-#define INCA_IP_PMU_PM_WUP_WUP12 (1 << 12)
-#define INCA_IP_PMU_PM_WUP_WUP11 (1 << 11)
-#define INCA_IP_PMU_PM_WUP_WUP10 (1 << 10)
-#define INCA_IP_PMU_PM_WUP_WUP9 (1 << 9)
-#define INCA_IP_PMU_PM_WUP_WUP8 (1 << 8)
-#define INCA_IP_PMU_PM_WUP_WUP7 (1 << 7)
-#define INCA_IP_PMU_PM_WUP_WUP5 (1 << 5)
-#define INCA_IP_PMU_PM_WUP_WUP4 (1 << 4)
-#define INCA_IP_PMU_PM_WUP_WUP3 (1 << 3)
-#define INCA_IP_PMU_PM_WUP_WUP2 (1 << 2)
-#define INCA_IP_PMU_PM_WUP_WUP0 (1 << 0)
-
-/***PM Control Register***/
-#define INCA_IP_PMU_PM_CR ((volatile u32*)(INCA_IP_PMU+ 0x0014))
-#define INCA_IP_PMU_PM_CR_AWEN (1 << 31)
-#define INCA_IP_PMU_PM_CR_SWRST (1 << 30)
-#define INCA_IP_PMU_PM_CR_SWCR (1 << 2)
-#define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : BCU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_BCU (0xB8000100)
-/***********************************************************************/
-
-
-/***BCU Control Register (0010H)***/
-#define INCA_IP_BCU_BCU_CON ((volatile u32*)(INCA_IP_BCU+ 0x0010))
-#define INCA_IP_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_BCU_BCU_CON_SPE (1 << 19)
-#define INCA_IP_BCU_BCU_CON_PSE (1 << 18)
-#define INCA_IP_BCU_BCU_CON_DBG (1 << 16)
-#define INCA_IP_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***BCU Error Control Capture Register (0020H)***/
-#define INCA_IP_BCU_BCU_ECON ((volatile u32*)(INCA_IP_BCU+ 0x0020))
-#define INCA_IP_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24)
-#define INCA_IP_BCU_BCU_ECON_RDN (1 << 23)
-#define INCA_IP_BCU_BCU_ECON_WRN (1 << 22)
-#define INCA_IP_BCU_BCU_ECON_SVM (1 << 21)
-#define INCA_IP_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19)
-#define INCA_IP_BCU_BCU_ECON_ABT (1 << 18)
-#define INCA_IP_BCU_BCU_ECON_RDY (1 << 17)
-#define INCA_IP_BCU_BCU_ECON_TOUT (1 << 16)
-#define INCA_IP_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0)
-#define INCA_IP_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28)
-
-/***BCU Error Address Capture Register (0024 H)***/
-#define INCA_IP_BCU_BCU_EADD ((volatile u32*)(INCA_IP_BCU+ 0x0024))
-#define INCA_IP_BCU_BCU_EADD_FPIADR
-
-/***BCU Error Data Capture Register (0028H)***/
-#define INCA_IP_BCU_BCU_EDAT ((volatile u32*)(INCA_IP_BCU+ 0x0028))
-#define INCA_IP_BCU_BCU_EDAT_FPIDAT
-
-/***********************************************************************/
-/* Module : MBC register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_MBC (0xBF103000)
-/***********************************************************************/
-
-
-/***Mailbox CPU Configuration Register***/
-#define INCA_IP_MBC_MBC_CFG ((volatile u32*)(INCA_IP_MBC+ 0x0080))
-#define INCA_IP_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_MBC_MBC_CFG_RES (1 << 5)
-#define INCA_IP_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1)
-#define INCA_IP_MBC_MBC_CFG_SIZE (1 << 0)
-
-/***Mailbox CPU Interrupt Status Register***/
-#define INCA_IP_MBC_MBC_ISR ((volatile u32*)(INCA_IP_MBC+ 0x0084))
-#define INCA_IP_MBC_MBC_ISR_B3DA (1 << 31)
-#define INCA_IP_MBC_MBC_ISR_B2DA (1 << 30)
-#define INCA_IP_MBC_MBC_ISR_B1E (1 << 29)
-#define INCA_IP_MBC_MBC_ISR_B0E (1 << 28)
-#define INCA_IP_MBC_MBC_ISR_WDT (1 << 27)
-#define INCA_IP_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask Register***/
-#define INCA_IP_MBC_MBC_MSK ((volatile u32*)(INCA_IP_MBC+ 0x0088))
-#define INCA_IP_MBC_MBC_MSK_B3DA (1 << 31)
-#define INCA_IP_MBC_MBC_MSK_B2DA (1 << 30)
-#define INCA_IP_MBC_MBC_MSK_B1E (1 << 29)
-#define INCA_IP_MBC_MBC_MSK_B0E (1 << 28)
-#define INCA_IP_MBC_MBC_MSK_WDT (1 << 27)
-#define INCA_IP_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask 01 Register***/
-#define INCA_IP_MBC_MBC_MSK01 ((volatile u32*)(INCA_IP_MBC+ 0x008C))
-#define INCA_IP_MBC_MBC_MSK01_B3DA (1 << 31)
-#define INCA_IP_MBC_MBC_MSK01_B2DA (1 << 30)
-#define INCA_IP_MBC_MBC_MSK01_B1E (1 << 29)
-#define INCA_IP_MBC_MBC_MSK01_B0E (1 << 28)
-#define INCA_IP_MBC_MBC_MSK01_WDT (1 << 27)
-#define INCA_IP_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask 10 Register***/
-#define INCA_IP_MBC_MBC_MSK10 ((volatile u32*)(INCA_IP_MBC+ 0x0090))
-#define INCA_IP_MBC_MBC_MSK10_B3DA (1 << 31)
-#define INCA_IP_MBC_MBC_MSK10_B2DA (1 << 30)
-#define INCA_IP_MBC_MBC_MSK10_B1E (1 << 29)
-#define INCA_IP_MBC_MBC_MSK10_B0E (1 << 28)
-#define INCA_IP_MBC_MBC_MSK10_WDT (1 << 27)
-#define INCA_IP_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Short Command Register***/
-#define INCA_IP_MBC_MBC_CMD ((volatile u32*)(INCA_IP_MBC+ 0x0094))
-#define INCA_IP_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***Mailbox CPU Input Data of Buffer 0***/
-#define INCA_IP_MBC_MBC_ID0 ((volatile u32*)(INCA_IP_MBC+ 0x0000))
-#define INCA_IP_MBC_MBC_ID0_INDATA
-
-/***Mailbox CPU Input Data of Buffer 1***/
-#define INCA_IP_MBC_MBC_ID1 ((volatile u32*)(INCA_IP_MBC+ 0x0020))
-#define INCA_IP_MBC_MBC_ID1_INDATA
-
-/***Mailbox CPU Output Data of Buffer 2***/
-#define INCA_IP_MBC_MBC_OD2 ((volatile u32*)(INCA_IP_MBC+ 0x0040))
-#define INCA_IP_MBC_MBC_OD2_OUTDATA
-
-/***Mailbox CPU Output Data of Buffer 3***/
-#define INCA_IP_MBC_MBC_OD3 ((volatile u32*)(INCA_IP_MBC+ 0x0060))
-#define INCA_IP_MBC_MBC_OD3_OUTDATA
-
-/***Mailbox CPU Control Register of Buffer 0***/
-#define INCA_IP_MBC_MBC_CR0 ((volatile u32*)(INCA_IP_MBC+ 0x0004))
-#define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 1***/
-#define INCA_IP_MBC_MBC_CR1 ((volatile u32*)(INCA_IP_MBC+ 0x0024))
-#define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 2***/
-#define INCA_IP_MBC_MBC_CR2 ((volatile u32*)(INCA_IP_MBC+ 0x0044))
-#define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 3***/
-#define INCA_IP_MBC_MBC_CR3 ((volatile u32*)(INCA_IP_MBC+ 0x0064))
-#define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Free Space of Buffer 0***/
-#define INCA_IP_MBC_MBC_FS0 ((volatile u32*)(INCA_IP_MBC+ 0x0008))
-#define INCA_IP_MBC_MBC_FS0_FS
-
-/***Mailbox CPU Free Space of Buffer 1***/
-#define INCA_IP_MBC_MBC_FS1 ((volatile u32*)(INCA_IP_MBC+ 0x0028))
-#define INCA_IP_MBC_MBC_FS1_FS
-
-/***Mailbox CPU Free Space of Buffer 2***/
-#define INCA_IP_MBC_MBC_FS2 ((volatile u32*)(INCA_IP_MBC+ 0x0048))
-#define INCA_IP_MBC_MBC_FS2_FS
-
-/***Mailbox CPU Free Space of Buffer 3***/
-#define INCA_IP_MBC_MBC_FS3 ((volatile u32*)(INCA_IP_MBC+ 0x0068))
-#define INCA_IP_MBC_MBC_FS3_FS
-
-/***Mailbox CPU Data Available in Buffer 0***/
-#define INCA_IP_MBC_MBC_DA0 ((volatile u32*)(INCA_IP_MBC+ 0x000C))
-#define INCA_IP_MBC_MBC_DA0_DA
-
-/***Mailbox CPU Data Available in Buffer 1***/
-#define INCA_IP_MBC_MBC_DA1 ((volatile u32*)(INCA_IP_MBC+ 0x002C))
-#define INCA_IP_MBC_MBC_DA1_DA
-
-/***Mailbox CPU Data Available in Buffer 2***/
-#define INCA_IP_MBC_MBC_DA2 ((volatile u32*)(INCA_IP_MBC+ 0x004C))
-#define INCA_IP_MBC_MBC_DA2_DA
-
-/***Mailbox CPU Data Available in Buffer 3***/
-#define INCA_IP_MBC_MBC_DA3 ((volatile u32*)(INCA_IP_MBC+ 0x006C))
-#define INCA_IP_MBC_MBC_DA3_DA
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_IABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0010))
-#define INCA_IP_MBC_MBC_IABS0_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_IABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0030))
-#define INCA_IP_MBC_MBC_IABS1_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_IABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0050))
-#define INCA_IP_MBC_MBC_IABS2_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_IABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0070))
-#define INCA_IP_MBC_MBC_IABS3_IABS
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_ITMP0 ((volatile u32*)(INCA_IP_MBC+ 0x0014))
-#define INCA_IP_MBC_MBC_ITMP0_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_ITMP1 ((volatile u32*)(INCA_IP_MBC+ 0x0034))
-#define INCA_IP_MBC_MBC_ITMP1_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_ITMP2 ((volatile u32*)(INCA_IP_MBC+ 0x0054))
-#define INCA_IP_MBC_MBC_ITMP2_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_ITMP3 ((volatile u32*)(INCA_IP_MBC+ 0x0074))
-#define INCA_IP_MBC_MBC_ITMP3_ITMP
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_OABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0018))
-#define INCA_IP_MBC_MBC_OABS0_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_OABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0038))
-#define INCA_IP_MBC_MBC_OABS1_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_OABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0058))
-#define INCA_IP_MBC_MBC_OABS2_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_OABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0078))
-#define INCA_IP_MBC_MBC_OABS3_OABS
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_OTMP0 ((volatile u32*)(INCA_IP_MBC+ 0x001C))
-#define INCA_IP_MBC_MBC_OTMP0_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_OTMP1 ((volatile u32*)(INCA_IP_MBC+ 0x003C))
-#define INCA_IP_MBC_MBC_OTMP1_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_OTMP2 ((volatile u32*)(INCA_IP_MBC+ 0x005C))
-#define INCA_IP_MBC_MBC_OTMP2_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_OTMP3 ((volatile u32*)(INCA_IP_MBC+ 0x007C))
-#define INCA_IP_MBC_MBC_OTMP3_OTMP
-
-/***DSP Control Register***/
-#define INCA_IP_MBC_DCTRL ((volatile u32*)(INCA_IP_MBC+ 0x00A0))
-#define INCA_IP_MBC_DCTRL_BA (1 << 0)
-#define INCA_IP_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1)
-#define INCA_IP_MBC_DCTRL_IDL (1 << 4)
-#define INCA_IP_MBC_DCTRL_RES (1 << 15)
-
-/***DSP Status Register***/
-#define INCA_IP_MBC_DSTA ((volatile u32*)(INCA_IP_MBC+ 0x00A4))
-#define INCA_IP_MBC_DSTA_IDLE (1 << 0)
-#define INCA_IP_MBC_DSTA_PD (1 << 1)
-
-/***DSP Test 1 Register***/
-#define INCA_IP_MBC_DTST1 ((volatile u32*)(INCA_IP_MBC+ 0x00A8))
-#define INCA_IP_MBC_DTST1_ABORT (1 << 0)
-#define INCA_IP_MBC_DTST1_HWF32 (1 << 1)
-#define INCA_IP_MBC_DTST1_HWF4M (1 << 2)
-#define INCA_IP_MBC_DTST1_HWFOP (1 << 3)
-
-/***********************************************************************/
-/* Module : Switch register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_Switch (0xBF104000)
-/***********************************************************************/
-
-
-/***Unknown Destination Register***/
-#define INCA_IP_Switch_UN_DEST ((volatile u32*)(INCA_IP_Switch+ 0x0000))
-#define INCA_IP_Switch_UN_DEST_CB (1 << 8)
-#define INCA_IP_Switch_UN_DEST_LB (1 << 7)
-#define INCA_IP_Switch_UN_DEST_PB (1 << 6)
-#define INCA_IP_Switch_UN_DEST_CM (1 << 5)
-#define INCA_IP_Switch_UN_DEST_LM (1 << 4)
-#define INCA_IP_Switch_UN_DEST_PM (1 << 3)
-#define INCA_IP_Switch_UN_DEST_CU (1 << 2)
-#define INCA_IP_Switch_UN_DEST_LU (1 << 1)
-#define INCA_IP_Switch_UN_DEST_PU (1 << 0)
-
-/***VLAN Control Register***/
-#define INCA_IP_Switch_VLAN_CTRL ((volatile u32*)(INCA_IP_Switch+ 0x0004))
-#define INCA_IP_Switch_VLAN_CTRL_SC (1 << 6)
-#define INCA_IP_Switch_VLAN_CTRL_SL (1 << 5)
-#define INCA_IP_Switch_VLAN_CTRL_SP (1 << 4)
-#define INCA_IP_Switch_VLAN_CTRL_TC (1 << 3)
-#define INCA_IP_Switch_VLAN_CTRL_TL (1 << 2)
-#define INCA_IP_Switch_VLAN_CTRL_TP (1 << 1)
-#define INCA_IP_Switch_VLAN_CTRL_VA (1 << 0)
-
-/***PC VLAN Configuration Register***/
-#define INCA_IP_Switch_PC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0008))
-#define INCA_IP_Switch_PC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_Switch_PC_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0)
-
-/***LAN VLAN Configuration Register***/
-#define INCA_IP_Switch_LAN_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x000C))
-#define INCA_IP_Switch_LAN_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0)
-
-/***CPU VLAN Configuration Register***/
-#define INCA_IP_Switch_CPU_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0010))
-#define INCA_IP_Switch_CPU_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0)
-
-/***Priority CoS Mapping Register***/
-#define INCA_IP_Switch_PRI_CoS ((volatile u32*)(INCA_IP_Switch+ 0x0014))
-#define INCA_IP_Switch_PRI_CoS_P7 (1 << 7)
-#define INCA_IP_Switch_PRI_CoS_P6 (1 << 6)
-#define INCA_IP_Switch_PRI_CoS_P5 (1 << 5)
-#define INCA_IP_Switch_PRI_CoS_P4 (1 << 4)
-#define INCA_IP_Switch_PRI_CoS_P3 (1 << 3)
-#define INCA_IP_Switch_PRI_CoS_P2 (1 << 2)
-#define INCA_IP_Switch_PRI_CoS_P1 (1 << 1)
-#define INCA_IP_Switch_PRI_CoS_P0 (1 << 0)
-
-/***Spanning Tree Port Status Register***/
-#define INCA_IP_Switch_ST_PT ((volatile u32*)(INCA_IP_Switch+ 0x0018))
-#define INCA_IP_Switch_ST_PT_CPS (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_Switch_ST_PT_LPS (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_Switch_ST_PT_PPS (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***ARL Control Register***/
-#define INCA_IP_Switch_ARL_CTL ((volatile u32*)(INCA_IP_Switch+ 0x001C))
-#define INCA_IP_Switch_ARL_CTL_CHCC (1 << 15)
-#define INCA_IP_Switch_ARL_CTL_CHCL (1 << 14)
-#define INCA_IP_Switch_ARL_CTL_CHCP (1 << 13)
-#define INCA_IP_Switch_ARL_CTL_CC (1 << 12)
-#define INCA_IP_Switch_ARL_CTL_CL (1 << 11)
-#define INCA_IP_Switch_ARL_CTL_CP (1 << 10)
-#define INCA_IP_Switch_ARL_CTL_CG (1 << 9)
-#define INCA_IP_Switch_ARL_CTL_PS (1 << 8)
-#define INCA_IP_Switch_ARL_CTL_MRO (1 << 7)
-#define INCA_IP_Switch_ARL_CTL_SRC (1 << 6)
-#define INCA_IP_Switch_ARL_CTL_ATS (1 << 5)
-#define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value) (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_ARL_CTL_MAF (1 << 1)
-#define INCA_IP_Switch_ARL_CTL_ENL (1 << 0)
-#define INCA_IP_Switch_ARL_CTL_Res (value) (((( 1 << 19) - 1) & (value)) << 13)
-
-/***CPU Access Control Register***/
-#define INCA_IP_Switch_CPU_ACTL ((volatile u32*)(INCA_IP_Switch+ 0x0020))
-#define INCA_IP_Switch_CPU_ACTL_RA (1 << 31)
-#define INCA_IP_Switch_CPU_ACTL_RW (1 << 30)
-#define INCA_IP_Switch_CPU_ACTL_Res (value) (((( 1 << 21) - 1) & (value)) << 9)
-#define INCA_IP_Switch_CPU_ACTL_AVA (1 << 8)
-#define INCA_IP_Switch_CPU_ACTL_IDX (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***CPU Access Data Register 1***/
-#define INCA_IP_Switch_DATA1 ((volatile u32*)(INCA_IP_Switch+ 0x0024))
-#define INCA_IP_Switch_DATA1_Data (value) (((( 1 << 24) - 1) & (value)) << 0)
-
-/***CPU Access Data Register 2***/
-#define INCA_IP_Switch_DATA2 ((volatile u32*)(INCA_IP_Switch+ 0x0028))
-#define INCA_IP_Switch_DATA2_Data
-
-/***CPU Port Control Register***/
-#define INCA_IP_Switch_CPU_PCTL ((volatile u32*)(INCA_IP_Switch+ 0x002C))
-#define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value) (((( 1 << 3) - 1) & (value)) << 11)
-#define INCA_IP_Switch_CPU_PCTL_DAC (1 << 10)
-#define INCA_IP_Switch_CPU_PCTL_MA_STATE (value) (((( 1 << 3) - 1) & (value)) << 7)
-#define INCA_IP_Switch_CPU_PCTL_MAM (1 << 6)
-#define INCA_IP_Switch_CPU_PCTL_MA_Ports (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_Switch_CPU_PCTL_MAC (1 << 2)
-#define INCA_IP_Switch_CPU_PCTL_EML (1 << 1)
-#define INCA_IP_Switch_CPU_PCTL_EDL (1 << 0)
-#define INCA_IP_Switch_CPU_PCTL_Res (value) (((( 1 << 18) - 1) & (value)) << 14)
-
-/***DSCP CoS Mapping Register 1***/
-#define INCA_IP_Switch_DSCP_COS1 ((volatile u32*)(INCA_IP_Switch+ 0x0030))
-#define INCA_IP_Switch_DSCP_COS1_DSCP
-
-/***DSCP CoS Mapping Register 1***/
-#define INCA_IP_Switch_DSCP_COS2 ((volatile u32*)(INCA_IP_Switch+ 0x0034))
-#define INCA_IP_Switch_DSCP_COS2_DSCP
-
-/***PC WFQ Control Register***/
-#define INCA_IP_Switch_PC_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0080))
-#define INCA_IP_Switch_PC_WFQ_CTL_P1 (1 << 9)
-#define INCA_IP_Switch_PC_WFQ_CTL_P0 (1 << 8)
-#define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5)
-#define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***PC TX Control Register***/
-#define INCA_IP_Switch_PC_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0084))
-#define INCA_IP_Switch_PC_TX_CTL_ELR (1 << 1)
-#define INCA_IP_Switch_PC_TX_CTL_EER (1 << 0)
-
-/***LAN WFQ Control Register***/
-#define INCA_IP_Switch_LAN_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0100))
-#define INCA_IP_Switch_LAN_WFQ_CTL_P1 (1 << 9)
-#define INCA_IP_Switch_LAN_WFQ_CTL_P0 (1 << 8)
-#define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5)
-#define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***LAN TX Control Register***/
-#define INCA_IP_Switch_LAN_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0104))
-#define INCA_IP_Switch_LAN_TX_CTL_ELR (1 << 1)
-#define INCA_IP_Switch_LAN_TX_CTL_EER (1 << 0)
-
-/***CPU WFQ Control Register***/
-#define INCA_IP_Switch_CPU_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0180))
-#define INCA_IP_Switch_CPU_WFQ_CTL_P1 (1 << 9)
-#define INCA_IP_Switch_CPU_WFQ_CTL_P0 (1 << 8)
-#define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5)
-#define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***PM PC RX Watermark Register***/
-#define INCA_IP_Switch_PC_WM ((volatile u32*)(INCA_IP_Switch+ 0x0200))
-#define INCA_IP_Switch_PC_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_PC_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_PC_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_PC_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM LAN RX Watermark Register***/
-#define INCA_IP_Switch_LAN_WM ((volatile u32*)(INCA_IP_Switch+ 0x0204))
-#define INCA_IP_Switch_LAN_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_LAN_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_LAN_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_LAN_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM CPU RX Watermark Register***/
-#define INCA_IP_Switch_CPU_WM ((volatile u32*)(INCA_IP_Switch+ 0x0208))
-#define INCA_IP_Switch_CPU_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_CPU_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_CPU_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_CPU_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM CPU RX Watermark Register***/
-#define INCA_IP_Switch_GBL_WM ((volatile u32*)(INCA_IP_Switch+ 0x020C))
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM Control Register***/
-#define INCA_IP_Switch_PM_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0210))
-#define INCA_IP_Switch_PM_CTL_GDN (1 << 3)
-#define INCA_IP_Switch_PM_CTL_CDN (1 << 2)
-#define INCA_IP_Switch_PM_CTL_LDN (1 << 1)
-#define INCA_IP_Switch_PM_CTL_PDN (1 << 0)
-
-/***PM Header Control Register***/
-#define INCA_IP_Switch_PMAC_HD_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0280))
-#define INCA_IP_Switch_PMAC_HD_CTL_RL2 (1 << 21)
-#define INCA_IP_Switch_PMAC_HD_CTL_RC (1 << 20)
-#define INCA_IP_Switch_PMAC_HD_CTL_CM (1 << 19)
-#define INCA_IP_Switch_PMAC_HD_CTL_CV (1 << 18)
-#define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value) (((( 1 << 16) - 1) & (value)) << 2)
-#define INCA_IP_Switch_PMAC_HD_CTL_TAG (1 << 1)
-#define INCA_IP_Switch_PMAC_HD_CTL_ADD (1 << 0)
-
-/***PM Source Address Register 1***/
-#define INCA_IP_Switch_PMAC_SA1 ((volatile u32*)(INCA_IP_Switch+ 0x0284))
-#define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***PM Source Address Register 2***/
-#define INCA_IP_Switch_PMAC_SA2 ((volatile u32*)(INCA_IP_Switch+ 0x0288))
-#define INCA_IP_Switch_PMAC_SA2_SA_31_0
-
-/***PM Dest Address Register 1***/
-#define INCA_IP_Switch_PMAC_DA1 ((volatile u32*)(INCA_IP_Switch+ 0x028C))
-#define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***PM Dest Address Register 2***/
-#define INCA_IP_Switch_PMAC_DA2 ((volatile u32*)(INCA_IP_Switch+ 0x0290))
-#define INCA_IP_Switch_PMAC_DA2_DA_31_0
-
-/***PM VLAN Register***/
-#define INCA_IP_Switch_PMAC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0294))
-#define INCA_IP_Switch_PMAC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 13)
-#define INCA_IP_Switch_PMAC_VLAN_CFI (1 << 12)
-#define INCA_IP_Switch_PMAC_VLAN_VLANID (value) (((( 1 << 12) - 1) & (value)) << 0)
-
-/***PM TX IPG Counter Register***/
-#define INCA_IP_Switch_PMAC_TX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x0298))
-#define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM RX IPG Counter Register***/
-#define INCA_IP_Switch_PMAC_RX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x029C))
-#define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Mirror Register***/
-#define INCA_IP_Switch_MRR ((volatile u32*)(INCA_IP_Switch+ 0x0300))
-#define INCA_IP_Switch_MRR_MRR (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_Switch_MRR_EC (1 << 5)
-#define INCA_IP_Switch_MRR_EL (1 << 4)
-#define INCA_IP_Switch_MRR_EP (1 << 3)
-#define INCA_IP_Switch_MRR_IC (1 << 2)
-#define INCA_IP_Switch_MRR_IL (1 << 1)
-#define INCA_IP_Switch_MRR_IP (1 << 0)
-
-/***Packet Length Register***/
-#define INCA_IP_Switch_PKT_LEN ((volatile u32*)(INCA_IP_Switch+ 0x0304))
-#define INCA_IP_Switch_PKT_LEN_ADD (1 << 11)
-#define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value) (((( 1 << 11) - 1) & (value)) << 0)
-
-/***MDIO Access Register***/
-#define INCA_IP_Switch_MDIO_ACC ((volatile u32*)(INCA_IP_Switch+ 0x0480))
-#define INCA_IP_Switch_MDIO_ACC_RA (1 << 31)
-#define INCA_IP_Switch_MDIO_ACC_RW (1 << 30)
-#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21)
-#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16)
-#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***Ethernet PHY Register***/
-#define INCA_IP_Switch_EPHY ((volatile u32*)(INCA_IP_Switch+ 0x0484))
-#define INCA_IP_Switch_EPHY_SL (1 << 7)
-#define INCA_IP_Switch_EPHY_SP (1 << 6)
-#define INCA_IP_Switch_EPHY_LL (1 << 5)
-#define INCA_IP_Switch_EPHY_LP (1 << 4)
-#define INCA_IP_Switch_EPHY_DL (1 << 3)
-#define INCA_IP_Switch_EPHY_DP (1 << 2)
-#define INCA_IP_Switch_EPHY_PL (1 << 1)
-#define INCA_IP_Switch_EPHY_PP (1 << 0)
-
-/***Pause Write Enable Register***/
-#define INCA_IP_Switch_PWR_EN ((volatile u32*)(INCA_IP_Switch+ 0x0488))
-#define INCA_IP_Switch_PWR_EN_PL (1 << 1)
-#define INCA_IP_Switch_PWR_EN_PP (1 << 0)
-
-/***MDIO Configuration Register***/
-#define INCA_IP_Switch_MDIO_CFG ((volatile u32*)(INCA_IP_Switch+ 0x048C))
-#define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14)
-#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9)
-#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value) (((( 1 << 5) - 1) & (value)) << 4)
-#define INCA_IP_Switch_MDIO_CFG_UEP (1 << 3)
-#define INCA_IP_Switch_MDIO_CFG_PS (1 << 2)
-#define INCA_IP_Switch_MDIO_CFG_PT (1 << 1)
-#define INCA_IP_Switch_MDIO_CFG_UMM (1 << 0)
-
-/***Clock Configuration Register***/
-#define INCA_IP_Switch_CLK_CFG ((volatile u32*)(INCA_IP_Switch+ 0x0500))
-#define INCA_IP_Switch_CLK_CFG_ARL_ID (1 << 9)
-#define INCA_IP_Switch_CLK_CFG_CPU_ID (1 << 8)
-#define INCA_IP_Switch_CLK_CFG_LAN_ID (1 << 7)
-#define INCA_IP_Switch_CLK_CFG_PC_ID (1 << 6)
-#define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5)
-
-/***********************************************************************/
-/* Module : SSC1 register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_SSC1 (0xB8000500)
-/***********************************************************************/
-
-
-/***Control Register (Programming Mode)***/
-#define INCA_IP_SSC1_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC1+ 0x0010))
-#define INCA_IP_SSC1_SCC_CON_PRG_EN (1 << 15)
-#define INCA_IP_SSC1_SCC_CON_PRG_MS (1 << 14)
-#define INCA_IP_SSC1_SCC_CON_PRG_AREN (1 << 12)
-#define INCA_IP_SSC1_SCC_CON_PRG_BEN (1 << 11)
-#define INCA_IP_SSC1_SCC_CON_PRG_PEN (1 << 10)
-#define INCA_IP_SSC1_SCC_CON_PRG_REN (1 << 9)
-#define INCA_IP_SSC1_SCC_CON_PRG_TEN (1 << 8)
-#define INCA_IP_SSC1_SCC_CON_PRG_LB (1 << 7)
-#define INCA_IP_SSC1_SCC_CON_PRG_PO (1 << 6)
-#define INCA_IP_SSC1_SCC_CON_PRG_PH (1 << 5)
-#define INCA_IP_SSC1_SCC_CON_PRG_HB (1 << 4)
-#define INCA_IP_SSC1_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SCC Control Register (Operating Mode)***/
-#define INCA_IP_SSC1_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC1+ 0x0010))
-#define INCA_IP_SSC1_SCC_CON_OPR_EN (1 << 15)
-#define INCA_IP_SSC1_SCC_CON_OPR_MS (1 << 14)
-#define INCA_IP_SSC1_SCC_CON_OPR_BSY (1 << 12)
-#define INCA_IP_SSC1_SCC_CON_OPR_BE (1 << 11)
-#define INCA_IP_SSC1_SCC_CON_OPR_PE (1 << 10)
-#define INCA_IP_SSC1_SCC_CON_OPR_RE (1 << 9)
-#define INCA_IP_SSC1_SCC_CON_OPR_TE (1 << 8)
-#define INCA_IP_SSC1_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SSC Write Hardware Modified Control Register***/
-#define INCA_IP_SSC1_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC1+ 0x0040))
-#define INCA_IP_SSC1_SSC_WHBCON_SETBE (1 << 15)
-#define INCA_IP_SSC1_SSC_WHBCON_SETPE (1 << 14)
-#define INCA_IP_SSC1_SSC_WHBCON_SETRE (1 << 13)
-#define INCA_IP_SSC1_SSC_WHBCON_SETTE (1 << 12)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRBE (1 << 11)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRPE (1 << 10)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRRE (1 << 9)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRTE (1 << 8)
-
-/***SSC Baudrate Timer Reload Register***/
-#define INCA_IP_SSC1_SSC_BR ((volatile u32*)(INCA_IP_SSC1+ 0x0014))
-#define INCA_IP_SSC1_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Transmitter Buffer Register***/
-#define INCA_IP_SSC1_SSC_TB ((volatile u32*)(INCA_IP_SSC1+ 0x0020))
-#define INCA_IP_SSC1_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receiver Buffer Register***/
-#define INCA_IP_SSC1_SSC_RB ((volatile u32*)(INCA_IP_SSC1+ 0x0024))
-#define INCA_IP_SSC1_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receive FIFO Control Register***/
-#define INCA_IP_SSC1_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0030))
-#define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_RXFCON_RXTMEN (1 << 2)
-#define INCA_IP_SSC1_SSC_RXFCON_RXFLU (1 << 1)
-#define INCA_IP_SSC1_SSC_RXFCON_RXFEN (1 << 0)
-
-/***SSC Transmit FIFO Control Register***/
-#define INCA_IP_SSC1_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0034))
-#define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_TXFCON_TXTMEN (1 << 2)
-#define INCA_IP_SSC1_SSC_TXFCON_TXFLU (1 << 1)
-#define INCA_IP_SSC1_SSC_TXFCON_TXFEN (1 << 0)
-
-/***SSC FIFO Status Register***/
-#define INCA_IP_SSC1_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC1+ 0x0038))
-#define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0)
-
-/***SSC Clock Control Register***/
-#define INCA_IP_SSC1_SSC_CLC ((volatile u32*)(INCA_IP_SSC1+ 0x0000))
-#define INCA_IP_SSC1_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_CLC_DISS (1 << 1)
-#define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0)
-
-/***********************************************************************/
-/* Module : SSC2 register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_SSC2 (0xB8000600)
-/***********************************************************************/
-
-
-/***Control Register (Programming Mode)***/
-#define INCA_IP_SSC2_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC2+ 0x0010))
-#define INCA_IP_SSC2_SCC_CON_PRG_EN (1 << 15)
-#define INCA_IP_SSC2_SCC_CON_PRG_MS (1 << 14)
-#define INCA_IP_SSC2_SCC_CON_PRG_AREN (1 << 12)
-#define INCA_IP_SSC2_SCC_CON_PRG_BEN (1 << 11)
-#define INCA_IP_SSC2_SCC_CON_PRG_PEN (1 << 10)
-#define INCA_IP_SSC2_SCC_CON_PRG_REN (1 << 9)
-#define INCA_IP_SSC2_SCC_CON_PRG_TEN (1 << 8)
-#define INCA_IP_SSC2_SCC_CON_PRG_LB (1 << 7)
-#define INCA_IP_SSC2_SCC_CON_PRG_PO (1 << 6)
-#define INCA_IP_SSC2_SCC_CON_PRG_PH (1 << 5)
-#define INCA_IP_SSC2_SCC_CON_PRG_HB (1 << 4)
-#define INCA_IP_SSC2_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SCC Control Register (Operating Mode)***/
-#define INCA_IP_SSC2_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC2+ 0x0010))
-#define INCA_IP_SSC2_SCC_CON_OPR_EN (1 << 15)
-#define INCA_IP_SSC2_SCC_CON_OPR_MS (1 << 14)
-#define INCA_IP_SSC2_SCC_CON_OPR_BSY (1 << 12)
-#define INCA_IP_SSC2_SCC_CON_OPR_BE (1 << 11)
-#define INCA_IP_SSC2_SCC_CON_OPR_PE (1 << 10)
-#define INCA_IP_SSC2_SCC_CON_OPR_RE (1 << 9)
-#define INCA_IP_SSC2_SCC_CON_OPR_TE (1 << 8)
-#define INCA_IP_SSC2_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SSC Write Hardware Modified Control Register***/
-#define INCA_IP_SSC2_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC2+ 0x0040))
-#define INCA_IP_SSC2_SSC_WHBCON_SETBE (1 << 15)
-#define INCA_IP_SSC2_SSC_WHBCON_SETPE (1 << 14)
-#define INCA_IP_SSC2_SSC_WHBCON_SETRE (1 << 13)
-#define INCA_IP_SSC2_SSC_WHBCON_SETTE (1 << 12)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRBE (1 << 11)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRPE (1 << 10)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRRE (1 << 9)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRTE (1 << 8)
-
-/***SSC Baudrate Timer Reload Register***/
-#define INCA_IP_SSC2_SSC_BR ((volatile u32*)(INCA_IP_SSC2+ 0x0014))
-#define INCA_IP_SSC2_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Transmitter Buffer Register***/
-#define INCA_IP_SSC2_SSC_TB ((volatile u32*)(INCA_IP_SSC2+ 0x0020))
-#define INCA_IP_SSC2_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receiver Buffer Register***/
-#define INCA_IP_SSC2_SSC_RB ((volatile u32*)(INCA_IP_SSC2+ 0x0024))
-#define INCA_IP_SSC2_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receive FIFO Control Register***/
-#define INCA_IP_SSC2_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0030))
-#define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_RXFCON_RXTMEN (1 << 2)
-#define INCA_IP_SSC2_SSC_RXFCON_RXFLU (1 << 1)
-#define INCA_IP_SSC2_SSC_RXFCON_RXFEN (1 << 0)
-
-/***SSC Transmit FIFO Control Register***/
-#define INCA_IP_SSC2_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0034))
-#define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_TXFCON_TXTMEN (1 << 2)
-#define INCA_IP_SSC2_SSC_TXFCON_TXFLU (1 << 1)
-#define INCA_IP_SSC2_SSC_TXFCON_TXFEN (1 << 0)
-
-/***SSC FIFO Status Register***/
-#define INCA_IP_SSC2_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC2+ 0x0038))
-#define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0)
-
-/***SSC Clock Control Register***/
-#define INCA_IP_SSC2_SSC_CLC ((volatile u32*)(INCA_IP_SSC2+ 0x0000))
-#define INCA_IP_SSC2_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_CLC_DISS (1 << 1)
-#define INCA_IP_SSC2_SSC_CLC_DISR (1 << 0)
-
-/***********************************************************************/
-/* Module : EBU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_EBU (0xB8000200)
-/***********************************************************************/
-
-
-/***EBU Clock Control Register***/
-#define INCA_IP_EBU_EBU_CLC ((volatile u32*)(INCA_IP_EBU+ 0x0000))
-#define INCA_IP_EBU_EBU_CLC_DISS (1 << 1)
-#define INCA_IP_EBU_EBU_CLC_DISR (1 << 0)
-
-/***EBU Global Control Register***/
-#define INCA_IP_EBU_EBU_CON ((volatile u32*)(INCA_IP_EBU+ 0x0010))
-#define INCA_IP_EBU_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_EBU_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_CON_ARBSYNC (1 << 5)
-#define INCA_IP_EBU_EBU_CON_1 (1 << 3)
-
-/***EBU Address Select Register 0***/
-#define INCA_IP_EBU_EBU_ADDSEL0 ((volatile u32*)(INCA_IP_EBU+ 0x0020))
-#define INCA_IP_EBU_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
-#define INCA_IP_EBU_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE (1 << 1)
-#define INCA_IP_EBU_EBU_ADDSEL0_REGEN (1 << 0)
-
-/***EBU Address Select Register 1***/
-#define INCA_IP_EBU_EBU_ADDSEL1 ((volatile u32*)(INCA_IP_EBU+ 0x0024))
-#define INCA_IP_EBU_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
-#define INCA_IP_EBU_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE (1 << 1)
-#define INCA_IP_EBU_EBU_ADDSEL1_REGEN (1 << 0)
-
-/***EBU Address Select Register 2***/
-#define INCA_IP_EBU_EBU_ADDSEL2 ((volatile u32*)(INCA_IP_EBU+ 0x0028))
-#define INCA_IP_EBU_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
-#define INCA_IP_EBU_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE (1 << 1)
-#define INCA_IP_EBU_EBU_ADDSEL2_REGEN (1 << 0)
-
-/***EBU Bus Configuration Register 0***/
-#define INCA_IP_EBU_EBU_BUSCON0 ((volatile u32*)(INCA_IP_EBU+ 0x0060))
-#define INCA_IP_EBU_EBU_BUSCON0_WRDIS (1 << 31)
-#define INCA_IP_EBU_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_EBU_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
-#define INCA_IP_EBU_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_EBU_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
-#define INCA_IP_EBU_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_BUSCON0_WAITINV (1 << 19)
-#define INCA_IP_EBU_EBU_BUSCON0_SETUP (1 << 18)
-#define INCA_IP_EBU_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
-#define INCA_IP_EBU_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_EBU_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***EBU Bus Configuration Register 1***/
-#define INCA_IP_EBU_EBU_BUSCON1 ((volatile u32*)(INCA_IP_EBU+ 0x0064))
-#define INCA_IP_EBU_EBU_BUSCON1_WRDIS (1 << 31)
-#define INCA_IP_EBU_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_EBU_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
-#define INCA_IP_EBU_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_EBU_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
-#define INCA_IP_EBU_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_BUSCON1_WAITINV (1 << 19)
-#define INCA_IP_EBU_EBU_BUSCON1_SETUP (1 << 18)
-#define INCA_IP_EBU_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
-#define INCA_IP_EBU_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_EBU_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***EBU Bus Configuration Register 2***/
-#define INCA_IP_EBU_EBU_BUSCON2 ((volatile u32*)(INCA_IP_EBU+ 0x0068))
-#define INCA_IP_EBU_EBU_BUSCON2_WRDIS (1 << 31)
-#define INCA_IP_EBU_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_EBU_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
-#define INCA_IP_EBU_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_EBU_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
-#define INCA_IP_EBU_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_BUSCON2_WAITINV (1 << 19)
-#define INCA_IP_EBU_EBU_BUSCON2_SETUP (1 << 18)
-#define INCA_IP_EBU_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
-#define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : SDRAM register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_SDRAM (0xBF800000)
-/***********************************************************************/
-
-
-/***MC Access Error Cause Register***/
-#define INCA_IP_SDRAM_MC_ERRCAUSE ((volatile u32*)(INCA_IP_SDRAM+ 0x0100))
-#define INCA_IP_SDRAM_MC_ERRCAUSE_ERR (1 << 31)
-#define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN)
-
-/***MC Access Error Address Register***/
-#define INCA_IP_SDRAM_MC_ERRADDR ((volatile u32*)(INCA_IP_SDRAM+ 0x0108))
-#define INCA_IP_SDRAM_MC_ERRADDR_ADDR
-
-/***MC I/O General Purpose Register***/
-#define INCA_IP_SDRAM_MC_IOGP ((volatile u32*)(INCA_IP_SDRAM+ 0x0800))
-#define INCA_IP_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28)
-#define INCA_IP_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24)
-#define INCA_IP_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20)
-#define INCA_IP_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12)
-#define INCA_IP_SDRAM_MC_IOGP_CPS (1 << 11)
-#define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***MC Self Refresh Register***/
-#define INCA_IP_SDRAM_MC_SELFRFSH ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00))
-#define INCA_IP_SDRAM_MC_SELFRFSH_PWDS (1 << 1)
-#define INCA_IP_SDRAM_MC_SELFRFSH_PWD (1 << 0)
-#define INCA_IP_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2)
-
-/***MC Enable Register***/
-#define INCA_IP_SDRAM_MC_CTRLENA ((volatile u32*)(INCA_IP_SDRAM+ 0x1000))
-#define INCA_IP_SDRAM_MC_CTRLENA_ENA (1 << 0)
-#define INCA_IP_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1)
-
-/***MC Mode Register Setup Code***/
-#define INCA_IP_SDRAM_MC_MRSCODE ((volatile u32*)(INCA_IP_SDRAM+ 0x1008))
-#define INCA_IP_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7)
-#define INCA_IP_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_MRSCODE_WT (1 << 3)
-#define INCA_IP_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***MC Configuration Data-word Width Register***/
-#define INCA_IP_SDRAM_MC_CFGDW ((volatile u32*)(INCA_IP_SDRAM+ 0x1010))
-#define INCA_IP_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4)
-
-/***MC Configuration Physical Bank 0 Register***/
-#define INCA_IP_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP_SDRAM+ 0x1018))
-#define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12)
-#define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8)
-#define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16)
-
-/***MC Latency Register***/
-#define INCA_IP_SDRAM_MC_LATENCY ((volatile u32*)(INCA_IP_SDRAM+ 0x1038))
-#define INCA_IP_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12)
-#define INCA_IP_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8)
-#define INCA_IP_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20)
-
-/***MC Refresh Cycle Time Register***/
-#define INCA_IP_SDRAM_MC_TREFRESH ((volatile u32*)(INCA_IP_SDRAM+ 0x1040))
-#define INCA_IP_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13)
-
-/***********************************************************************/
-/* Module : GPTU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_GPTU (0xB8000300)
-/***********************************************************************/
-
-
-/***GPT Clock Control Register***/
-#define INCA_IP_GPTU_GPT_CLC ((volatile u32*)(INCA_IP_GPTU+ 0x0000))
-#define INCA_IP_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_GPTU_GPT_CLC_DISS (1 << 1)
-#define INCA_IP_GPTU_GPT_CLC_DISR (1 << 0)
-
-/***GPT Timer 3 Control Register***/
-#define INCA_IP_GPTU_GPT_T3CON ((volatile u32*)(INCA_IP_GPTU+ 0x0014))
-#define INCA_IP_GPTU_GPT_T3CON_T3RDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_T3CON_T3CHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_T3CON_T3EDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11)
-#define INCA_IP_GPTU_GPT_T3CON_T3OTL (1 << 10)
-#define INCA_IP_GPTU_GPT_T3CON_T3UD (1 << 7)
-#define INCA_IP_GPTU_GPT_T3CON_T3R (1 << 6)
-#define INCA_IP_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write Hardware Modified Timer 3 Control Register
-If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT3CON ((volatile u32*)(INCA_IP_GPTU+ 0x004C))
-#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12)
-#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11)
-#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10)
-
-/***GPT Timer 2 Control Register***/
-#define INCA_IP_GPTU_GPT_T2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0010))
-#define INCA_IP_GPTU_GPT_T2CON_TxRDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_T2CON_TxCHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_T2CON_TxEDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_T2CON_TxIRDIS (1 << 12)
-#define INCA_IP_GPTU_GPT_T2CON_TxRC (1 << 9)
-#define INCA_IP_GPTU_GPT_T2CON_TxUD (1 << 7)
-#define INCA_IP_GPTU_GPT_T2CON_TxR (1 << 6)
-#define INCA_IP_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Timer 4 Control Register***/
-#define INCA_IP_GPTU_GPT_T4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0018))
-#define INCA_IP_GPTU_GPT_T4CON_TxRDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_T4CON_TxCHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_T4CON_TxEDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_T4CON_TxIRDIS (1 << 12)
-#define INCA_IP_GPTU_GPT_T4CON_TxRC (1 << 9)
-#define INCA_IP_GPTU_GPT_T4CON_TxUD (1 << 7)
-#define INCA_IP_GPTU_GPT_T4CON_TxR (1 << 6)
-#define INCA_IP_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write HW Modified Timer 2 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0048))
-#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12)
-
-/***GPT Write HW Modified Timer 4 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0050))
-#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12)
-
-/***GPT Capture Reload Register***/
-#define INCA_IP_GPTU_GPT_CAPREL ((volatile u32*)(INCA_IP_GPTU+ 0x0030))
-#define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 2 Register***/
-#define INCA_IP_GPTU_GPT_T2 ((volatile u32*)(INCA_IP_GPTU+ 0x0034))
-#define INCA_IP_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 3 Register***/
-#define INCA_IP_GPTU_GPT_T3 ((volatile u32*)(INCA_IP_GPTU+ 0x0038))
-#define INCA_IP_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 4 Register***/
-#define INCA_IP_GPTU_GPT_T4 ((volatile u32*)(INCA_IP_GPTU+ 0x003C))
-#define INCA_IP_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 5 Register***/
-#define INCA_IP_GPTU_GPT_T5 ((volatile u32*)(INCA_IP_GPTU+ 0x0040))
-#define INCA_IP_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 6 Register***/
-#define INCA_IP_GPTU_GPT_T6 ((volatile u32*)(INCA_IP_GPTU+ 0x0044))
-#define INCA_IP_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 6 Control Register***/
-#define INCA_IP_GPTU_GPT_T6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0020))
-#define INCA_IP_GPTU_GPT_T6CON_T6SR (1 << 15)
-#define INCA_IP_GPTU_GPT_T6CON_T6CLR (1 << 14)
-#define INCA_IP_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11)
-#define INCA_IP_GPTU_GPT_T6CON_T6OTL (1 << 10)
-#define INCA_IP_GPTU_GPT_T6CON_T6UD (1 << 7)
-#define INCA_IP_GPTU_GPT_T6CON_T6R (1 << 6)
-#define INCA_IP_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write HW Modified Timer 6 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0054))
-#define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11)
-#define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10)
-
-/***GPT Timer 5 Control Register***/
-#define INCA_IP_GPTU_GPT_T5CON ((volatile u32*)(INCA_IP_GPTU+ 0x001C))
-#define INCA_IP_GPTU_GPT_T5CON_T5SC (1 << 15)
-#define INCA_IP_GPTU_GPT_T5CON_T5CLR (1 << 14)
-#define INCA_IP_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12)
-#define INCA_IP_GPTU_GPT_T5CON_T5CC (1 << 11)
-#define INCA_IP_GPTU_GPT_T5CON_CT3 (1 << 10)
-#define INCA_IP_GPTU_GPT_T5CON_T5RC (1 << 9)
-#define INCA_IP_GPTU_GPT_T5CON_T5UDE (1 << 8)
-#define INCA_IP_GPTU_GPT_T5CON_T5UD (1 << 7)
-#define INCA_IP_GPTU_GPT_T5CON_T5R (1 << 6)
-#define INCA_IP_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : IOM register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_IOM (0xBF105000)
-/***********************************************************************/
-
-
-/***Receive FIFO***/
-#define INCA_IP_IOM_RFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000))
-#define INCA_IP_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Transmit FIFO***/
-#define INCA_IP_IOM_XFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000))
-#define INCA_IP_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Interrupt Status Register HDLC***/
-#define INCA_IP_IOM_ISTAH ((volatile u32*)(INCA_IP_IOM+ 0x0080))
-#define INCA_IP_IOM_ISTAH_RME (1 << 7)
-#define INCA_IP_IOM_ISTAH_RPF (1 << 6)
-#define INCA_IP_IOM_ISTAH_RFO (1 << 5)
-#define INCA_IP_IOM_ISTAH_XPR (1 << 4)
-#define INCA_IP_IOM_ISTAH_XMR (1 << 3)
-#define INCA_IP_IOM_ISTAH_XDU (1 << 2)
-
-/***Interrupt Mask Register HDLC***/
-#define INCA_IP_IOM_MASKH ((volatile u32*)(INCA_IP_IOM+ 0x0080))
-#define INCA_IP_IOM_MASKH_RME (1 << 7)
-#define INCA_IP_IOM_MASKH_RPF (1 << 6)
-#define INCA_IP_IOM_MASKH_RFO (1 << 5)
-#define INCA_IP_IOM_MASKH_XPR (1 << 4)
-#define INCA_IP_IOM_MASKH_XMR (1 << 3)
-#define INCA_IP_IOM_MASKH_XDU (1 << 2)
-
-/***Status Register***/
-#define INCA_IP_IOM_STAR ((volatile u32*)(INCA_IP_IOM+ 0x0084))
-#define INCA_IP_IOM_STAR_XDOV (1 << 7)
-#define INCA_IP_IOM_STAR_XFW (1 << 6)
-#define INCA_IP_IOM_STAR_RACI (1 << 3)
-#define INCA_IP_IOM_STAR_XACI (1 << 1)
-
-/***Command Register***/
-#define INCA_IP_IOM_CMDR ((volatile u32*)(INCA_IP_IOM+ 0x0084))
-#define INCA_IP_IOM_CMDR_RMC (1 << 7)
-#define INCA_IP_IOM_CMDR_RRES (1 << 6)
-#define INCA_IP_IOM_CMDR_XTF (1 << 3)
-#define INCA_IP_IOM_CMDR_XME (1 << 1)
-#define INCA_IP_IOM_CMDR_XRES (1 << 0)
-
-/***Mode Register***/
-#define INCA_IP_IOM_MODEH ((volatile u32*)(INCA_IP_IOM+ 0x0088))
-#define INCA_IP_IOM_MODEH_MDS2 (1 << 7)
-#define INCA_IP_IOM_MODEH_MDS1 (1 << 6)
-#define INCA_IP_IOM_MODEH_MDS0 (1 << 5)
-#define INCA_IP_IOM_MODEH_RAC (1 << 3)
-#define INCA_IP_IOM_MODEH_DIM2 (1 << 2)
-#define INCA_IP_IOM_MODEH_DIM1 (1 << 1)
-#define INCA_IP_IOM_MODEH_DIM0 (1 << 0)
-
-/***Extended Mode Register***/
-#define INCA_IP_IOM_EXMR ((volatile u32*)(INCA_IP_IOM+ 0x008C))
-#define INCA_IP_IOM_EXMR_XFBS (1 << 7)
-#define INCA_IP_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5)
-#define INCA_IP_IOM_EXMR_SRA (1 << 4)
-#define INCA_IP_IOM_EXMR_XCRC (1 << 3)
-#define INCA_IP_IOM_EXMR_RCRC (1 << 2)
-#define INCA_IP_IOM_EXMR_ITF (1 << 0)
-
-/***SAPI1 Register***/
-#define INCA_IP_IOM_SAP1 ((volatile u32*)(INCA_IP_IOM+ 0x0094))
-#define INCA_IP_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2)
-#define INCA_IP_IOM_SAP1_MHA (1 << 0)
-
-/***Receive Frame Byte Count Low***/
-#define INCA_IP_IOM_RBCL ((volatile u32*)(INCA_IP_IOM+ 0x0098))
-#define INCA_IP_IOM_RBCL_RBC(value) (1 << value)
-
-
-/***SAPI2 Register***/
-#define INCA_IP_IOM_SAP2 ((volatile u32*)(INCA_IP_IOM+ 0x0098))
-#define INCA_IP_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2)
-#define INCA_IP_IOM_SAP2_MLA (1 << 0)
-
-/***Receive Frame Byte Count High***/
-#define INCA_IP_IOM_RBCH ((volatile u32*)(INCA_IP_IOM+ 0x009C))
-#define INCA_IP_IOM_RBCH_OV (1 << 4)
-#define INCA_IP_IOM_RBCH_RBC11 (1 << 3)
-#define INCA_IP_IOM_RBCH_RBC10 (1 << 2)
-#define INCA_IP_IOM_RBCH_RBC9 (1 << 1)
-#define INCA_IP_IOM_RBCH_RBC8 (1 << 0)
-
-/***TEI1 Register 1***/
-#define INCA_IP_IOM_TEI1 ((volatile u32*)(INCA_IP_IOM+ 0x009C))
-#define INCA_IP_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1)
-#define INCA_IP_IOM_TEI1_EA (1 << 0)
-
-/***Receive Status Register***/
-#define INCA_IP_IOM_RSTA ((volatile u32*)(INCA_IP_IOM+ 0x00A0))
-#define INCA_IP_IOM_RSTA_VFR (1 << 7)
-#define INCA_IP_IOM_RSTA_RDO (1 << 6)
-#define INCA_IP_IOM_RSTA_CRC (1 << 5)
-#define INCA_IP_IOM_RSTA_RAB (1 << 4)
-#define INCA_IP_IOM_RSTA_SA1 (1 << 3)
-#define INCA_IP_IOM_RSTA_SA0 (1 << 2)
-#define INCA_IP_IOM_RSTA_TA (1 << 0)
-#define INCA_IP_IOM_RSTA_CR (1 << 1)
-
-/***TEI2 Register***/
-#define INCA_IP_IOM_TEI2 ((volatile u32*)(INCA_IP_IOM+ 0x00A0))
-#define INCA_IP_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1)
-#define INCA_IP_IOM_TEI2_EA (1 << 0)
-
-/***Test Mode Register HDLC***/
-#define INCA_IP_IOM_TMH ((volatile u32*)(INCA_IP_IOM+ 0x00A4))
-#define INCA_IP_IOM_TMH_TLP (1 << 0)
-
-/***Command/Indication Receive 0***/
-#define INCA_IP_IOM_CIR0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8))
-#define INCA_IP_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_IOM_CIR0_CIC0 (1 << 3)
-#define INCA_IP_IOM_CIR0_CIC1 (1 << 2)
-#define INCA_IP_IOM_CIR0_SG (1 << 1)
-#define INCA_IP_IOM_CIR0_BAS (1 << 0)
-
-/***Command/Indication Transmit 0***/
-#define INCA_IP_IOM_CIX0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8))
-#define INCA_IP_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_IOM_CIX0_TBA2 (1 << 3)
-#define INCA_IP_IOM_CIX0_TBA1 (1 << 2)
-#define INCA_IP_IOM_CIX0_TBA0 (1 << 1)
-#define INCA_IP_IOM_CIX0_BAC (1 << 0)
-
-/***Command/Indication Receive 1***/
-#define INCA_IP_IOM_CIR1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC))
-#define INCA_IP_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2)
-
-/***Command/Indication Transmit 1***/
-#define INCA_IP_IOM_CIX1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC))
-#define INCA_IP_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2)
-#define INCA_IP_IOM_CIX1_CICW (1 << 1)
-#define INCA_IP_IOM_CIX1_CI1E (1 << 0)
-
-/***Controller Data Access Reg. (CH10)***/
-#define INCA_IP_IOM_CDA10 ((volatile u32*)(INCA_IP_IOM+ 0x0100))
-#define INCA_IP_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH11)***/
-#define INCA_IP_IOM_CDA11 ((volatile u32*)(INCA_IP_IOM+ 0x0104))
-#define INCA_IP_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH20)***/
-#define INCA_IP_IOM_CDA20 ((volatile u32*)(INCA_IP_IOM+ 0x0108))
-#define INCA_IP_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH21)***/
-#define INCA_IP_IOM_CDA21 ((volatile u32*)(INCA_IP_IOM+ 0x010C))
-#define INCA_IP_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH10)***/
-#define INCA_IP_IOM_CDA_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0110))
-#define INCA_IP_IOM_CDA_TSDP10_DPS (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH11)***/
-#define INCA_IP_IOM_CDA_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0114))
-#define INCA_IP_IOM_CDA_TSDP11_DPS (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH20)***/
-#define INCA_IP_IOM_CDA_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0118))
-#define INCA_IP_IOM_CDA_TSDP20_DPS (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH21)***/
-#define INCA_IP_IOM_CDA_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x011C))
-#define INCA_IP_IOM_CDA_TSDP21_DPS (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH10)***/
-#define INCA_IP_IOM_CO_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0120))
-#define INCA_IP_IOM_CO_TSDP10_DPS (1 << 7)
-#define INCA_IP_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH11)***/
-#define INCA_IP_IOM_CO_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0124))
-#define INCA_IP_IOM_CO_TSDP11_DPS (1 << 7)
-#define INCA_IP_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH20)***/
-#define INCA_IP_IOM_CO_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0128))
-#define INCA_IP_IOM_CO_TSDP20_DPS (1 << 7)
-#define INCA_IP_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH21)***/
-#define INCA_IP_IOM_CO_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x012C))
-#define INCA_IP_IOM_CO_TSDP21_DPS (1 << 7)
-#define INCA_IP_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Ctrl. Reg. Contr. Data Access CH1x***/
-#define INCA_IP_IOM_CDA1_CR ((volatile u32*)(INCA_IP_IOM+ 0x0138))
-#define INCA_IP_IOM_CDA1_CR_EN_TBM (1 << 5)
-#define INCA_IP_IOM_CDA1_CR_EN_I1 (1 << 4)
-#define INCA_IP_IOM_CDA1_CR_EN_I0 (1 << 3)
-#define INCA_IP_IOM_CDA1_CR_EN_O1 (1 << 2)
-#define INCA_IP_IOM_CDA1_CR_EN_O0 (1 << 1)
-#define INCA_IP_IOM_CDA1_CR_SWAP (1 << 0)
-
-/***Ctrl. Reg. Contr. Data Access CH1x***/
-#define INCA_IP_IOM_CDA2_CR ((volatile u32*)(INCA_IP_IOM+ 0x013C))
-#define INCA_IP_IOM_CDA2_CR_EN_TBM (1 << 5)
-#define INCA_IP_IOM_CDA2_CR_EN_I1 (1 << 4)
-#define INCA_IP_IOM_CDA2_CR_EN_I0 (1 << 3)
-#define INCA_IP_IOM_CDA2_CR_EN_O1 (1 << 2)
-#define INCA_IP_IOM_CDA2_CR_EN_O0 (1 << 1)
-#define INCA_IP_IOM_CDA2_CR_SWAP (1 << 0)
-
-/***Control Register B-Channel Data***/
-#define INCA_IP_IOM_BCHA_CR ((volatile u32*)(INCA_IP_IOM+ 0x0144))
-#define INCA_IP_IOM_BCHA_CR_EN_BC2 (1 << 4)
-#define INCA_IP_IOM_BCHA_CR_EN_BC1 (1 << 3)
-
-/***Control Register B-Channel Data***/
-#define INCA_IP_IOM_BCHB_CR ((volatile u32*)(INCA_IP_IOM+ 0x0148))
-#define INCA_IP_IOM_BCHB_CR_EN_BC2 (1 << 4)
-#define INCA_IP_IOM_BCHB_CR_EN_BC1 (1 << 3)
-
-/***Control Reg. for HDLC and CI1 Data***/
-#define INCA_IP_IOM_DCI_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C))
-#define INCA_IP_IOM_DCI_CR_DPS_CI1 (1 << 7)
-#define INCA_IP_IOM_DCI_CR_EN_CI1 (1 << 6)
-#define INCA_IP_IOM_DCI_CR_EN_D (1 << 5)
-
-/***Control Reg. for HDLC and CI1 Data***/
-#define INCA_IP_IOM_DCIC_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C))
-#define INCA_IP_IOM_DCIC_CR_DPS_CI0 (1 << 7)
-#define INCA_IP_IOM_DCIC_CR_EN_CI0 (1 << 6)
-#define INCA_IP_IOM_DCIC_CR_DPS_D (1 << 5)
-
-/***Control Reg. Serial Data Strobe x***/
-#define INCA_IP_IOM_SDS_CR ((volatile u32*)(INCA_IP_IOM+ 0x0154))
-#define INCA_IP_IOM_SDS_CR_ENS_TSS (1 << 7)
-#define INCA_IP_IOM_SDS_CR_ENS_TSS_1 (1 << 6)
-#define INCA_IP_IOM_SDS_CR_ENS_TSS_3 (1 << 5)
-#define INCA_IP_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Control Register IOM Data***/
-#define INCA_IP_IOM_IOM_CR ((volatile u32*)(INCA_IP_IOM+ 0x015C))
-#define INCA_IP_IOM_IOM_CR_SPU (1 << 7)
-#define INCA_IP_IOM_IOM_CR_CI_CS (1 << 5)
-#define INCA_IP_IOM_IOM_CR_TIC_DIS (1 << 4)
-#define INCA_IP_IOM_IOM_CR_EN_BCL (1 << 3)
-#define INCA_IP_IOM_IOM_CR_CLKM (1 << 2)
-#define INCA_IP_IOM_IOM_CR_Res (1 << 1)
-#define INCA_IP_IOM_IOM_CR_DIS_IOM (1 << 0)
-
-/***Synchronous Transfer Interrupt***/
-#define INCA_IP_IOM_STI ((volatile u32*)(INCA_IP_IOM+ 0x0160))
-#define INCA_IP_IOM_STI_STOV21 (1 << 7)
-#define INCA_IP_IOM_STI_STOV20 (1 << 6)
-#define INCA_IP_IOM_STI_STOV11 (1 << 5)
-#define INCA_IP_IOM_STI_STOV10 (1 << 4)
-#define INCA_IP_IOM_STI_STI21 (1 << 3)
-#define INCA_IP_IOM_STI_STI20 (1 << 2)
-#define INCA_IP_IOM_STI_STI11 (1 << 1)
-#define INCA_IP_IOM_STI_STI10 (1 << 0)
-
-/***Acknowledge Synchronous Transfer Interrupt***/
-#define INCA_IP_IOM_ASTI ((volatile u32*)(INCA_IP_IOM+ 0x0160))
-#define INCA_IP_IOM_ASTI_ACK21 (1 << 3)
-#define INCA_IP_IOM_ASTI_ACK20 (1 << 2)
-#define INCA_IP_IOM_ASTI_ACK11 (1 << 1)
-#define INCA_IP_IOM_ASTI_ACK10 (1 << 0)
-
-/***Mask Synchronous Transfer Interrupt***/
-#define INCA_IP_IOM_MSTI ((volatile u32*)(INCA_IP_IOM+ 0x0164))
-#define INCA_IP_IOM_MSTI_STOV21 (1 << 7)
-#define INCA_IP_IOM_MSTI_STOV20 (1 << 6)
-#define INCA_IP_IOM_MSTI_STOV11 (1 << 5)
-#define INCA_IP_IOM_MSTI_STOV10 (1 << 4)
-#define INCA_IP_IOM_MSTI_STI21 (1 << 3)
-#define INCA_IP_IOM_MSTI_STI20 (1 << 2)
-#define INCA_IP_IOM_MSTI_STI11 (1 << 1)
-#define INCA_IP_IOM_MSTI_STI10 (1 << 0)
-
-/***Configuration Register for Serial Data Strobes***/
-#define INCA_IP_IOM_SDS_CONF ((volatile u32*)(INCA_IP_IOM+ 0x0168))
-#define INCA_IP_IOM_SDS_CONF_SDS_BCL (1 << 0)
-
-/***Monitoring CDA Bits***/
-#define INCA_IP_IOM_MCDA ((volatile u32*)(INCA_IP_IOM+ 0x016C))
-#define INCA_IP_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : ASC register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_ASC (0xB8000400)
-/***********************************************************************/
-
-
-/***ASC Port Input Select Register***/
-#define INCA_IP_ASC_ASC_PISEL ((volatile u32*)(INCA_IP_ASC+ 0x0004))
-#define INCA_IP_ASC_ASC_PISEL_RIS (1 << 0)
-
-/***ASC Control Register***/
-#define INCA_IP_ASC_ASC_CON ((volatile u32*)(INCA_IP_ASC+ 0x0010))
-#define INCA_IP_ASC_ASC_CON_R (1 << 15)
-#define INCA_IP_ASC_ASC_CON_LB (1 << 14)
-#define INCA_IP_ASC_ASC_CON_BRS (1 << 13)
-#define INCA_IP_ASC_ASC_CON_ODD (1 << 12)
-#define INCA_IP_ASC_ASC_CON_FDE (1 << 11)
-#define INCA_IP_ASC_ASC_CON_OE (1 << 10)
-#define INCA_IP_ASC_ASC_CON_FE (1 << 9)
-#define INCA_IP_ASC_ASC_CON_PE (1 << 8)
-#define INCA_IP_ASC_ASC_CON_OEN (1 << 7)
-#define INCA_IP_ASC_ASC_CON_FEN (1 << 6)
-#define INCA_IP_ASC_ASC_CON_PENRXDI (1 << 5)
-#define INCA_IP_ASC_ASC_CON_REN (1 << 4)
-#define INCA_IP_ASC_ASC_CON_STP (1 << 3)
-#define INCA_IP_ASC_ASC_CON_M (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***ASC Write Hardware Modified Control Register***/
-#define INCA_IP_ASC_ASC_WHBCON ((volatile u32*)(INCA_IP_ASC+ 0x0050))
-#define INCA_IP_ASC_ASC_WHBCON_SETOE (1 << 13)
-#define INCA_IP_ASC_ASC_WHBCON_SETFE (1 << 12)
-#define INCA_IP_ASC_ASC_WHBCON_SETPE (1 << 11)
-#define INCA_IP_ASC_ASC_WHBCON_CLROE (1 << 10)
-#define INCA_IP_ASC_ASC_WHBCON_CLRFE (1 << 9)
-#define INCA_IP_ASC_ASC_WHBCON_CLRPE (1 << 8)
-#define INCA_IP_ASC_ASC_WHBCON_SETREN (1 << 5)
-#define INCA_IP_ASC_ASC_WHBCON_CLRREN (1 << 4)
-
-/***ASC Baudrate Timer/Reload Register***/
-#define INCA_IP_ASC_ASC_BTR ((volatile u32*)(INCA_IP_ASC+ 0x0014))
-#define INCA_IP_ASC_ASC_BTR_BR_VALUE (value) (((( 1 << 13) - 1) & (value)) << 0)
-
-/***ASC Fractional Divider Register***/
-#define INCA_IP_ASC_ASC_FDV ((volatile u32*)(INCA_IP_ASC+ 0x0018))
-#define INCA_IP_ASC_ASC_FDV_FD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC IrDA Pulse Mode/Width Register***/
-#define INCA_IP_ASC_ASC_PMW ((volatile u32*)(INCA_IP_ASC+ 0x001C))
-#define INCA_IP_ASC_ASC_PMW_IRPW (1 << 8)
-#define INCA_IP_ASC_ASC_PMW_PW_VALUE (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***ASC Transmit Buffer Register***/
-#define INCA_IP_ASC_ASC_TBUF ((volatile u32*)(INCA_IP_ASC+ 0x0020))
-#define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Receive Buffer Register***/
-#define INCA_IP_ASC_ASC_RBUF ((volatile u32*)(INCA_IP_ASC+ 0x0024))
-#define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Autobaud Control Register***/
-#define INCA_IP_ASC_ASC_ABCON ((volatile u32*)(INCA_IP_ASC+ 0x0030))
-#define INCA_IP_ASC_ASC_ABCON_RXINV (1 << 11)
-#define INCA_IP_ASC_ASC_ABCON_TXINV (1 << 10)
-#define INCA_IP_ASC_ASC_ABCON_ABEM (value) (((( 1 << 2) - 1) & (value)) << 8)
-#define INCA_IP_ASC_ASC_ABCON_FCDETEN (1 << 4)
-#define INCA_IP_ASC_ASC_ABCON_ABDETEN (1 << 3)
-#define INCA_IP_ASC_ASC_ABCON_ABSTEN (1 << 2)
-#define INCA_IP_ASC_ASC_ABCON_AUREN (1 << 1)
-#define INCA_IP_ASC_ASC_ABCON_ABEN (1 << 0)
-
-/***Receive FIFO Control Register***/
-#define INCA_IP_ASC_RXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0040))
-#define INCA_IP_ASC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_ASC_RXFCON_RXTMEN (1 << 2)
-#define INCA_IP_ASC_RXFCON_RXFFLU (1 << 1)
-#define INCA_IP_ASC_RXFCON_RXFEN (1 << 0)
-
-/***Transmit FIFO Control Register***/
-#define INCA_IP_ASC_TXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0044))
-#define INCA_IP_ASC_TXFCON_TXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_ASC_TXFCON_TXTMEN (1 << 2)
-#define INCA_IP_ASC_TXFCON_TXFFLU (1 << 1)
-#define INCA_IP_ASC_TXFCON_TXFEN (1 << 0)
-
-/***FIFO Status Register***/
-#define INCA_IP_ASC_FSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0048))
-#define INCA_IP_ASC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_ASC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0)
-
-/***ASC Write HW Modified Autobaud Control Register***/
-#define INCA_IP_ASC_ASC_WHBABCON ((volatile u32*)(INCA_IP_ASC+ 0x0054))
-#define INCA_IP_ASC_ASC_WHBABCON_SETABEN (1 << 1)
-#define INCA_IP_ASC_ASC_WHBABCON_CLRABEN (1 << 0)
-
-/***ASC Autobaud Status Register***/
-#define INCA_IP_ASC_ASC_ABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0034))
-#define INCA_IP_ASC_ASC_ABSTAT_DETWAIT (1 << 4)
-#define INCA_IP_ASC_ASC_ABSTAT_SCCDET (1 << 3)
-#define INCA_IP_ASC_ASC_ABSTAT_SCSDET (1 << 2)
-#define INCA_IP_ASC_ASC_ABSTAT_FCCDET (1 << 1)
-#define INCA_IP_ASC_ASC_ABSTAT_FCSDET (1 << 0)
-
-/***ASC Write HW Modified Autobaud Status Register***/
-#define INCA_IP_ASC_ASC_WHBABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0058))
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT (1 << 9)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT (1 << 8)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCCDET (1 << 7)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCCDET (1 << 6)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCSDET (1 << 5)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCSDET (1 << 4)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCCDET (1 << 3)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET (1 << 2)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET (1 << 1)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET (1 << 0)
-
-/***ASC Clock Control Register***/
-#define INCA_IP_ASC_ASC_CLC ((volatile u32*)(INCA_IP_ASC+ 0x0000))
-#define INCA_IP_ASC_ASC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_ASC_ASC_CLC_DISS (1 << 1)
-#define INCA_IP_ASC_ASC_CLC_DISR (1 << 0)
-
-/***********************************************************************/
-/* Module : DMA register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_DMA (0xBF108000)
-/***********************************************************************/
-
-
-/***DMA RX Channel 0 Command Register***/
-#define INCA_IP_DMA_DMA_RXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0800))
-#define INCA_IP_DMA_DMA_RXCCR0_LBE (1 << 31)
-#define INCA_IP_DMA_DMA_RXCCR0_HPEN (1 << 30)
-#define INCA_IP_DMA_DMA_RXCCR0_INIT (1 << 2)
-#define INCA_IP_DMA_DMA_RXCCR0_OFF (1 << 1)
-#define INCA_IP_DMA_DMA_RXCCR0_HR (1 << 0)
-
-/***DMA RX Channel 1 Command Register***/
-#define INCA_IP_DMA_DMA_RXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0804))
-#define INCA_IP_DMA_DMA_RXCCR1_LBE (1 << 31)
-#define INCA_IP_DMA_DMA_RXCCR1_HPEN (1 << 30)
-#define INCA_IP_DMA_DMA_RXCCR1_INIT (1 << 2)
-#define INCA_IP_DMA_DMA_RXCCR1_OFF (1 << 1)
-#define INCA_IP_DMA_DMA_RXCCR1_HR (1 << 0)
-
-/***DMA Receive Interrupt Status Register***/
-#define INCA_IP_DMA_DMA_RXISR ((volatile u32*)(INCA_IP_DMA+ 0x0808))
-#define INCA_IP_DMA_DMA_RXISR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8)
-#define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_RXISR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_DMA_DMA_RXISR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_DMA_DMA_RXISR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***DMA Receive Interrupt Mask Register***/
-#define INCA_IP_DMA_DMA_RXIMR ((volatile u32*)(INCA_IP_DMA+ 0x080C))
-#define INCA_IP_DMA_DMA_RXIMR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8)
-#define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_RXIMR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_DMA_DMA_RXIMR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_DMA_DMA_RXIMR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Rx Channel 0
-***/
-#define INCA_IP_DMA_DMA_RXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x0810))
-#define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Rx Channel 1
-***/
-#define INCA_IP_DMA_DMA_RXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x0814))
-#define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA Receive Channel Polling Time***/
-#define INCA_IP_DMA_DMA_RXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x0818))
-#define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 30)
-#define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 28)
-#define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***DMA TX Channel 0 Command Register (Voice Port)***/
-#define INCA_IP_DMA_DMA_TXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0880))
-#define INCA_IP_DMA_DMA_TXCCR0_LBE (1 << 31)
-#define INCA_IP_DMA_DMA_TXCCR0_HPEN (1 << 30)
-#define INCA_IP_DMA_DMA_TXCCR0_HR (1 << 2)
-#define INCA_IP_DMA_DMA_TXCCR0_OFF (1 << 1)
-#define INCA_IP_DMA_DMA_TXCCR0_INIT (1 << 0)
-
-/***DMA TX Channel 1 Command Register (Mangmt Port)***/
-#define INCA_IP_DMA_DMA_TXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0884))
-#define INCA_IP_DMA_DMA_TXCCR1_LBE (1 << 31)
-#define INCA_IP_DMA_DMA_TXCCR1_HPEN (1 << 30)
-#define INCA_IP_DMA_DMA_TXCCR1_HR (1 << 2)
-#define INCA_IP_DMA_DMA_TXCCR1_OFF (1 << 1)
-#define INCA_IP_DMA_DMA_TXCCR1_INIT (1 << 0)
-
-/***DMA TX Channel 2 Command Register (SSC Port)***/
-#define INCA_IP_DMA_DMA_TXCCR2 ((volatile u32*)(INCA_IP_DMA+ 0x0888))
-#define INCA_IP_DMA_DMA_TXCCR2_LBE (1 << 31)
-#define INCA_IP_DMA_DMA_TXCCR2_HPEN (1 << 30)
-#define INCA_IP_DMA_DMA_TXCCR2_HBF (1 << 29)
-#define INCA_IP_DMA_DMA_TXCCR2_HR (1 << 2)
-#define INCA_IP_DMA_DMA_TXCCR2_OFF (1 << 1)
-#define INCA_IP_DMA_DMA_TXCCR2_INIT (1 << 0)
-
-/***DMA First Receive Descriptor Addr. for Tx Channel 0
-***/
-#define INCA_IP_DMA_DMA_TXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x08A0))
-#define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Tx Channel 1
-***/
-#define INCA_IP_DMA_DMA_TXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x08A4))
-#define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Tx Channel 2
-***/
-#define INCA_IP_DMA_DMA_TXFRDA2 ((volatile u32*)(INCA_IP_DMA+ 0x08A8))
-#define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA Transmit Channel Arbitration Register***/
-#define INCA_IP_DMA_DMA_TXWGT ((volatile u32*)(INCA_IP_DMA+ 0x08C0))
-#define INCA_IP_DMA_DMA_TXWGT_TX2PR (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***DMA Transmit Channel Polling Time***/
-#define INCA_IP_DMA_DMA_TXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x08C4))
-#define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value) (((( 1 << 2) - 1) & (value)) << 30)
-#define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 28)
-#define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 26)
-#define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***DMA Transmit Interrupt Status Register***/
-#define INCA_IP_DMA_DMA_TXISR ((volatile u32*)(INCA_IP_DMA+ 0x08C8))
-#define INCA_IP_DMA_DMA_TXISR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_DMA_DMA_TXISR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9)
-#define INCA_IP_DMA_DMA_TXISR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_TXISR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***DMA Transmit Interrupt Mask Register***/
-#define INCA_IP_DMA_DMA_TXIMR ((volatile u32*)(INCA_IP_DMA+ 0x08CC))
-#define INCA_IP_DMA_DMA_TXIMR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_DMA_DMA_TXIMR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9)
-#define INCA_IP_DMA_DMA_TXIMR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_TXIMR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : Debug register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_Debug (0xBF106000)
-/***********************************************************************/
-
-
-/***MCD Break Bus Switch Register***/
-#define INCA_IP_Debug_MCD_BBS ((volatile u32*)(INCA_IP_Debug+ 0x0000))
-#define INCA_IP_Debug_MCD_BBS_BTP1 (1 << 19)
-#define INCA_IP_Debug_MCD_BBS_BTP0 (1 << 18)
-#define INCA_IP_Debug_MCD_BBS_BSP1 (1 << 17)
-#define INCA_IP_Debug_MCD_BBS_BSP0 (1 << 16)
-#define INCA_IP_Debug_MCD_BBS_BT5EN (1 << 15)
-#define INCA_IP_Debug_MCD_BBS_BT4EN (1 << 14)
-#define INCA_IP_Debug_MCD_BBS_BT5 (1 << 13)
-#define INCA_IP_Debug_MCD_BBS_BT4 (1 << 12)
-#define INCA_IP_Debug_MCD_BBS_BS5EN (1 << 7)
-#define INCA_IP_Debug_MCD_BBS_BS4EN (1 << 6)
-#define INCA_IP_Debug_MCD_BBS_BS5 (1 << 5)
-#define INCA_IP_Debug_MCD_BBS_BS4 (1 << 4)
-
-/***MCD Multiplexer Control Register***/
-#define INCA_IP_Debug_MCD_MCR ((volatile u32*)(INCA_IP_Debug+ 0x0008))
-#define INCA_IP_Debug_MCD_MCR_MUX5 (1 << 4)
-#define INCA_IP_Debug_MCD_MCR_MUX4 (1 << 3)
-#define INCA_IP_Debug_MCD_MCR_MUX1 (1 << 0)
-
-/***********************************************************************/
-/* Module : TSF register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_TSF (0xB8000900)
-/***********************************************************************/
-
-
-/***TSF Configuration Register (0000H)***/
-#define INCA_IP_TSF_TSF_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0000))
-#define INCA_IP_TSF_TSF_CONF_PWMEN (1 << 2)
-#define INCA_IP_TSF_TSF_CONF_LEDEN (1 << 1)
-#define INCA_IP_TSF_TSF_CONF_KEYEN (1 << 0)
-
-/***Key scan Configuration Register (0004H)***/
-#define INCA_IP_TSF_KEY_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0004))
-#define INCA_IP_TSF_KEY_CONF_SL (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Scan Register Line 0 and 1 (0008H)***/
-#define INCA_IP_TSF_SREG01 ((volatile u32*)(INCA_IP_TSF+ 0x0008))
-#define INCA_IP_TSF_SREG01_RES1x (value) (((( 1 << 12) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG01_RES0x (value) (((( 1 << 13) - 1) & (value)) << 0)
-
-/***Scan Register Line 2 and 3 (000CH)***/
-#define INCA_IP_TSF_SREG23 ((volatile u32*)(INCA_IP_TSF+ 0x000C))
-#define INCA_IP_TSF_SREG23_RES3x (value) (((( 1 << 10) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG23_RES2x (value) (((( 1 << 11) - 1) & (value)) << 0)
-
-/***Scan Register Line 4, 5 and 6 (0010H)***/
-#define INCA_IP_TSF_SREG456 ((volatile u32*)(INCA_IP_TSF+ 0x0010))
-#define INCA_IP_TSF_SREG456_RES6x (value) (((( 1 << 7) - 1) & (value)) << 24)
-#define INCA_IP_TSF_SREG456_RES5x (value) (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG456_RES4x (value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***Scan Register Line 7 to 12 (0014H)***/
-#define INCA_IP_TSF_SREG7to12 ((volatile u32*)(INCA_IP_TSF+ 0x0014))
-#define INCA_IP_TSF_SREG7to12_RES12x (1 << 28)
-#define INCA_IP_TSF_SREG7to12_RES11x (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_TSF_SREG7to12_RES10x (value) (((( 1 << 3) - 1) & (value)) << 20)
-#define INCA_IP_TSF_SREG7to12_RES9x (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG7to12_RES8x (value) (((( 1 << 5) - 1) & (value)) << 8)
-#define INCA_IP_TSF_SREG7to12_RES7x (value) (((( 1 << 6) - 1) & (value)) << 0)
-
-/***LEDMUX Configuration Register (0018H)***/
-#define INCA_IP_TSF_LEDMUX_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0018))
-#define INCA_IP_TSF_LEDMUX_CONF_ETL1 (1 << 25)
-#define INCA_IP_TSF_LEDMUX_CONF_ESTA1 (1 << 24)
-#define INCA_IP_TSF_LEDMUX_CONF_EDPX1 (1 << 23)
-#define INCA_IP_TSF_LEDMUX_CONF_EACT1 (1 << 22)
-#define INCA_IP_TSF_LEDMUX_CONF_ESPD1 (1 << 21)
-#define INCA_IP_TSF_LEDMUX_CONF_ETL0 (1 << 20)
-#define INCA_IP_TSF_LEDMUX_CONF_ESTA0 (1 << 19)
-#define INCA_IP_TSF_LEDMUX_CONF_EDPX0 (1 << 18)
-#define INCA_IP_TSF_LEDMUX_CONF_EACT0 (1 << 17)
-#define INCA_IP_TSF_LEDMUX_CONF_ESPD0 (1 << 16)
-#define INCA_IP_TSF_LEDMUX_CONF_INV (1 << 1)
-#define INCA_IP_TSF_LEDMUX_CONF_NCOL (1 << 0)
-
-/***LED Register (001CH)***/
-#define INCA_IP_TSF_LED_REG ((volatile u32*)(INCA_IP_TSF+ 0x001C))
-#define INCA_IP_TSF_LED_REG_Lxy (value) (((( 1 << 24) - 1) & (value)) << 0)
-
-/***Pulse Width Modulator 1 and 2 Register (0020H)***/
-#define INCA_IP_TSF_PWM12 ((volatile u32*)(INCA_IP_TSF+ 0x0020))
-#define INCA_IP_TSF_PWM12_PW2PW1 (value) (((( 1 << NaN) - 1) & (value)) << NaN)
-
-/***********************************************************************/
-/* Module : Ports register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_Ports (0xB8000A00)
-/***********************************************************************/
-
-
-/***Port 1 Data Output Register (0020H)***/
-#define INCA_IP_Ports_P1_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0020))
-#define INCA_IP_Ports_P1_OUT_P(value) (1 << value)
-
-
-/***Port 2 Data Output Register (0040H)***/
-#define INCA_IP_Ports_P2_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0040))
-#define INCA_IP_Ports_P2_OUT_P(value) (1 << value)
-
-
-/***Port 1 Data Input Register (0024H)***/
-#define INCA_IP_Ports_P1_IN ((volatile u32*)(INCA_IP_Ports+ 0x0024))
-#define INCA_IP_Ports_P1_IN_P(value) (1 << value)
-
-
-/***Port 2 Data Input Register (0044H)***/
-#define INCA_IP_Ports_P2_IN ((volatile u32*)(INCA_IP_Ports+ 0x0044))
-#define INCA_IP_Ports_P2_IN_P(value) (1 << value)
-
-
-/***Port 1 Direction Register (0028H)***/
-#define INCA_IP_Ports_P1_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0028))
-#define INCA_IP_Ports_P1_DIR_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P1_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***Port 2 Direction Register (0048H)***/
-#define INCA_IP_Ports_P2_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0048))
-#define INCA_IP_Ports_P2_DIR_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P2_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***Port 0 Alternate Function Select Register 0 (000C H)
-***/
-#define INCA_IP_Ports_P0_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x000C))
-#define INCA_IP_Ports_P0_ALTSEL_Port0P(value) (1 << value)
-
-
-/***Port 1 Alternate Function Select Register 0 (002C H)
-***/
-#define INCA_IP_Ports_P1_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x002C))
-#define INCA_IP_Ports_P1_ALTSEL_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P1_ALTSEL_Port2P(value) (1 << value)
-
-
-/***Port 2 Alternate Function Select Register 0 (004C H)
-***/
-#define INCA_IP_Ports_P2_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x004C))
-#define INCA_IP_Ports_P2_ALTSEL_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P2_ALTSEL_Port2P(value) (1 << value)
-
-
-/***Port 0 Input Schmitt-Trigger Off Register (0010 H)
-***/
-#define INCA_IP_Ports_P0_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0010))
-#define INCA_IP_Ports_P0_STOFF_Port0P(value) (1 << value)
-
-
-/***Port 1 Input Schmitt-Trigger Off Register (0030 H)
-***/
-#define INCA_IP_Ports_P1_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0030))
-#define INCA_IP_Ports_P1_STOFF_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P1_STOFF_Port2P(value) (1 << value)
-
-
-/***Port 2 Input Schmitt-Trigger Off Register (0050 H)
-***/
-#define INCA_IP_Ports_P2_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0050))
-#define INCA_IP_Ports_P2_STOFF_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P2_STOFF_Port2P(value) (1 << value)
-
-
-/***Port 2 Open Drain Control Register (0054H)***/
-#define INCA_IP_Ports_P2_OD ((volatile u32*)(INCA_IP_Ports+ 0x0054))
-#define INCA_IP_Ports_P2_OD_Port2P(value) (1 << value)
-
-
-/***Port 0 Pull Up Device Enable Register (0018 H)***/
-#define INCA_IP_Ports_P0_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0018))
-#define INCA_IP_Ports_P0_PUDEN_Port0P(value) (1 << value)
-
-
-/***Port 2 Pull Up Device Enable Register (0058 H)***/
-#define INCA_IP_Ports_P2_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0058))
-#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value)
-
-#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value)
-
-
-/***Port 0 Pull Up/Pull Down Select Register (001C H)***/
-#define INCA_IP_Ports_P0_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x001C))
-#define INCA_IP_Ports_P0_PUDSEL_Port0P(value) (1 << value)
-
-
-/***Port 2 Pull Up/Pull Down Select Register (005C H)***/
-#define INCA_IP_Ports_P2_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x005C))
-#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value)
-
-#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value)
-
-
-/***********************************************************************/
-/* Module : DES/3DES register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_DES_3DES (0xB8000800)
-/***********************************************************************/
-
-
-/***DES Input Data High Register***/
-#define INCA_IP_DES_3DES_DES_IHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000))
-#define INCA_IP_DES_3DES_DES_IHR_IH(value) (1 << value)
-
-
-/***DES Input Data Low Register***/
-#define INCA_IP_DES_3DES_DES_ILR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004))
-#define INCA_IP_DES_3DES_DES_ILR_IL(value) (1 << value)
-
-
-/***DES Key #1 High Register***/
-#define INCA_IP_DES_3DES_DES_K1HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008))
-#define INCA_IP_DES_3DES_DES_K1HR_K1H(value) (1 << value)
-
-
-/***DES Key #1 Low Register***/
-#define INCA_IP_DES_3DES_DES_K1LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C))
-#define INCA_IP_DES_3DES_DES_K1LR_K1L(value) (1 << value)
-
-
-/***DES Key #2 High Register***/
-#define INCA_IP_DES_3DES_DES_K2HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010))
-#define INCA_IP_DES_3DES_DES_K2HR_K2H(value) (1 << value)
-
-
-/***DES Key #2 Low Register***/
-#define INCA_IP_DES_3DES_DES_K2LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014))
-#define INCA_IP_DES_3DES_DES_K2LR_K2L(value) (1 << value)
-
-
-/***DES Key #3 High Register***/
-#define INCA_IP_DES_3DES_DES_K3HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018))
-#define INCA_IP_DES_3DES_DES_K3HR_K3H(value) (1 << value)
-
-
-/***DES Key #3 Low Register***/
-#define INCA_IP_DES_3DES_DES_K3LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C))
-#define INCA_IP_DES_3DES_DES_K3LR_K3L(value) (1 << value)
-
-
-/***DES Initialization Vector High Register***/
-#define INCA_IP_DES_3DES_DES_IVHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020))
-#define INCA_IP_DES_3DES_DES_IVHR_IVH(value) (1 << value)
-
-
-/***DES Initialization Vector Low Register***/
-#define INCA_IP_DES_3DES_DES_IVLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024))
-#define INCA_IP_DES_3DES_DES_IVLR_IVL(value) (1 << value)
-
-
-/***DES Control Register***/
-#define INCA_IP_DES_3DES_DES_CONTROLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028))
-#define INCA_IP_DES_3DES_DES_CONTROLR_KRE (1 << 31)
-#define INCA_IP_DES_3DES_DES_CONTROLR_DAU (1 << 16)
-#define INCA_IP_DES_3DES_DES_CONTROLR_F(value) (1 << value)
-
-#define INCA_IP_DES_3DES_DES_CONTROLR_O(value) (1 << value)
-
-#define INCA_IP_DES_3DES_DES_CONTROLR_GO (1 << 8)
-#define INCA_IP_DES_3DES_DES_CONTROLR_STP (1 << 7)
-#define INCA_IP_DES_3DES_DES_CONTROLR_IEN (1 << 6)
-#define INCA_IP_DES_3DES_DES_CONTROLR_BUS (1 << 5)
-#define INCA_IP_DES_3DES_DES_CONTROLR_SM (1 << 4)
-#define INCA_IP_DES_3DES_DES_CONTROLR_E_D (1 << 3)
-#define INCA_IP_DES_3DES_DES_CONTROLR_M(value) (1 << value)
-
-
-/***DES Output Data High Register***/
-#define INCA_IP_DES_3DES_DES_OHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C))
-#define INCA_IP_DES_3DES_DES_OHR_OH(value) (1 << value)
-
-
-/***DES Output Data Low Register***/
-#define INCA_IP_DES_3DES_DES_OLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030))
-#define INCA_IP_DES_3DES_DES_OLR_OL(value) (1 << value)
-
-
-/***********************************************************************/
-/* Module : AES register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_AES (0xB8000880)
-/***********************************************************************/
-
-
-/***AES Input Data 3 Register***/
-#define INCA_IP_AES_AES_ID3R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID3R_I(value) (1 << value)
-
-
-/***AES Input Data 2 Register***/
-#define INCA_IP_AES_AES_ID2R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID2R_I(value) (1 << value)
-
-
-/***AES Input Data 1 Register***/
-#define INCA_IP_AES_AES_ID1R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID1R_I(value) (1 << value)
-
-
-/***AES Input Data 0 Register***/
-#define INCA_IP_AES_AES_ID0R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID0R_I(value) (1 << value)
-
-
-/***AES Output Data 3 Register***/
-#define INCA_IP_AES_AES_OD3R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD3R_O(value) (1 << value)
-
-
-/***AES Output Data 2 Register***/
-#define INCA_IP_AES_AES_OD2R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD2R_O(value) (1 << value)
-
-
-/***AES Output Data 1 Register***/
-#define INCA_IP_AES_AES_OD1R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD1R_O(value) (1 << value)
-
-
-/***AES Output Data 0 Register***/
-#define INCA_IP_AES_AES_OD0R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD0R_O(value) (1 << value)
-
-
-/***AES Key 7 Register***/
-#define INCA_IP_AES_AES_K7R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K7R_K(value) (1 << value)
-
-
-/***AES Key 6 Register***/
-#define INCA_IP_AES_AES_K6R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K6R_K(value) (1 << value)
-
-
-/***AES Key 5 Register***/
-#define INCA_IP_AES_AES_K5R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K5R_K(value) (1 << value)
-
-
-/***AES Key 4 Register***/
-#define INCA_IP_AES_AES_K4R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K4R_K(value) (1 << value)
-
-
-/***AES Key 3 Register***/
-#define INCA_IP_AES_AES_K3R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K3R_K(value) (1 << value)
-
-
-/***AES Key 2 Register***/
-#define INCA_IP_AES_AES_K2R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K2R_K(value) (1 << value)
-
-
-/***AES Key 1 Register***/
-#define INCA_IP_AES_AES_K1R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K1R_K(value) (1 << value)
-
-
-/***AES Key 0 Register***/
-#define INCA_IP_AES_AES_K0R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K0R_K(value) (1 << value)
-
-
-/***AES Initialization Vector 3 Register***/
-#define INCA_IP_AES_AES_IV3R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV3R_IV(value) (1 << value)
-
-
-/***AES Initialization Vector 2 Register***/
-#define INCA_IP_AES_AES_IV2R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV2R_IV(value) (1 << value)
-
-
-/***AES Initialization Vector 1 Register***/
-#define INCA_IP_AES_AES_IV1R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV1R_IV(value) (1 << value)
-
-
-/***AES Initialization Vector 0 Register***/
-#define INCA_IP_AES_AES_IV0R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV0R_IV (value) (((( 1 << 32) - 1) &(value)) << 0)
-
-/***AES Control Register***/
-#define INCA_IP_AES_AES_CONTROLR ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_CONTROLR_KRE (1 << 31)
-#define INCA_IP_AES_AES_CONTROLR_DAU (1 << 16)
-#define INCA_IP_AES_AES_CONTROLR_PNK (1 << 15)
-#define INCA_IP_AES_AES_CONTROLR_F(value) (1 << value)
-
-#define INCA_IP_AES_AES_CONTROLR_O(value) (1 << value)
-
-#define INCA_IP_AES_AES_CONTROLR_GO (1 << 8)
-#define INCA_IP_AES_AES_CONTROLR_STP (1 << 7)
-#define INCA_IP_AES_AES_CONTROLR_IEN (1 << 6)
-#define INCA_IP_AES_AES_CONTROLR_BUS (1 << 5)
-#define INCA_IP_AES_AES_CONTROLR_SM (1 << 4)
-#define INCA_IP_AES_AES_CONTROLR_E_D (1 << 3)
-#define INCA_IP_AES_AES_CONTROLR_KV (1 << 2)
-#define INCA_IP_AES_AES_CONTROLR_K(value) (1 << value)
-
-
-/***********************************************************************/
-/* Module : I²C register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_IIC (0xB8000700)
-/***********************************************************************/
-
-
-/***I²C Port Input Select Register***/
-#define INCA_IP_IIC_IIC_PISEL ((volatile u32*)(INCA_IP_IIC+ 0x0004))
-#define INCA_IP_IIC_IIC_PISEL_SDAIS(value) (1 << value)
-
-#define INCA_IP_IIC_IIC_PISEL_SCLIS(value) (1 << value)
-
-
-/***I²C Clock Control Register***/
-#define INCA_IP_IIC_IIC_CLC ((volatile u32*)(INCA_IP_IIC+ 0x0000))
-#define INCA_IP_IIC_IIC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_CLC_DISS (1 << 1)
-#define INCA_IP_IIC_IIC_CLC_DISR (1 << 0)
-
-/***I²C System Control Register***/
-#define INCA_IP_IIC_IIC_SYSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
-#define INCA_IP_IIC_IIC_SYSCON_0_WMEN (1 << 31)
-#define INCA_IP_IIC_IIC_SYSCON_0_CI (value) (((( 1 << 2) - 1) & (value)) << 26)
-#define INCA_IP_IIC_IIC_SYSCON_0_STP (1 << 25)
-#define INCA_IP_IIC_IIC_SYSCON_0_IGE (1 << 24)
-#define INCA_IP_IIC_IIC_SYSCON_0_TRX (1 << 23)
-#define INCA_IP_IIC_IIC_SYSCON_0_INT (1 << 22)
-#define INCA_IP_IIC_IIC_SYSCON_0_ACKDIS (1 << 21)
-#define INCA_IP_IIC_IIC_SYSCON_0_BUM (1 << 20)
-#define INCA_IP_IIC_IIC_SYSCON_0_MOD (value) (((( 1 << 2) - 1) & (value)) << 18)
-#define INCA_IP_IIC_IIC_SYSCON_0_RSC (1 << 17)
-#define INCA_IP_IIC_IIC_SYSCON_0_M10 (1 << 16)
-#define INCA_IP_IIC_IIC_SYSCON_0_RMEN (1 << 15)
-#define INCA_IP_IIC_IIC_SYSCON_0_CO (value) (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_SYSCON_0_IRQE (1 << 7)
-#define INCA_IP_IIC_IIC_SYSCON_0_IRQP (1 << 6)
-#define INCA_IP_IIC_IIC_SYSCON_0_IRQD (1 << 5)
-#define INCA_IP_IIC_IIC_SYSCON_0_BB (1 << 4)
-#define INCA_IP_IIC_IIC_SYSCON_0_LRB (1 << 3)
-#define INCA_IP_IIC_IIC_SYSCON_0_SLA (1 << 2)
-#define INCA_IP_IIC_IIC_SYSCON_0_AL (1 << 1)
-#define INCA_IP_IIC_IIC_SYSCON_0_ADR (1 << 0)
-
-/***I²C System Control Register***/
-#define INCA_IP_IIC_IIC_SYSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
-#define INCA_IP_IIC_IIC_SYSCON_1_RM (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_IIC_IIC_SYSCON_1_TRX (1 << 23)
-#define INCA_IP_IIC_IIC_SYSCON_1_INT (1 << 22)
-#define INCA_IP_IIC_IIC_SYSCON_1_ACKDIS (1 << 21)
-#define INCA_IP_IIC_IIC_SYSCON_1_BUM (1 << 20)
-#define INCA_IP_IIC_IIC_SYSCON_1_MOD (value) (((( 1 << 2) - 1) & (value)) << 18)
-#define INCA_IP_IIC_IIC_SYSCON_1_RSC (1 << 17)
-#define INCA_IP_IIC_IIC_SYSCON_1_M10 (1 << 16)
-#define INCA_IP_IIC_IIC_SYSCON_1_RMEN (1 << 15)
-#define INCA_IP_IIC_IIC_SYSCON_1_CO (value) (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_SYSCON_1_IRQE (1 << 7)
-#define INCA_IP_IIC_IIC_SYSCON_1_IRQP (1 << 6)
-#define INCA_IP_IIC_IIC_SYSCON_1_IRQD (1 << 5)
-#define INCA_IP_IIC_IIC_SYSCON_1_BB (1 << 4)
-#define INCA_IP_IIC_IIC_SYSCON_1_LRB (1 << 3)
-#define INCA_IP_IIC_IIC_SYSCON_1_SLA (1 << 2)
-#define INCA_IP_IIC_IIC_SYSCON_1_AL (1 << 1)
-#define INCA_IP_IIC_IIC_SYSCON_1_ADR (1 << 0)
-
-/***I²C System Control Register***/
-#define INCA_IP_IIC_IIC_SYSCON_2 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
-#define INCA_IP_IIC_IIC_SYSCON_2_WMEN (1 << 31)
-#define INCA_IP_IIC_IIC_SYSCON_2_CI (value) (((( 1 << 2) - 1) & (value)) << 26)
-#define INCA_IP_IIC_IIC_SYSCON_2_STP (1 << 25)
-#define INCA_IP_IIC_IIC_SYSCON_2_IGE (1 << 24)
-#define INCA_IP_IIC_IIC_SYSCON_2_TRX (1 << 23)
-#define INCA_IP_IIC_IIC_SYSCON_2_INT (1 << 22)
-#define INCA_IP_IIC_IIC_SYSCON_2_ACKDIS (1 << 21)
-#define INCA_IP_IIC_IIC_SYSCON_2_BUM (1 << 20)
-#define INCA_IP_IIC_IIC_SYSCON_2_MOD (value) (((( 1 << 2) - 1) & (value)) << 18)
-#define INCA_IP_IIC_IIC_SYSCON_2_RSC (1 << 17)
-#define INCA_IP_IIC_IIC_SYSCON_2_M10 (1 << 16)
-#define INCA_IP_IIC_IIC_SYSCON_2_WM (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_SYSCON_2_IRQE (1 << 7)
-#define INCA_IP_IIC_IIC_SYSCON_2_IRQP (1 << 6)
-#define INCA_IP_IIC_IIC_SYSCON_2_IRQD (1 << 5)
-#define INCA_IP_IIC_IIC_SYSCON_2_BB (1 << 4)
-#define INCA_IP_IIC_IIC_SYSCON_2_LRB (1 << 3)
-#define INCA_IP_IIC_IIC_SYSCON_2_SLA (1 << 2)
-#define INCA_IP_IIC_IIC_SYSCON_2_AL (1 << 1)
-#define INCA_IP_IIC_IIC_SYSCON_2_ADR (1 << 0)
-
-/***I²C Write Hardware Modified System Control Register
-***/
-#define INCA_IP_IIC_IIC_WHBSYSCON ((volatile u32*)(INCA_IP_IIC+ 0x0020))
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRWMEN (1 << 31)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETWMEN (1 << 30)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETSTP (1 << 26)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRSTP (1 << 25)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETTRX (1 << 24)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRTRX (1 << 23)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETACKDIS (1 << 22)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRACKDIS (1 << 21)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETBUM (1 << 20)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRBUM (1 << 19)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETRSC (1 << 17)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRSC (1 << 16)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETRMEN (1 << 15)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRMEN (1 << 14)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQE (1 << 10)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQP (1 << 9)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQD (1 << 8)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQE (1 << 7)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQP (1 << 6)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQD (1 << 5)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETAL (1 << 2)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRAL (1 << 1)
-
-/***I²C Bus Control Register***/
-#define INCA_IP_IIC_IIC_BUSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0014))
-#define INCA_IP_IIC_IIC_BUSCON_0_BRPMOD (1 << 31)
-#define INCA_IP_IIC_IIC_BUSCON_0_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_IIC_IIC_BUSCON_0_ICA9_0 (value) (((( 1 << 10) - 1) & (value)) << 16)
-#define INCA_IP_IIC_IIC_BUSCON_0_BRP (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_BUSCON_0_SCLEN(value) (1 << value)
-
-#define INCA_IP_IIC_IIC_BUSCON_0_SDAEN(value) (1 << value)
-
-
-/***I²C Bus Control Register***/
-#define INCA_IP_IIC_IIC_BUSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0014))
-#define INCA_IP_IIC_IIC_BUSCON_1_BRPMOD (1 << 31)
-#define INCA_IP_IIC_IIC_BUSCON_1_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_IIC_IIC_BUSCON_1_ICA7_1 (value) (((( 1 << 7) - 1) & (value)) << 17)
-#define INCA_IP_IIC_IIC_BUSCON_1_BRP (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_BUSCON_1_SCLEN(value) (1 << value)
-
-#define INCA_IP_IIC_IIC_BUSCON_1_SDAEN(value) (1 << value)
-
-
-/***I²C Receive Transmit Buffer***/
-#define INCA_IP_IIC_IIC_RTB ((volatile u32*)(INCA_IP_IIC+ 0x0018))
-#define INCA_IP_IIC_IIC_RTB_RTB(value) (1 << value)
-
-
-/***********************************************************************/
-/* Module : FB register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_FB (0xBF880000)
-/***********************************************************************/
-
-
-/***FB Access Error Cause Register***/
-#define INCA_IP_FB_FB_ERRCAUSE ((volatile u32*)(INCA_IP_FB+ 0x0100))
-#define INCA_IP_FB_FB_ERRCAUSE_ERR (1 << 31)
-#define INCA_IP_FB_FB_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_FB_FB_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***FB Access Error Address Register***/
-#define INCA_IP_FB_FB_ERRADDR ((volatile u32*)(INCA_IP_FB+ 0x0108))
-#define INCA_IP_FB_FB_ERRADDR_ADDR
-
-/***FB Configuration Register***/
-#define INCA_IP_FB_FB_CFG ((volatile u32*)(INCA_IP_FB+ 0x0800))
-#define INCA_IP_FB_FB_CFG_SVM (1 << 0)
-
-/***********************************************************************/
-/* Module : SRAM register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_SRAM (0xBF980000)
-/***********************************************************************/
-
-
-/***SRAM Size Register***/
-#define INCA_IP_SRAM_SRAM_SIZE ((volatile u32*)(INCA_IP_SRAM+ 0x0800))
-#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : BIU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_BIU (0xBFA80000)
-/***********************************************************************/
-
-
-/***BIU Identification Register***/
-#define INCA_IP_BIU_BIU_ID ((volatile u32*)(INCA_IP_BIU+ 0x0000))
-#define INCA_IP_BIU_BIU_ID_ARCH (1 << 16)
-#define INCA_IP_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***BIU Access Error Cause Register***/
-#define INCA_IP_BIU_BIU_ERRCAUSE ((volatile u32*)(INCA_IP_BIU+ 0x0100))
-#define INCA_IP_BIU_BIU_ERRCAUSE_ERR (1 << 31)
-#define INCA_IP_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***BIU Access Error Address Register***/
-#define INCA_IP_BIU_BIU_ERRADDR ((volatile u32*)(INCA_IP_BIU+ 0x0108))
-#define INCA_IP_BIU_BIU_ERRADDR_ADDR
-
-/***********************************************************************/
-/* Module : ICU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_ICU (0xBF101000)
-/***********************************************************************/
-
-
-/***IM0 Interrupt Status Register***/
-#define INCA_IP_ICU_IM0_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0000))
-#define INCA_IP_ICU_IM0_ISR_IR(value) (1 << value)
-
-
-/***IM1 Interrupt Status Register***/
-#define INCA_IP_ICU_IM1_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0200))
-#define INCA_IP_ICU_IM1_ISR_IR(value) (1 << value)
-
-
-/***IM2 Interrupt Status Register***/
-#define INCA_IP_ICU_IM2_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0400))
-#define INCA_IP_ICU_IM2_ISR_IR(value) (1 << value)
-
-
-/***IM0 Interrupt Enable Register***/
-#define INCA_IP_ICU_IM0_IER ((volatile u32*)(INCA_IP_ICU+ 0x0008))
-#define INCA_IP_ICU_IM0_IER_IR(value) (1 << value)
-
-
-/***IM1 Interrupt Enable Register***/
-#define INCA_IP_ICU_IM1_IER ((volatile u32*)(INCA_IP_ICU+ 0x0208))
-#define INCA_IP_ICU_IM1_IER_IR(value) (1 << value)
-
-
-/***IM2 Interrupt Enable Register***/
-#define INCA_IP_ICU_IM2_IER ((volatile u32*)(INCA_IP_ICU+ 0x0408))
-#define INCA_IP_ICU_IM2_IER_IR(value) (1 << value)
-
-
-/***IM0 Interrupt Output Status Register***/
-#define INCA_IP_ICU_IM0_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0010))
-#define INCA_IP_ICU_IM0_IOSR_IR(value) (1 << value)
-
-
-/***IM1 Interrupt Output Status Register***/
-#define INCA_IP_ICU_IM1_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0210))
-#define INCA_IP_ICU_IM1_IOSR_IR(value) (1 << value)
-
-
-/***IM2 Interrupt Output Status Register***/
-#define INCA_IP_ICU_IM2_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0410))
-#define INCA_IP_ICU_IM2_IOSR_IR(value) (1 << value)
-
-
-/***IM0 Interrupt Request Set Register***/
-#define INCA_IP_ICU_IM0_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0018))
-#define INCA_IP_ICU_IM0_IRSR_IR(value) (1 << value)
-
-
-/***IM1 Interrupt Request Set Register***/
-#define INCA_IP_ICU_IM1_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0218))
-#define INCA_IP_ICU_IM1_IRSR_IR(value) (1 << value)
-
-
-/***IM2 Interrupt Request Set Register***/
-#define INCA_IP_ICU_IM2_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0418))
-#define INCA_IP_ICU_IM2_IRSR_IR(value) (1 << value)
-
-
-/***External Interrupt Control Register***/
-#define INCA_IP_ICU_ICU_EICR ((volatile u32*)(INCA_IP_ICU+ 0x0B00))
-#define INCA_IP_ICU_ICU_EICR_EII5 (value) (((( 1 << 3) - 1) & (value)) << 20)
-#define INCA_IP_ICU_ICU_EICR_EII4 (value) (((( 1 << 3) - 1) & (value)) << 16)
-#define INCA_IP_ICU_ICU_EICR_EII3 (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_ICU_ICU_EICR_EII2 (value) (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_ICU_ICU_EICR_EII1 (value) (((( 1 << 3) - 1) & (value)) << 4)
-#define INCA_IP_ICU_ICU_EICR_EII0 (value) (((( 1 << 3) - 1) & (value)) << 0)
diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h
index 9f3cce9..a5b2fc0 100644
--- a/arch/mips/include/asm/u-boot-mips.h
+++ b/arch/mips/include/asm/u-boot-mips.h
@@ -21,5 +21,3 @@ static inline unsigned long image_copy_end(void)
extern char __image_copy_end[];
return (unsigned long) &__image_copy_end;
}
-
-extern int incaip_set_cpuclk(void);
diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h
index 985d7d8..0eb170d 100644
--- a/arch/mips/include/asm/u-boot.h
+++ b/arch/mips/include/asm/u-boot.h
@@ -15,6 +15,13 @@
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
+#ifdef CONFIG_SYS_GENERIC_BOARD
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+
+#else /* !CONFIG_SYS_GENERIC_BOARD */
+
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
@@ -26,6 +33,8 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
} bd_t;
+#endif /* !CONFIG_SYS_GENERIC_BOARD */
+
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_MIPS
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index fabeb83..e483e86 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -5,7 +5,11 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifndef CONFIG_SYS_GENERIC_BOARD
obj-y += board.o
+endif
+obj-y += io.o
+
obj-$(CONFIG_CMD_BOOTM) += bootm.o
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index 9e6ba15..3200d87 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -27,12 +27,6 @@ ulong monitor_flash_len;
static char *failed = "*** failed ***\n";
-/*
- * mips_io_port_base is the begin of the address space to which x86 style
- * I/O ports are mapped.
- */
-const unsigned long mips_io_port_base = -1;
-
int __board_early_init_f(void)
{
/*
@@ -109,9 +103,6 @@ init_fnc_t *init_sequence[] = {
board_early_init_f,
timer_init,
env_init, /* initialize environment */
-#ifdef CONFIG_INCA_IP
- incaip_set_cpuclk, /* set cpu clock according to env. variable */
-#endif
init_baudrate, /* initialize baudrate settings */
serial_init, /* serial communications setup */
console_init_f,
diff --git a/arch/mips/lib/io.c b/arch/mips/lib/io.c
new file mode 100644
index 0000000..b2d4a09
--- /dev/null
+++ b/arch/mips/lib/io.c
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * mips_io_port_base is the begin of the address space to which x86 style
+ * I/O ports are mapped.
+ */
+const unsigned long mips_io_port_base = -1;