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-rw-r--r--arch/i386/cpu/sc520/sc520.c33
-rw-r--r--arch/i386/cpu/sc520/sc520_pci.c24
-rw-r--r--arch/i386/cpu/sc520/sc520_ssi.c27
-rw-r--r--arch/i386/cpu/sc520/sc520_timer.c31
4 files changed, 63 insertions, 52 deletions
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 4b566a7..519bfd8 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -44,24 +44,24 @@ void init_sc520(void)
/* Set the UARTxCTL register at it's slower,
* baud clock giving us a 1.8432 MHz reference
*/
- sc520_mmcr->uart1ctl = 0x07;
- sc520_mmcr->uart2ctl = 0x07;
+ writeb(0x07, &sc520_mmcr->uart1ctl);
+ writeb(0x07, &sc520_mmcr->uart2ctl);
/* first set the timer pin mapping */
- sc520_mmcr->clksel = 0x72; /* no clock frequency selected, use 1.1892MHz */
+ writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */
/* enable PCI bus arbitrer */
- sc520_mmcr->sysarbctl = 0x02; /* enable concurrent mode */
+ writeb(0x02, &sc520_mmcr->sysarbctl); /* enable concurrent mode */
- sc520_mmcr->sysarbmenb = 0x1f; /* enable external grants */
- sc520_mmcr->hbctl = 0x04; /* enable posted-writes */
+ writeb(0x1f, &sc520_mmcr->sysarbmenb); /* enable external grants */
+ writeb(0x04, &sc520_mmcr->hbctl); /* enable posted-writes */
if (CONFIG_SYS_SC520_HIGH_SPEED) {
- sc520_mmcr->cpuctl = 0x02; /* set it to 133 MHz and write back */
+ writeb(0x02, &sc520_mmcr->cpuctl); /* set it to 133 MHz and write back */
gd->cpu_clk = 133000000;
printf("## CPU Speed set to 133MHz\n");
} else {
- sc520_mmcr->cpuctl = 0x01; /* set it to 100 MHz and write back */
+ writeb(0x01, &sc520_mmcr->cpuctl); /* set it to 100 MHz and write back */
printf("## CPU Speed set to 100MHz\n");
gd->cpu_clk = 100000000;
}
@@ -74,7 +74,7 @@ void init_sc520(void)
"loop 0b\n": : : "ecx");
/* turn on the SDRAM write buffer */
- sc520_mmcr->dbctl = 0x11;
+ writeb(0x11, &sc520_mmcr->dbctl);
/* turn on the cache and disable write through */
asm("movl %%cr0, %%eax\n"
@@ -88,6 +88,7 @@ unsigned long init_sc520_dram(void)
u32 dram_present=0;
u32 dram_ctrl;
+
#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
/* these memory control registers are set up in the assember part,
* in sc520_asm.S, during 'mem_init'. If we muck with them here,
@@ -97,7 +98,8 @@ unsigned long init_sc520_dram(void)
* simply dictates it.
*/
#else
- int val;
+ u8 tmp;
+ u8 val;
int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
@@ -116,9 +118,10 @@ unsigned long init_sc520_dram(void)
val = 3; /* 62.4us */
}
- sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4);
+ tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
+ writeb(tmp, &sc520_mmcr->drcctl);
- val = sc520_mmcr->drctmctl & 0xf0;
+ val = readb(&sc520_mmcr->drctmctl) & 0xf0;
if (cas_precharge_delay==3) {
val |= 0x04; /* 3T */
@@ -133,12 +136,12 @@ unsigned long init_sc520_dram(void)
} else {
val |= 1;
}
- sc520_mmcr->drctmctl = val;
+ writeb(val, &c520_mmcr->drctmctl);
#endif
/* We read-back the configuration of the dram
* controller that the assembly code wrote */
- dram_ctrl = sc520_mmcr->drcbendadr;
+ dram_ctrl = readl(&sc520_mmcr->drcbendadr);
bd->bi_dram[0].start = 0;
if (dram_ctrl & 0x80) {
@@ -191,7 +194,7 @@ void reset_cpu(ulong addr)
{
printf("Resetting using SC520 MMCR\n");
/* Write a '1' to the SYS_RST of the RESCFG MMCR */
- sc520_mmcr->rescfg = 0x01;
+ writeb(0x01, &sc520_mmcr->rescfg);
/* NOTREACHED */
}
diff --git a/arch/i386/cpu/sc520/sc520_pci.c b/arch/i386/cpu/sc520/sc520_pci.c
index f446c6d..ee7e720 100644
--- a/arch/i386/cpu/sc520/sc520_pci.c
+++ b/arch/i386/cpu/sc520/sc520_pci.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <pci.h>
+#include <asm/io.h>
#include <asm/pci.h>
#include <asm/ic/sc520.h>
@@ -63,6 +64,8 @@ int sc520_pci_ints[15] = {
int pci_sc520_set_irq(int pci_pin, int irq)
{
int i;
+ u8 tmpb;
+ u16 tmpw;
# if 1
printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
@@ -80,31 +83,34 @@ int pci_sc520_set_irq(int pci_pin, int irq)
/* PCI interrupt mapping (A through D)*/
for (i=0; i<=3 ;i++) {
- if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority)
- sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED;
+ if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority)
+ writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
}
/* GP IRQ interrupt mapping */
for (i=0; i<=10 ;i++) {
- if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority)
- sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED;
+ if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority)
+ writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
}
/* Set the trigger to level */
- sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] =
- sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit;
+ tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
+ tmpb |= sc520_irq[irq].level_bit;
+ writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
if (pci_pin < 4) {
/* PCI INTA-INTD */
/* route the interrupt */
- sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority;
+ writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]);
} else {
/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
- sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority;
+ writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]);
/* also set the polarity in this case */
- sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4));
+ tmpw = readw(&sc520_mmcr->intpinpol);
+ tmpw |= (1 << (pci_pin-4));
+ writew(tmpw, &sc520_mmcr->intpinpol);
}
/* register the pin */
diff --git a/arch/i386/cpu/sc520/sc520_ssi.c b/arch/i386/cpu/sc520/sc520_ssi.c
index 8dbe17a..6e5e346 100644
--- a/arch/i386/cpu/sc520/sc520_ssi.c
+++ b/arch/i386/cpu/sc520/sc520_ssi.c
@@ -24,6 +24,7 @@
/* stuff specific for the sc520, but independent of implementation */
#include <common.h>
+#include <asm/io.h>
#include <asm/ic/ssi.h>
#include <asm/ic/sc520.h>
@@ -61,34 +62,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
temp |= PHS_INV_ENB;
}
- sc520_mmcr->ssictl = temp;
+ writeb(temp, &sc520_mmcr->ssictl);
return 0;
}
u8 ssi_txrx_byte(u8 data)
{
- sc520_mmcr->ssixmit = data;
- while (sc520_mmcr->ssista & SSISTA_BSY);
- sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV;
- while (sc520_mmcr->ssista & SSISTA_BSY);
+ writeb(data, &sc520_mmcr->ssixmit);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
- return sc520_mmcr->ssircv;
+ return readb(&sc520_mmcr->ssircv);
}
void ssi_tx_byte(u8 data)
{
- sc520_mmcr->ssixmit = data;
- while (sc520_mmcr->ssista & SSISTA_BSY);
- sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT;
+ writeb(data, &sc520_mmcr->ssixmit);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
}
u8 ssi_rx_byte(void)
{
- while (sc520_mmcr->ssista & SSISTA_BSY);
- sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV;
- while (sc520_mmcr->ssista & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
- return sc520_mmcr->ssircv;
+ return readb(&sc520_mmcr->ssircv);
}
diff --git a/arch/i386/cpu/sc520/sc520_timer.c b/arch/i386/cpu/sc520/sc520_timer.c
index 93b5b55..eca48e0 100644
--- a/arch/i386/cpu/sc520/sc520_timer.c
+++ b/arch/i386/cpu/sc520/sc520_timer.c
@@ -24,13 +24,14 @@
/* stuff specific for the sc520, but independent of implementation */
#include <common.h>
+#include <asm/io.h>
#include <asm/interrupt.h>
#include <asm/ic/sc520.h>
void sc520_timer_isr(void)
{
/* Ack the GP Timer Interrupt */
- sc520_mmcr->gptmrsta = 0x02;
+ writeb(0x02, &sc520_mmcr->gptmrsta);
}
int timer_init(void)
@@ -42,28 +43,28 @@ int timer_init(void)
irq_install_handler (0, timer_isr, NULL);
/* Map GP Timer 1 to Master PIC IR0 */
- sc520_mmcr->gp_tmr_int_map[1] = 0x01;
+ writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]);
/* Disable GP Timers 1 & 2 - Allow configuration writes */
- sc520_mmcr->gptmr1ctl = 0x4000;
- sc520_mmcr->gptmr2ctl = 0x4000;
+ writew(0x4000, &sc520_mmcr->gptmr1ctl);
+ writew(0x4000, &sc520_mmcr->gptmr2ctl);
/* Reset GP Timers 1 & 2 */
- sc520_mmcr->gptmr1cnt = 0x0000;
- sc520_mmcr->gptmr2cnt = 0x0000;
+ writew(0x0000, &sc520_mmcr->gptmr1cnt);
+ writew(0x0000, &sc520_mmcr->gptmr2cnt);
/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
- sc520_mmcr->gptmr2maxcmpa = 83;
- sc520_mmcr->gptmr2ctl = 0xc001;
+ writew(83, &sc520_mmcr->gptmr2maxcmpa);
+ writew(0xc001, &sc520_mmcr->gptmr2ctl);
/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
- sc520_mmcr->gptmr1maxcmpa = 100;
- sc520_mmcr->gptmr1ctl = 0xe009;
+ writew(100, &sc520_mmcr->gptmr1maxcmpa);
+ writew(0xe009, &sc520_mmcr->gptmr1ctl);
unmask_irq (0);
/* Clear the GP Timer 1 status register to get the show rolling*/
- sc520_mmcr->gptmrsta = 0x02;
+ writeb(0x02, &sc520_mmcr->gptmrsta);
return 0;
}
@@ -74,11 +75,11 @@ void __udelay(unsigned long usec)
long u;
long temp;
- temp = sc520_mmcr->swtmrmilli;
- temp = sc520_mmcr->swtmrmicro;
+ temp = readw(&sc520_mmcr->swtmrmilli);
+ temp = readw(&sc520_mmcr->swtmrmicro);
do {
- m += sc520_mmcr->swtmrmilli;
- u = sc520_mmcr->swtmrmicro + (m * 1000);
+ m += readw(&sc520_mmcr->swtmrmilli);
+ u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000);
} while (u < usec);
}
generated by cgit v1.1 at 2024-12-25 00:42:34 +0000