diff options
Diffstat (limited to 'arch/blackfin/lib')
| -rw-r--r-- | arch/blackfin/lib/board.c | 21 | ||||
| -rw-r--r-- | arch/blackfin/lib/u-boot.lds.S | 10 |
2 files changed, 16 insertions, 15 deletions
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 8eca7d6..362b8c4 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -207,7 +207,6 @@ extern int timer_init(void); void board_init_f(ulong bootflag) { - ulong addr; bd_t *bd; char buf[32]; @@ -244,17 +243,12 @@ void board_init_f(ulong bootflag) gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR); memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); - /* Board data initialization */ - addr = (CONFIG_SYS_GBL_DATA_ADDR + sizeof(gd_t)); - - /* Align to 4 byte boundary */ - addr &= ~(4 - 1); - bd = (bd_t *) addr; + bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR); gd->bd = bd; - memset((void *)bd, 0, sizeof(bd_t)); + memset((void *)bd, 0, GENERATED_BD_INFO_SIZE); bd->bi_r_version = version_string; - bd->bi_cpu = BFIN_CPU; + bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU); bd->bi_board_name = BFIN_BOARD_NAME; bd->bi_vco = get_vco(); bd->bi_cclk = get_cclk(); @@ -283,8 +277,11 @@ void board_init_f(ulong bootflag) printf("Core: %s MHz, ", strmhz(buf, get_cclk())); printf("System: %s MHz\n", strmhz(buf, get_sclk())); - printf("RAM: "); - print_size(bd->bi_memsize, "\n"); + if (CONFIG_MEM_SIZE) { + printf("RAM: "); + print_size(bd->bi_memsize, "\n"); + } + #if defined(CONFIG_POST) post_init_f(); post_bootmode_init(); @@ -393,7 +390,7 @@ void board_init_r(gd_t * id, ulong dest_addr) post_run(NULL, POST_RAM | post_bootmode_get(0)); #endif - if (bfin_os_log_check()) { + if (CONFIG_MEM_SIZE && bfin_os_log_check()) { puts("\nLog buffer from operating system:\n"); bfin_os_log_dump(); puts("\n"); diff --git a/arch/blackfin/lib/u-boot.lds.S b/arch/blackfin/lib/u-boot.lds.S index f15c97e..2b8d285 100644 --- a/arch/blackfin/lib/u-boot.lds.S +++ b/arch/blackfin/lib/u-boot.lds.S @@ -40,9 +40,13 @@ * This is here in the first place so we can quickly test building * for different CPU's which may lack non-cache L1 data. */ +#ifndef L1_DATA_A_SRAM +# define L1_DATA_A_SRAM 0 +# define L1_DATA_A_SRAM_SIZE 0 +#endif #ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 +# define L1_DATA_B_SRAM L1_DATA_A_SRAM +# define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE #endif /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ @@ -138,7 +142,7 @@ SECTIONS } >l1_data AT>ram_data __data_l1_lma = LOADADDR(.data_l1); __data_l1_len = SIZEOF(.data_l1); - ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!") + ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!") .bss : { |