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-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/cpu.c17
-rw-r--r--arch/arm/include/asm/arch-kirkwood/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-kirkwood/gpio.h16
-rw-r--r--arch/arm/include/asm/arch-kirkwood/soc.h4
-rw-r--r--arch/arm/mvebu-common/Makefile1
-rw-r--r--arch/arm/mvebu-common/gpio.c30
6 files changed, 42 insertions, 28 deletions
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 75d3799..ea835fc 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -140,23 +140,6 @@ int kw_config_adr_windows(void)
}
/*
- * kw_config_gpio - GPIO configuration
- */
-void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
-{
- struct kwgpio_registers *gpio0reg =
- (struct kwgpio_registers *)KW_GPIO0_BASE;
- struct kwgpio_registers *gpio1reg =
- (struct kwgpio_registers *)KW_GPIO1_BASE;
-
- /* Init GPIOS to default values as per board requirement */
- writel(gpp0_oe_val, &gpio0reg->dout);
- writel(gpp1_oe_val, &gpio1reg->dout);
- writel(gpp0_oe, &gpio0reg->oe);
- writel(gpp1_oe, &gpio1reg->oe);
-}
-
-/*
* kw_config_mpp - Multi-Purpose Pins Functionality configuration
*
* Each MPP can be configured to different functionality through
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h
index 97daa40..5900a15 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -144,7 +144,7 @@ unsigned int kw_sdram_bar(enum memory_bank bank);
unsigned int kw_sdram_bs(enum memory_bank bank);
void kw_sdram_size_adjust(enum memory_bank bank);
int kw_config_adr_windows(void);
-void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
+void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
unsigned int mpp16_23, unsigned int mpp24_31,
diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h
index 5f4d786..aa8c5da 100644
--- a/arch/arm/include/asm/arch-kirkwood/gpio.h
+++ b/arch/arm/include/asm/arch-kirkwood/gpio.h
@@ -21,14 +21,14 @@
#define GPIO_MAX 50
#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000)
-#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
+#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
+#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
+#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
+#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
+#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
+#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
+#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
+#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
/*
* Kirkwood-specific GPIO API
diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h b/arch/arm/include/asm/arch-kirkwood/soc.h
index 29fb2d9..332cc24 100644
--- a/arch/arm/include/asm/arch-kirkwood/soc.h
+++ b/arch/arm/include/asm/arch-kirkwood/soc.h
@@ -26,8 +26,8 @@
#define KW_UART0_BASE (KW_REGISTER(0x12000))
#define KW_UART1_BASE (KW_REGISTER(0x12100))
#define KW_MPP_BASE (KW_REGISTER(0x10000))
-#define KW_GPIO0_BASE (KW_REGISTER(0x10100))
-#define KW_GPIO1_BASE (KW_REGISTER(0x10140))
+#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
+#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140))
#define KW_RTC_BASE (KW_REGISTER(0x10300))
#define KW_NANDF_BASE (KW_REGISTER(0x10418))
#define KW_SPI_BASE (KW_REGISTER(0x10600))
diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile
index 391a125..9dcab69 100644
--- a/arch/arm/mvebu-common/Makefile
+++ b/arch/arm/mvebu-common/Makefile
@@ -7,5 +7,6 @@
#
obj-y = dram.o
+obj-y += gpio.o
obj-$(CONFIG_ARMADA_XP) += mbus.o
obj-y += timer.o
diff --git a/arch/arm/mvebu-common/gpio.c b/arch/arm/mvebu-common/gpio.c
new file mode 100644
index 0000000..56e54e0
--- /dev/null
+++ b/arch/arm/mvebu-common/gpio.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+/*
+ * mvebu_config_gpio - GPIO configuration
+ */
+void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val,
+ u32 gpp0_oe, u32 gpp1_oe)
+{
+ struct kwgpio_registers *gpio0reg =
+ (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
+ struct kwgpio_registers *gpio1reg =
+ (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+
+ /* Init GPIOS to default values as per board requirement */
+ writel(gpp0_oe_val, &gpio0reg->dout);
+ writel(gpp1_oe_val, &gpio1reg->dout);
+ writel(gpp0_oe, &gpio0reg->oe);
+ writel(gpp1_oe, &gpio1reg->oe);
+}
generated by cgit v1.1 at 2024-10-30 07:23:52 +0000