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-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c12
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch329
-rw-r--r--arch/arm/dts/fsl-ls2080a-qds.dts14
-rw-r--r--arch/arm/dts/fsl-ls2080a.dtsi10
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/cpu.h4
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h4
6 files changed, 73 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 9a5a6b5..297687d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -636,6 +636,9 @@ int timer_init(void)
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
+#ifdef CONFIG_LS2080A
+ u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+#endif
#ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
@@ -650,6 +653,15 @@ int timer_init(void)
out_le32(cltbenr, 0xf);
#endif
+#ifdef CONFIG_LS2080A
+ /*
+ * In certain Layerscape SoCs, the clock for each core's
+ * has an enable bit in the PMU Physical Core Time Base Enable
+ * Register (PCTBENR), which allows the watchdog to operate.
+ */
+ setbits_le32(pctbenr, 0xff);
+#endif
+
/* Enable clock for timer
* This is a global setting.
*/
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index f9323c1..da5e052 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -121,6 +121,35 @@ mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
mcmemsize: MC DRAM block size. If this variable is not defined, the value
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+mcinitcmd: This environment variable is defined to initiate MC and DPL deployment
+ from the location where it is stored(NOR, NAND, SD, SATA, USB)during
+ u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
+ will be null and MC will not be booted and DPL will not be applied
+ during U-boot booting.However the MC, DPC and DPL can be applied from
+ console independently.
+ The variable needs to be set from the console once and then on
+ rebooting the parameters set in the varible will automatically be
+ executed. The commmand is demostrated taking an example of mc boot
+ using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash:
+
+ cp.b 0xa0000000 0x580300000 $filesize
+ cp.b 0x80000000 0x580800000 $filesize
+ cp.b 0x90000000 0x580700000 $filesize
+
+ setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000'
+
+ If only linux is to be booted then the mcinitcmd environment should be set as
+
+ setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
+
+ Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where
+ MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000
+ and 0x580700000 are addresses in NOR where these are copied. It is to be
+ noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
+ can be replaced with the addresses of DDR to
+ which these will be copied in case of these binaries being stored in other
+ devices like SATA, USB, NAND, SD etc.
+
Booting from NAND
-------------------
Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
aliases {
+ spi0 = &qspi;
spi1 = &dspi;
};
};
@@ -51,3 +52,16 @@
reg = <2>;
};
};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fs256s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+ qspi: quadspi@1550000 {
+ compatible = "fsl,vf610-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ num-cs = <4>;
+ };
};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 1cebe2f..df877dd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -122,6 +122,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+ { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE},
/* For IFC Region #1, only the first 4MB is cache-enabled */
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -176,6 +178,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+ { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357..8d12d6c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -26,6 +26,7 @@
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
@@ -128,6 +129,8 @@
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
#define DCFG_RCWSR13 0x130
#define DCFG_RCWSR13_DSPI (0 << 8)
+#define DCFG_RCWSR15 0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
#define DCFG_DCSR_BASE 0X700100000ULL
#define DCFG_DCSR_PORCR1 0x000
@@ -139,6 +142,7 @@
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
+#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
generated by cgit v1.1 at 2025-01-01 06:20:02 +0000