diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/cpu/arm926ejs/cpu.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 11 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/at91/sama5d4_devices.c | 16 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/ls102xa/fdt.c | 49 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/virt-v7.c | 9 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/zynq/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/zynq/config.mk | 7 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/zynq/cpu.c | 4 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/zynq/ddrc.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/zynq/lowlevel_init.S | 26 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/zynq/slcr.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/zynq/spl.c | 9 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-at91/atmel_usba_udc.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 5 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/gpio.h | 15 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-zynq/hardware.h | 5 | ||||
-rw-r--r-- | arch/arm/lib/cache.c | 2 |
18 files changed, 160 insertions, 11 deletions
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index e37e87b..a90ce30 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -45,7 +45,9 @@ int cleanup_before_linux (void) /* flush I/D-cache */ static void cache_flush (void) { +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long i = 0; asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); +#endif } diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index 9e412bb..4c9d3fd 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -181,7 +181,7 @@ static void kw_sysrst_check(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - char *rev; + char *rev = "??"; u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; @@ -192,7 +192,13 @@ int print_cpuinfo(void) switch (revid) { case 0: - rev = "Z0"; + if (devid == 0x6281) + rev = "Z0"; + else if (devid == 0x6282) + rev = "A0"; + break; + case 1: + rev = "A1"; break; case 2: rev = "A0"; @@ -201,7 +207,6 @@ int print_cpuinfo(void) rev = "A1"; break; default: - rev = "??"; break; } diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c b/arch/arm/cpu/armv7/at91/sama5d4_devices.c index 2708097..7469825 100644 --- a/arch/arm/cpu/armv7/at91/sama5d4_devices.c +++ b/arch/arm/cpu/armv7/at91/sama5d4_devices.c @@ -6,6 +6,10 @@ */ #include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/sama5d4.h> char *get_cpu_name() @@ -28,3 +32,15 @@ char *get_cpu_name() else return "Unknown CPU type"; } + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +void at91_udp_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable UPLL clock */ + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + /* Enable UDPHS clock */ + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 989780d..71a1753 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -15,6 +15,8 @@ #include <fsl_esdhc.h> #endif #include <tsec.h> +#include <asm/arch/immap_ls102xa.h> +#include <fsl_sec.h> DECLARE_GLOBAL_DATA_PTR; @@ -77,9 +79,24 @@ void ft_cpu_setup(void *blob, bd_t *bd) int off; int val; const char *sysclk_path; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr; + svr = in_be32(&gur->svr); unsigned long busclk = get_bus_freq(0); + /* delete crypto node if not on an E-processor */ + if (!IS_E_PROCESSOR(svr)) + fdt_fixup_crypto_node(blob, 0); +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 + else { + ccsr_sec_t __iomem *sec; + + sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); + } +#endif + fdt_fixup_ethernet(blob); off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); @@ -107,6 +124,25 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); +#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT) +#define UBOOT_HEAD_LEN 0x1000 + /* + * Reserved memory in SD boot deep sleep case. + * Second stage uboot binary and malloc space should be reserved. + * If the memory they occupied has not been reserved, then this + * space would be used by kernel and overwritten in uboot when + * deep sleep resume, which cause deep sleep failed. + * Since second uboot binary has a head, that space need to be + * reserved either(assuming its size is less than 0x1000). + */ + off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN, + CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE + + UBOOT_HEAD_LEN); + if (off < 0) + printf("Failed to reserve memory for SD boot deep sleep: %s\n", + fdt_strerror(off)); +#endif + #if defined(CONFIG_FSL_ESDHC) fdt_fixup_esdhc(blob, bd); #endif @@ -133,4 +169,17 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", "clock-frequency", busclk / 2, 1); + +#ifdef CONFIG_QSPI_BOOT + off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, + CONFIG_SYS_IFC_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +#else + off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, + QSPI0_BASE_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); + off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT, + DSPI1_BASE_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +#endif } diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 651ca40..b69fd37 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -15,8 +15,6 @@ #include <asm/io.h> #include <asm/secure.h> -unsigned long gic_dist_addr; - static unsigned int read_id_pfr1(void) { unsigned int reg; @@ -68,6 +66,12 @@ static void kick_secondary_cpus_gic(unsigned long gicdaddr) void __weak smp_kick_all_cpus(void) { + unsigned long gic_dist_addr; + + gic_dist_addr = get_gicd_base_address(); + if (gic_dist_addr == -1) + return; + kick_secondary_cpus_gic(gic_dist_addr); } @@ -75,6 +79,7 @@ int armv7_init_nonsec(void) { unsigned int reg; unsigned itlinesnr, i; + unsigned long gic_dist_addr; /* check whether the CPU supports the security extensions */ reg = read_id_pfr1(); diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile index 3363a3c..901f2ce 100644 --- a/arch/arm/cpu/armv7/zynq/Makefile +++ b/arch/arm/cpu/armv7/zynq/Makefile @@ -13,4 +13,5 @@ obj-y += cpu.o obj-y += ddrc.o obj-y += slcr.o obj-y += clk.o +obj-y += lowlevel_init.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/cpu/armv7/zynq/config.mk b/arch/arm/cpu/armv7/zynq/config.mk new file mode 100644 index 0000000..778a377 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/config.mk @@ -0,0 +1,7 @@ +# +# Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0 +# +# Allow NEON instructions (needed for lowlevel_init.S with GNU toolchain) +PLATFORM_RELFLAGS += -mfpu=neon diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 816d0c5..914b1fe 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -10,10 +10,6 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> -void lowlevel_init(void) -{ -} - #define ZYNQ_SILICON_VER_MASK 0xF0000000 #define ZYNQ_SILICON_VER_SHIFT 28 diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index d74f8db..5b20acc 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -42,6 +42,8 @@ void zynq_ddrc_init(void) */ /* cppcheck-suppress nullPointer */ memset((void *)0, 0, 1 * 1024 * 1024); + + gd->ram_size /= 2; } else { puts("ECC disabled "); } diff --git a/arch/arm/cpu/armv7/zynq/lowlevel_init.S b/arch/arm/cpu/armv7/zynq/lowlevel_init.S new file mode 100644 index 0000000..6d714b7 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/lowlevel_init.S @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + + /* Enable the the VFP */ + mrc p15, 0, r1, c1, c0, 2 + orr r1, r1, #(0x3 << 20) + orr r1, r1, #(0x3 << 20) + mcr p15, 0, r1, c1, c0, 2 + isb + fmrx r1, FPEXC + orr r1,r1, #(1<<30) + fmxr FPEXC, r1 + + /* Move back to caller */ + mov pc, lr + +ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 934ccc3..2521589 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void) zynq_slcr_unlock(); /* Disable AXI interface by asserting FPGA resets */ - writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); + writel(0xF, &slcr_base->fpga_rst_ctrl); /* Set Level Shifters DT618760 */ writel(0xA, &slcr_base->lvl_shftr_en); diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c index 0936bdd..b80c357 100644 --- a/arch/arm/cpu/armv7/zynq/spl.c +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -43,12 +43,21 @@ u32 spl_boot_device(void) mode = BOOT_DEVICE_SPI; break; #endif + case ZYNQ_BM_NAND: + mode = BOOT_DEVICE_NAND; + break; + case ZYNQ_BM_NOR: + mode = BOOT_DEVICE_NOR; + break; #ifdef CONFIG_SPL_MMC_SUPPORT case ZYNQ_BM_SD: puts("mmc boot\n"); mode = BOOT_DEVICE_MMC1; break; #endif + case ZYNQ_BM_JTAG: + mode = BOOT_DEVICE_RAM; + break; default: puts("Unsupported boot mode selected\n"); hang(); diff --git a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h index 6f540d2..38b5012 100644 --- a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h +++ b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h @@ -31,7 +31,7 @@ static struct usba_ep_data usba_udc_ep[] = { EP("ep5", 5, 1024, 3, 1, 1), EP("ep6", 6, 1024, 3, 1, 1), }; -#elif defined(CONFIG_SAMA5D3) +#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) static struct usba_ep_data usba_udc_ep[] = { EP("ep0", 0, 64, 1, 0, 0), EP("ep1", 1, 1024, 3, 1, 0), diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 5e934da..7915518 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -97,8 +97,13 @@ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_FSL_ERRATUM_A008378 #else #error SoC not defined #endif +#define FSL_IFC_COMPAT "fsl,ifc" +#define FSL_QSPI_COMPAT "fsl,ls1-qspi" +#define FSL_DSPI_COMPAT "fsl,vf610-dspi" + #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h new file mode 100644 index 0000000..b704436 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/gpio.h @@ -0,0 +1,15 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_LS102XA_GPIO_H_ +#define __ASM_ARCH_LS102XA_GPIO_H_ + +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 697d4ca..f70d568 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -105,6 +105,8 @@ struct ccsr_gur { #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 +#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 +#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 @@ -456,6 +458,8 @@ struct ccsr_ddr { #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 #define CCI400_CTRLORD_EN_BARRIER 0 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 /* CCI-400 registers */ struct ccsr_cci400 { diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 2aede0c..e2e0b73 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -21,6 +21,9 @@ #define ZYNQ_I2C_BASEADDR1 0xE0005000 #define ZYNQ_SPI_BASEADDR0 0xE0006000 #define ZYNQ_SPI_BASEADDR1 0xE0007000 +#define ZYNQ_QSPI_BASEADDR 0xE000D000 +#define ZYNQ_SMC_BASEADDR 0xE000E000 +#define ZYNQ_NAND_BASEADDR 0xE1000000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 #define ZYNQ_EFUSE_BASEADDR 0xF800D000 #define ZYNQ_USB_BASEADDR0 0xE0002000 @@ -28,7 +31,9 @@ /* Bootmode setting values */ #define ZYNQ_BM_MASK 0x7 +#define ZYNQ_BM_QSPI 0x1 #define ZYNQ_BM_NOR 0x2 +#define ZYNQ_BM_NAND 0x4 #define ZYNQ_BM_SD 0x5 #define ZYNQ_BM_JTAG 0x0 diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 9cedeac..74cfde6 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -25,10 +25,12 @@ __weak void flush_cache(unsigned long start, unsigned long size) #endif /* CONFIG_CPU_ARM1136 */ #ifdef CONFIG_CPU_ARM926EJS +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +#endif #endif /* CONFIG_CPU_ARM926EJS */ return; } |