19 files changed, 380 insertions, 118 deletions

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index eaf09d1..81477aa 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -285,14 +285,6 @@ void s_init(void)
 #ifdef CONFIG_NOR_BOOT
 	enable_norboot_pin_mux();
 #endif
-	/*
-	 * Save the boot parameters passed from romcode.
-	 * We cannot delay the saving further than this,
-	 * to prevent overwrites.
-	 */
-#ifdef CONFIG_SPL_BUILD
-	save_omap_boot_params();
-#endif
 	watchdog_disable();
 	set_uart_mux_conf();
 	setup_clocks_for_console();
@@ -301,9 +293,6 @@ void s_init(void)
 	gd->baudrate = CONFIG_BAUDRATE;
 	serial_init();
 	gd->have_console = 1;
-#elif defined(CONFIG_SPL_BUILD)
-	gd = &gdata;
-	preloader_console_init();
 #endif
 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 	/* Enable RTC32K clock */
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fc66872..85cceae 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -76,13 +76,13 @@ static void configure_mr(int nr, u32 cs)
 }
 
 /*
- * Configure EMIF4D5 registers and MR registers
+ * Configure EMIF4D5 registers and MR registers For details about these magic
+ * values please see the EMIF registers section of the TRM.
  */
 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 {
 	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
 	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
-	writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
 	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 
 	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
@@ -106,10 +106,45 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 		writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
 	}
 
-	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
-	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+	/*
+	 * Sequence to ensure that the PHY is in a known state prior to
+	 * startting hardware leveling.  Also acts as to latch some state from
+	 * the EMIF into the PHY.
+	 */
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+
+	clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+			EMIF_REG_INITREF_DIS_MASK);
+
 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+
+	/* Perform hardware leveling. */
+	udelay(1000);
+	writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
+	       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+	writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
+	       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+
+	writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+
+	/* Enable read leveling */
+	writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+
+	/*
+	 * Enable full read and write leveling.  Wait for read and write
+	 * leveling bit to clear RDWRLVLFULL_START bit 31
+	 */
+	while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
+		;
+
+	/* Check the timeout register to see if leveling is complete */
+	if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
+		puts("DDR3 H/W leveling incomplete with errors\n");
 
 	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
 		configure_mr(nr, 0);
@@ -123,21 +158,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 void config_sdram(const struct emif_regs *regs, int nr)
 {
 	if (regs->zq_config) {
-		/*
-		 * A value of 0x2800 for the REF CTRL will give us
-		 * about 570us for a delay, which will be long enough
-		 * to configure things.
-		 */
-		writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
 		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	}
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
-	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 }
 
 /**
@@ -153,46 +182,55 @@ void set_sdram_timings(const struct emif_regs *regs, int nr)
 	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 }
 
-void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
-{
-}
-
 /*
- * Configure EXT PHY registers
+ * Configure EXT PHY registers for hardware leveling
  */
 static void ext_phy_settings(const struct emif_regs *regs, int nr)
 {
-	u32 *ext_phy_ctrl_base = 0;
-	u32 *emif_ext_phy_ctrl_base = 0;
-	const u32 *ext_phy_ctrl_const_regs;
-	u32 i = 0;
-	u32 size;
-
-	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
-	emif_ext_phy_ctrl_base =
-			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
-
-	/* Configure external phy control timing registers */
-	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
-		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
-		/* Update shadow registers */
-		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
-	}
-
 	/*
-	 * external phy 6-24 registers do not change with
-	 * ddr frequency
+	 * Enable hardware leveling on the EMIF.  For details about these
+	 * magic values please see the EMIF registers section of the TRM.
 	 */
-	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
-
-	if (!size)
-		return;
+	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
+	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
+	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
+	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
+	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
+	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
+	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
+	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 
-	for (i = 0; i < size; i++) {
-		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
-		/* Update shadow registers */
-		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
-	}
+	/*
+	 * Sequence to ensure that the PHY is again in a known state after
+	 * hardware leveling.
+	 */
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 }
 
 /**
@@ -201,11 +239,17 @@ static void ext_phy_settings(const struct emif_regs *regs, int nr)
 void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
 	/*
-	 * disable initialization and refreshes for now until we
+	 * Disable initialization and refreshes for now until we
 	 * finish programming EMIF regs.
+	 * Also set time between rising edge of DDR_RESET to rising
+	 * edge of DDR_CKE to > 500us per memory spec.
 	 */
+#ifndef CONFIG_AM43XX
 	setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
 		     EMIF_REG_INITREF_DIS_MASK);
+#endif
+	if (regs->zq_config)
+		writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
 
 	writel(regs->emif_ddr_phy_ctlr_1,
 		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 8b7527c..9cf816c 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -112,17 +112,20 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
 #endif
 #ifdef CONFIG_AM43XX
 	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
 	while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
 		;
-	writel(0x80000000, &ddrctrl->ddrioctrl);
 
 	config_io_ctrl(ioregs);
 
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
+	/* Allow EMIF to control DDR_RESET */
+	writel(0x00000000, &ddrctrl->ddrioctrl);
 #endif
 
 	/* Program EMIF instance */
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 00a1082..17500f2 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -106,6 +106,16 @@ u32 spl_boot_mode(void)
 
 void spl_board_init(void)
 {
+	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+	save_omap_boot_params();
+
+	/* Prepare console output */
+	preloader_console_init();
+
 #ifdef CONFIG_SPL_NAND_SUPPORT
 	gpmc_init();
 #endif
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index dd52e93..cb35c19 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -111,14 +111,6 @@ int arch_cpu_init(void)
  */
 void s_init(void)
 {
-	/*
-	 * Save the boot parameters passed from romcode.
-	 * We cannot delay the saving further than this,
-	 * to prevent overwrites.
-	 */
-#ifdef CONFIG_SPL_BUILD
-	save_omap_boot_params();
-#endif
 	init_omap_revision();
 	hw_data_init();
 
@@ -133,9 +125,6 @@ void s_init(void)
 	srcomp_enable();
 	setup_clocks_for_console();
 
-	gd = &gdata;
-
-	preloader_console_init();
 	do_io_settings();
 #endif
 	prcm_init();
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 53a9e5d..90d6ae7 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -119,6 +119,7 @@ int board_mmc_init(bd_t *bis)
 
 void spl_board_init(void)
 {
+	preloader_console_init();
 #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
 	gpmc_init();
 #endif
@@ -264,14 +265,6 @@ void s_init(void)
 	ehci_clocks_enable();
 #endif
 
-#ifdef CONFIG_SPL_BUILD
-	gd = &gdata;
-
-	preloader_console_init();
-
-	timer_init();
-#endif
-
 	if (!in_sdram)
 		mem_init();
 }
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index bc98c56..f4a580a 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -46,9 +46,8 @@ u32 spl_boot_mode(void)
 {
 	return MMCSD_MODE_RAW;
 }
-#endif
 
-int gpio_init(void)
+static int gpio_init(void)
 {
 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
@@ -86,36 +85,9 @@ int gpio_init(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void board_init_f(ulong dummy)
 {
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
-	static const struct sunxi_wdog *wdog =
-		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
-
-	/* Set the watchdog for its shortest interval (.5s) and wait */
-	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
-	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
-
-	while (1) {
-		/* sun5i sometimes gets stuck without this */
-		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
-	}
-#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
-	static const struct sunxi_wdog *wdog =
-		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
-
-	/* Set the watchdog for its shortest interval (.5s) and wait */
-	writel(WDT_CFG_RESET, &wdog->cfg);
-	writel(WDT_MODE_EN, &wdog->mode);
-	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
-#endif
-}
-
-/* do some early init */
-void s_init(void)
-{
-#if defined CONFIG_SPL_BUILD && \
-		(defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 	/* Magic (undocmented) value taken from boot0, without this DRAM
 	 * access gets messed up (seems cache related) */
 	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
@@ -134,8 +106,6 @@ void s_init(void)
 	gpio_init();
 	i2c_init_board();
 
-#ifdef CONFIG_SPL_BUILD
-	gd = &gdata;
 	preloader_console_init();
 
 #ifdef CONFIG_SPL_I2C_SUPPORT
@@ -143,6 +113,36 @@ void s_init(void)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 	sunxi_board_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
+#endif
+
+void reset_cpu(ulong addr)
+{
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+	static const struct sunxi_wdog *wdog =
+		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+	/* Set the watchdog for its shortest interval (.5s) and wait */
+	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+
+	while (1) {
+		/* sun5i sometimes gets stuck without this */
+		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+	}
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
+	static const struct sunxi_wdog *wdog =
+		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+	/* Set the watchdog for its shortest interval (.5s) and wait */
+	writel(WDT_CFG_RESET, &wdog->cfg);
+	writel(WDT_MODE_EN, &wdog->mode);
+	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 #endif
 }
 
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
index 31627f9..0936bdd 100644
--- a/arch/arm/cpu/armv7/zynq/spl.c
+++ b/arch/arm/cpu/armv7/zynq/spl.c
@@ -20,9 +20,6 @@ void board_init_f(ulong dummy)
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
-	/* Set global data pointer. */
-	gd = &gdata;
-
 	preloader_console_init();
 	arch_cpu_init();
 	board_init_r(NULL, 0);
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 8dd69b3..b94b56c 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -219,6 +219,12 @@ struct cm_dpll {
 	unsigned int resv4[2];
 	unsigned int clklcdcpixelclk;	/* offset 0x34 */
 };
+
+struct prm_device_inst {
+	unsigned int prm_rstctrl;
+	unsigned int prm_rsttime;
+	unsigned int prm_rstst;
+};
 #else
 /* Encapsulating core pll registers */
 struct cm_wkuppll {
@@ -386,6 +392,11 @@ struct cm_device_inst {
 	unsigned int cm_dll_ctrl;
 };
 
+struct prm_device_inst {
+	unsigned int prm_rstctrl;
+	unsigned int prm_rstst;
+};
+
 struct cm_dpll {
 	unsigned int resv1;
 	unsigned int clktimer2clk;	/* offset 0x04 */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index c67a080..d1aed58 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -39,6 +39,7 @@
 /* VTP Base address */
 #define VTP0_CTRL_ADDR			0x44E10E0C
 #define VTP1_CTRL_ADDR			0x48140E10
+#define PRM_DEVICE_INST			0x44E00F00
 
 /* DDR Base address */
 #define DDR_PHY_CMD_ADDR		0x44E12000
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index efdecf4..29e3816 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -71,6 +71,7 @@
 #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
 #define USBPHYOCPSCP_MODULE_EN	(1 << 1)
 #define CM_DEVICE_INST			0x44df4100
+#define PRM_DEVICE_INST			0x44df4000
 
 /* Control status register */
 #define CTRL_CRYSTAL_FREQ_SRC_MASK		(1 << 31)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
index 132d58c..748b802 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -28,6 +28,12 @@
 #define MSTP10_BITS	0xFFFEFFE0
 #define MSTP11_BITS	0x00000000
 
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
+
 #define R8A7790_CUT_ES2X	2
 #define IS_R8A7790_ES2()	\
 	(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index d2cbcd7..1d06b65 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -17,6 +17,11 @@
 /* SH-I2C */
 #define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
 
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+
 #define DBSC3_1_QOS_R0_BASE	0xE67A1000
 #define DBSC3_1_QOS_R1_BASE	0xE67A1100
 #define DBSC3_1_QOS_R2_BASE	0xE67A1200
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793.h b/arch/arm/include/asm/arch-rmobile/r8a7793.h
index 1abdeb7..3efc62a 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7793.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7793.h
@@ -18,6 +18,11 @@
 /* SH-I2C */
 #define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
 
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+
 #define DBSC3_1_QOS_R0_BASE	0xE67A1000
 #define DBSC3_1_QOS_R1_BASE	0xE67A1100
 #define DBSC3_1_QOS_R2_BASE	0xE67A1200
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h
index d7c9004..6d11fa4 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7794.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h
@@ -27,4 +27,9 @@
 #define MSTP10_BITS	0xFFFEFFE0
 #define MSTP11_BITS	0x000001C0
 
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+
 #endif /* __ASM_ARCH_R8A7794_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index 23c4bba..d594cd7 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -82,6 +82,9 @@
 #define CONFIG_SYS_RCAR_I2C2_BASE	0xE6530000
 #define CONFIG_SYS_RCAR_I2C3_BASE	0xE6540000
 
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI0_BASE	0xEE100000
+
 #define S3C_BASE		0xE6784000
 #define S3C_INT_BASE		0xE6784A00
 #define S3C_MEDIA_BASE		0xE6784B00
diff --git a/arch/arm/include/asm/arch-rmobile/sh_sdhi.h b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h
new file mode 100644
index 0000000..057bf3f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h
@@ -0,0 +1,168 @@
+/*
+ * drivers/mmc/sh-sdhi.h
+ *
+ * SD/MMC driver for Reneas rmobile ARM SoCs
+ *
+ * Copyright (C) 2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2008-2009 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SH_SDHI_H
+#define _SH_SDHI_H
+
+#define SDHI_CMD			(0x0000 >> 1)
+#define SDHI_PORTSEL			(0x0004 >> 1)
+#define SDHI_ARG0			(0x0008 >> 1)
+#define SDHI_ARG1			(0x000C >> 1)
+#define SDHI_STOP			(0x0010 >> 1)
+#define SDHI_SECCNT			(0x0014 >> 1)
+#define SDHI_RSP00			(0x0018 >> 1)
+#define SDHI_RSP01			(0x001C >> 1)
+#define SDHI_RSP02			(0x0020 >> 1)
+#define SDHI_RSP03			(0x0024 >> 1)
+#define SDHI_RSP04			(0x0028 >> 1)
+#define SDHI_RSP05			(0x002C >> 1)
+#define SDHI_RSP06			(0x0030 >> 1)
+#define SDHI_RSP07			(0x0034 >> 1)
+#define SDHI_INFO1			(0x0038 >> 1)
+#define SDHI_INFO2			(0x003C >> 1)
+#define SDHI_INFO1_MASK			(0x0040 >> 1)
+#define SDHI_INFO2_MASK			(0x0044 >> 1)
+#define SDHI_CLK_CTRL			(0x0048 >> 1)
+#define SDHI_SIZE			(0x004C >> 1)
+#define SDHI_OPTION			(0x0050 >> 1)
+#define SDHI_ERR_STS1			(0x0058 >> 1)
+#define SDHI_ERR_STS2			(0x005C >> 1)
+#define SDHI_BUF0			(0x0060 >> 1)
+#define SDHI_SDIO_MODE			(0x0068 >> 1)
+#define SDHI_SDIO_INFO1			(0x006C >> 1)
+#define SDHI_SDIO_INFO1_MASK		(0x0070 >> 1)
+#define SDHI_CC_EXT_MODE		(0x01B0 >> 1)
+#define SDHI_SOFT_RST			(0x01C0 >> 1)
+#define SDHI_VERSION			(0x01C4 >> 1)
+#define SDHI_HOST_MODE			(0x01C8 >> 1)
+#define SDHI_SDIF_MODE			(0x01CC >> 1)
+#define SDHI_EXT_SWAP			(0x01E0 >> 1)
+#define SDHI_SD_DMACR			(0x0324 >> 1)
+
+/* SDHI CMD VALUE */
+#define CMD_MASK			0x0000ffff
+#define SDHI_APP			0x0040
+#define SDHI_SD_APP_SEND_SCR		0x0073
+#define SDHI_SD_SWITCH			0x1C06
+
+/* SDHI_PORTSEL */
+#define USE_1PORT			(1 << 8) /* 1 port */
+
+/* SDHI_ARG */
+#define ARG0_MASK			0x0000ffff
+#define ARG1_MASK			0x0000ffff
+
+/* SDHI_STOP */
+#define STOP_SEC_ENABLE			(1 << 8)
+
+/* SDHI_INFO1 */
+#define INFO1_RESP_END			(1 << 0)
+#define INFO1_ACCESS_END		(1 << 2)
+#define INFO1_CARD_RE			(1 << 3)
+#define INFO1_CARD_IN			(1 << 4)
+#define INFO1_ISD0CD			(1 << 5)
+#define INFO1_WRITE_PRO			(1 << 7)
+#define INFO1_DATA3_CARD_RE		(1 << 8)
+#define INFO1_DATA3_CARD_IN		(1 << 9)
+#define INFO1_DATA3			(1 << 10)
+
+/* SDHI_INFO2 */
+#define INFO2_CMD_ERROR			(1 << 0)
+#define INFO2_CRC_ERROR			(1 << 1)
+#define INFO2_END_ERROR			(1 << 2)
+#define INFO2_TIMEOUT			(1 << 3)
+#define INFO2_BUF_ILL_WRITE		(1 << 4)
+#define INFO2_BUF_ILL_READ		(1 << 5)
+#define INFO2_RESP_TIMEOUT		(1 << 6)
+#define INFO2_SDDAT0			(1 << 7)
+#define INFO2_BRE_ENABLE		(1 << 8)
+#define INFO2_BWE_ENABLE		(1 << 9)
+#define INFO2_CBUSY			(1 << 14)
+#define INFO2_ILA			(1 << 15)
+#define INFO2_ALL_ERR			(0x807f)
+
+/* SDHI_INFO1_MASK */
+#define INFO1M_RESP_END			(1 << 0)
+#define INFO1M_ACCESS_END		(1 << 2)
+#define INFO1M_CARD_RE			(1 << 3)
+#define INFO1M_CARD_IN			(1 << 4)
+#define INFO1M_DATA3_CARD_RE		(1 << 8)
+#define INFO1M_DATA3_CARD_IN		(1 << 9)
+#define INFO1M_ALL			(0xffff)
+#define INFO1M_SET			(INFO1M_RESP_END |	\
+					INFO1M_ACCESS_END |	\
+					INFO1M_DATA3_CARD_RE |	\
+					INFO1M_DATA3_CARD_IN)
+
+/* SDHI_INFO2_MASK */
+#define INFO2M_CMD_ERROR		(1 << 0)
+#define INFO2M_CRC_ERROR		(1 << 1)
+#define INFO2M_END_ERROR		(1 << 2)
+#define INFO2M_TIMEOUT			(1 << 3)
+#define INFO2M_BUF_ILL_WRITE		(1 << 4)
+#define INFO2M_BUF_ILL_READ		(1 << 5)
+#define INFO2M_RESP_TIMEOUT		(1 << 6)
+#define INFO2M_BRE_ENABLE		(1 << 8)
+#define INFO2M_BWE_ENABLE		(1 << 9)
+#define INFO2M_ILA			(1 << 15)
+#define INFO2M_ALL			(0xffff)
+#define INFO2M_ALL_ERR			(0x807f)
+
+/* SDHI_CLK_CTRL */
+#define CLK_ENABLE			(1 << 8)
+
+/* SDHI_OPTION */
+#define OPT_BUS_WIDTH_1			(1 << 15)	/* bus width = 1 bit */
+
+/* SDHI_ERR_STS1 */
+#define ERR_STS1_CRC_ERROR		((1 << 11) | (1 << 10) | (1 << 9) | \
+					(1 << 8) | (1 << 5))
+#define ERR_STS1_CMD_ERROR		((1 << 4) | (1 << 3) | (1 << 2) | \
+					(1 << 1) | (1 << 0))
+
+/* SDHI_ERR_STS2 */
+#define ERR_STS2_RES_TIMEOUT		(1 << 0)
+#define ERR_STS2_RES_STOP_TIMEOUT	((1 << 0) | (1 << 1))
+#define ERR_STS2_SYS_ERROR		((1 << 6) | (1 << 5) | (1 << 4) | \
+					(1 << 3) | (1 << 2) | (1 << 1) | \
+					(1 << 0))
+
+/* SDHI_SDIO_MODE */
+#define SDIO_MODE_ON			(1 << 0)
+#define SDIO_MODE_OFF			(0 << 0)
+
+/* SDHI_SDIO_INFO1 */
+#define SDIO_INFO1_IOIRQ		(1 << 0)
+#define SDIO_INFO1_EXPUB52		(1 << 14)
+#define SDIO_INFO1_EXWT			(1 << 15)
+
+/* SDHI_SDIO_INFO1_MASK */
+#define SDIO_INFO1M_CLEAR		((1 << 1) | (1 << 2))
+#define SDIO_INFO1M_ON			((1 << 15) | (1 << 14) | (1 << 2) | \
+					 (1 << 1) | (1 << 0))
+
+/* SDHI_EXT_SWAP */
+#define SET_SWAP			((1 << 6) | (1 << 7))	/* SWAP */
+
+/* SDHI_SOFT_RST */
+#define SOFT_RST_ON			(0 << 0)
+#define SOFT_RST_OFF			(1 << 0)
+
+#define	CLKDEV_SD_DATA			25000000	/* 25 MHz */
+#define CLKDEV_HS_DATA			50000000	/* 50 MHz */
+#define CLKDEV_MMC_DATA			20000000	/* 20MHz */
+#define	CLKDEV_INIT			400000		/* 100 - 400 KHz */
+
+/* For quirk */
+#define SH_SDHI_QUIRK_16BIT_BUF		(1)
+int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
+
+#endif /* _SH_SDHI_H */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 2fe5776..342f045 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -650,8 +650,8 @@ struct emif_reg_struct {
 	u32 emif_rd_wr_exec_thresh;
 	u32 emif_cos_config;
 	u32 padding9[6];
-	u32 emif_ddr_phy_status[21];
-	u32 padding10[27];
+	u32 emif_ddr_phy_status[28];
+	u32 padding10[20];
 	u32 emif_ddr_ext_phy_ctrl_1;
 	u32 emif_ddr_ext_phy_ctrl_1_shdw;
 	u32 emif_ddr_ext_phy_ctrl_2;
@@ -700,9 +700,36 @@ struct emif_reg_struct {
 	u32 emif_ddr_ext_phy_ctrl_23_shdw;
 	u32 emif_ddr_ext_phy_ctrl_24;
 	u32 emif_ddr_ext_phy_ctrl_24_shdw;
-	u32 padding[22];
-	u32 emif_ddr_fifo_misaligned_clear_1;
-	u32 emif_ddr_fifo_misaligned_clear_2;
+	u32 emif_ddr_ext_phy_ctrl_25;
+	u32 emif_ddr_ext_phy_ctrl_25_shdw;
+	u32 emif_ddr_ext_phy_ctrl_26;
+	u32 emif_ddr_ext_phy_ctrl_26_shdw;
+	u32 emif_ddr_ext_phy_ctrl_27;
+	u32 emif_ddr_ext_phy_ctrl_27_shdw;
+	u32 emif_ddr_ext_phy_ctrl_28;
+	u32 emif_ddr_ext_phy_ctrl_28_shdw;
+	u32 emif_ddr_ext_phy_ctrl_29;
+	u32 emif_ddr_ext_phy_ctrl_29_shdw;
+	u32 emif_ddr_ext_phy_ctrl_30;
+	u32 emif_ddr_ext_phy_ctrl_30_shdw;
+	u32 emif_ddr_ext_phy_ctrl_31;
+	u32 emif_ddr_ext_phy_ctrl_31_shdw;
+	u32 emif_ddr_ext_phy_ctrl_32;
+	u32 emif_ddr_ext_phy_ctrl_32_shdw;
+	u32 emif_ddr_ext_phy_ctrl_33;
+	u32 emif_ddr_ext_phy_ctrl_33_shdw;
+	u32 emif_ddr_ext_phy_ctrl_34;
+	u32 emif_ddr_ext_phy_ctrl_34_shdw;
+	u32 emif_ddr_ext_phy_ctrl_35;
+	u32 emif_ddr_ext_phy_ctrl_35_shdw;
+	union {
+		u32 emif_ddr_ext_phy_ctrl_36;
+		u32 emif_ddr_fifo_misaligned_clear_1;
+	};
+	union {
+		u32 emif_ddr_ext_phy_ctrl_36_shdw;
+		u32 emif_ddr_fifo_misaligned_clear_2;
+	};
 };
 
 struct dmm_lisa_map_regs {
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index dfcc596..c41850a 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -15,6 +15,11 @@
 
 /* Pointer to as well as the global data structure for SPL */
 DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * WARNING: This is going away very soon. Don't use it and don't submit
+ * pafches that rely on it. The global_data area is set up in crt0.S.
+ */
 gd_t gdata __attribute__ ((section(".data")));
 
 /*
@@ -28,7 +33,7 @@ void __weak board_init_f(ulong dummy)
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
-	/* Set global data pointer. */
+	/* TODO: Remove settings of the global data pointer here */
 	gd = &gdata;
 
 	board_init_r(NULL, 0);