diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/Makefile | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/cache_v7.c | 10 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/Kconfig | 25 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/psci-common.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/psci.c | 12 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/cache_v8.c | 4 | ||||
| -rw-r--r-- | arch/arm/dts/tegra186.dtsi | 270 | ||||
| -rw-r--r-- | arch/arm/include/asm/barriers.h | 11 | ||||
| -rw-r--r-- | arch/arm/include/asm/config.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/io.h | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/system.h | 8 | ||||
| -rw-r--r-- | arch/arm/lib/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/system.h | 10 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/dram_helpers.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/board186.c | 7 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra20/Makefile | 3 |
18 files changed, 311 insertions, 76 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a0a866e..5ac9401 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH config ARM64 bool + select PHYS_64BIT config DMA_ADDR_T_64BIT bool @@ -553,11 +554,14 @@ config TARGET_MX53SMD config OMAP34XX bool "OMAP34XX SoC" select CPU_V7 + select SUPPORT_SPL + select USE_TINY_PRINTF config OMAP44XX bool "OMAP44XX SoC" select CPU_V7 select SUPPORT_SPL + select USE_TINY_PRINTF config OMAP54XX bool "OMAP54XX SoC" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6a07cd1..82f2fd0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -20,6 +20,14 @@ arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7, -march=armv5)) arch-$(CONFIG_ARM64) =-march=armv8-a +# On Tegra systems we must build SPL for the armv4 core on the device +# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy) +arch-y += -D__LINUX_ARM_ARCH__=4 +else +arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) +endif + # Evaluate arch cc-option calls now arch-y := $(arch-y) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 52f1856..c4bbcc3 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -75,7 +75,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* DSB to make sure the operation is complete */ - DSB; + dsb(); } /* Invalidate TLB */ @@ -88,9 +88,9 @@ static void v7_inval_tlb(void) /* Invalidate entire instruction TLB */ asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - DSB; + dsb(); /* Full system ISB - make sure the instruction stream sees it */ - ISB; + isb(); } void invalidate_dcache_all(void) @@ -194,10 +194,10 @@ void invalidate_icache_all(void) asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - DSB; + dsb(); /* ISB - make sure the instruction stream sees it */ - ISB; + isb(); } #else void invalidate_icache_all(void) diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 85d6436..99a25f9 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -6,55 +6,39 @@ choice config TARGET_AM3517_EVM bool "AM3517 EVM" - select SUPPORT_SPL config TARGET_MT_VENTOUX bool "TeeJet Mt.Ventoux" - select SUPPORT_SPL config TARGET_OMAP3_BEAGLE bool "TI OMAP3 BeagleBoard" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_CM_T35 bool "CompuLab CM-T3530 and CM-T3730 boards" - select SUPPORT_SPL config TARGET_CM_T3517 bool "CompuLab CM-T3517 boards" config TARGET_DEVKIT8000 bool "TimLL OMAP3 Devkit8000" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_OMAP3_EVM bool "TI OMAP3 EVM" - select SUPPORT_SPL - -config TARGET_OMAP3_EVM_QUICK_MMC - bool "TI OMAP3 EVM Quick MMC" - select SUPPORT_SPL - -config TARGET_OMAP3_EVM_QUICK_NAND - bool "TI OMAP3 EVM Quick NAND" - select SUPPORT_SPL config TARGET_OMAP3_IGEP00X0 bool "IGEP" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_OMAP3_OVERO bool "OMAP35xx Gumstix Overo" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO @@ -67,51 +51,42 @@ config TARGET_OMAP3_ZOOM1 config TARGET_AM3517_CRANE bool "am3517_crane" - select SUPPORT_SPL config TARGET_OMAP3_PANDORA bool "OMAP3 Pandora" config TARGET_ECO5PK bool "ECO5PK" - select SUPPORT_SPL config TARGET_TRICORDER bool "Tricorder" - select SUPPORT_SPL config TARGET_MCX bool "MCX" - select SUPPORT_SPL config TARGET_OMAP3_LOGIC bool "OMAP3 Logic" select DM select DM_SERIAL select DM_GPIO - select SUPPORT_SPL config TARGET_NOKIA_RX51 bool "Nokia RX51" config TARGET_TAO3530 bool "TAO3530" - select SUPPORT_SPL config TARGET_TWISTER bool "Twister" - select SUPPORT_SPL config TARGET_OMAP3_CAIRO bool "QUIPOS CAIRO" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_SNIPER bool "LG Optimus Black" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 4fb5ef9..a8600b1 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -13,6 +13,7 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX" select TI_I2C_BOARD_DETECT + select PHYS_64BIT config TARGET_AM57XX_EVM bool "AM57XX" diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c index d14b693..8cb4107 100644 --- a/arch/arm/cpu/armv7/psci-common.c +++ b/arch/arm/cpu/armv7/psci-common.c @@ -29,7 +29,7 @@ static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 }; void __secure psci_save_target_pc(int cpu, u32 pc) { psci_target_pc[cpu] = pc; - DSB; + dsb(); } u32 __secure psci_get_target_pc(int cpu) diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 7ac8406..766b8c7 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -53,16 +53,16 @@ static void __secure __mdelay(u32 ms) u32 reg = ONE_MS * ms; cp15_write_cntp_tval(reg); - ISB; + isb(); cp15_write_cntp_ctl(3); do { - ISB; + isb(); reg = cp15_read_cntp_ctl(); } while (!(reg & BIT(2))); cp15_write_cntp_ctl(0); - ISB; + isb(); } static void __secure clamp_release(u32 __maybe_unused *clamp) @@ -164,7 +164,7 @@ static u32 __secure cp15_read_scr(void) static void __secure cp15_write_scr(u32 scr) { asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr)); - ISB; + isb(); } /* @@ -190,7 +190,7 @@ void __secure __irq psci_fiq_enter(void) /* End of interrupt */ writel(reg, GICC_BASE + GICC_EOIR); - DSB; + dsb(); /* Get CPU number */ cpu = (reg >> 10) & 0x7; @@ -242,7 +242,7 @@ void __secure psci_cpu_off(void) /* Ask CPU0 via SGI15 to pull the rug... */ writel(BIT(16) | 15, GICD_BASE + GICD_SGIR); - DSB; + dsb(); /* Wait to be turned off */ while (1) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index ac909a1..cd3f6c1 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -380,6 +380,7 @@ void setup_pgtables(void) static void setup_all_pgtables(void) { u64 tlb_addr = gd->arch.tlb_addr; + u64 tlb_size = gd->arch.tlb_size; /* Reset the fill ptr */ gd->arch.tlb_fillptr = tlb_addr; @@ -388,10 +389,13 @@ static void setup_all_pgtables(void) setup_pgtables(); /* Create emergency page tables */ + gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr - + (uintptr_t)gd->arch.tlb_addr; gd->arch.tlb_addr = gd->arch.tlb_fillptr; setup_pgtables(); gd->arch.tlb_emerg = gd->arch.tlb_addr; gd->arch.tlb_addr = tlb_addr; + gd->arch.tlb_size = tlb_size; } /* to activate the MMU we need to set up virtual memory */ diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index 99d4925..d9e7f03 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -1,14 +1,18 @@ #include "skeleton.dtsi" +#include <dt-bindings/clock/tegra186-clock.h> #include <dt-bindings/gpio/tegra186-gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/mailbox/tegra-hsp.h> +#include <dt-bindings/mailbox/tegra186-hsp.h> +#include <dt-bindings/power/tegra186-powergate.h> +#include <dt-bindings/reset/tegra186-reset.h> / { compatible = "nvidia,tegra186"; + interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; - gpio@2200000 { + gpio_main: gpio@2200000 { compatible = "nvidia,tegra186-gpio"; reg-names = "security", "gpio"; reg = @@ -34,26 +38,154 @@ status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x3160000 0x0 0x100>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C1>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C1>; + reset-names = "i2c"; + status = "disabled"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x3180000 0x0 0x100>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C3>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C3>; + reset-names = "i2c"; + status = "disabled"; + }; + + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x3190000 0x0 0x100>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C4>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C4>; + reset-names = "i2c"; + status = "disabled"; + }; + + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x31b0000 0x0 0x100>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C6>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C6>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen7_i2c: i2c@31c0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x31c0000 0x0 0x100>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C7>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C7>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen9_i2c: i2c@31e0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x31e0000 0x0 0x100>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C9>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C9>; + reset-names = "i2c"; + status = "disabled"; + }; + + sdhci@3400000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x0 0x03400000 0x0 0x200>; + resets = <&bpmp TEGRA186_RESET_SDMMC1>; + reset-names = "sdmmc"; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>; + clock-names = "sdmmc"; + interrupts = <GIC_SPI 62 0x04>; + status = "disabled"; + }; + sdhci@3460000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x200>; + resets = <&bpmp TEGRA186_RESET_SDMMC4>; + reset-names = "sdmmc"; + clocks = <&bpmp TEGRA186_CLK_SDMMC4>; + clock-names = "sdmmc"; interrupts = <GIC_SPI 31 0x04>; status = "disabled"; }; + gic: interrupt-controller@3881000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x3881000 0x0 0x1000>, + <0x0 0x3882000 0x0 0x2000>, + <0x0 0x3884000 0x0 0x2000>, + <0x0 0x3886000 0x0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + hsp: hsp@3c00000 { compatible = "nvidia,tegra186-hsp"; reg = <0x0 0x03c00000 0x0 0xa0000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - nvidia,num-SM = <0x8>; - nvidia,num-AS = <0x2>; - nvidia,num-SS = <0x2>; - nvidia,num-DB = <0x7>; - nvidia,num-SI = <0x8>; - #mbox-cells = <1>; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0xc240000 0x0 0x100>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C2>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C2>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0xc250000 0x0 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C8>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C8>; + reset-names = "i2c"; + status = "disabled"; }; - gpio@c2f0000 { + gpio_aon: gpio@c2f0000 { compatible = "nvidia,tegra186-gpio-aon"; reg-names = "security", "gpio"; reg = @@ -66,4 +198,124 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pcie-controller@10003000 { + compatible = "nvidia,tegra186-pcie"; + device_type = "pci"; + reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */ + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; /* Wake interrupt */ + interrupt-names = "intr", "msi", "wake"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ + 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ + 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */ + 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ + + clocks = <&bpmp TEGRA186_CLK_PCIE>, + <&bpmp TEGRA186_CLK_AFI>; + clock-names = "pex", "afi"; + resets = <&bpmp TEGRA186_RESET_PCIE>, + <&bpmp TEGRA186_RESET_AFI>, + <&bpmp TEGRA186_RESET_PCIEXCLK>; + reset-names = "pex", "afi", "pcie_x"; + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + + sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x0 0x30000000 0x0 0x50000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + + sysram_cpu_bpmp_tx: shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + }; + + sysram_cpu_bpmp_rx: shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + }; + }; + + bpmp: bpmp { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; + /* + * In theory, these references, and the configuration in the + * node these reference point at, are board-specific, since + * they depend on the BCT's memory carve-out setup, the + * firmware that's actually loaded onto the BPMP, etc. However, + * in practice, all boards are likely to use identical values. + */ + shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + bpmp_i2c: i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp = <&bpmp>; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm/include/asm/barriers.h b/arch/arm/include/asm/barriers.h index 37870f9..04784b7 100644 --- a/arch/arm/include/asm/barriers.h +++ b/arch/arm/include/asm/barriers.h @@ -30,15 +30,22 @@ #endif /* !CONFIG_ARM64 */ -#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64) +#if __LINUX_ARM_ARCH__ >= 7 #define ISB asm volatile ("isb sy" : : : "memory") #define DSB asm volatile ("dsb sy" : : : "memory") #define DMB asm volatile ("dmb sy" : : : "memory") -#else +#elif __LINUX_ARM_ARCH__ == 6 #define ISB CP15ISB #define DSB CP15DSB #define DMB CP15DMB +#else +#define ISB asm volatile ("" : : : "memory") +#define DSB CP15DSB +#define DMB asm volatile ("" : : : "memory") #endif +#define isb() ISB +#define dsb() DSB +#define dmb() DMB #endif /* __ASSEMBLY__ */ #endif /* __BARRIERS_H__ */ diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 435fc45..1ad221a 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_BOOT_RAMDISK_HIGH #ifdef CONFIG_ARM64 -#define CONFIG_PHYS_64BIT #define CONFIG_STATIC_RELA #endif diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 6121f1d..5834f5b 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -25,6 +25,7 @@ #include <linux/types.h> #include <asm/byteorder.h> #include <asm/memory.h> +#include <asm/barriers.h> #if 0 /* XXX###XXX */ #include <asm/arch/hardware.h> #endif /* XXX###XXX */ @@ -136,8 +137,7 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) * TODO: The kernel offers some more advanced versions of barriers, it might * have some advantages to use them instead of the simple one here. */ -#define mb() asm volatile("dsb sy" : : : "memory") -#define dmb() __asm__ __volatile__ ("" : : : "memory") +#define mb() dsb() #define __iormb() dmb() #define __iowmb() dmb() diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 2bdc0be..7b7b867 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -3,6 +3,7 @@ #include <common.h> #include <linux/compiler.h> +#include <asm/barriers.h> #ifdef CONFIG_ARM64 @@ -34,11 +35,6 @@ enum dcache_option { DCACHE_WRITEALLOC = 4 << 2, }; -#define isb() \ - ({asm volatile( \ - "isb" : : : "memory"); \ - }) - #define wfi() \ ({asm volatile( \ "wfi" : : : "memory"); \ @@ -227,8 +223,6 @@ void __noreturn psci_system_reset(bool smc); */ void save_boot_params_ret(void); -#define isb() __asm__ __volatile__ ("" : : : "memory") - #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); #ifdef __ARM_ARCH_7A__ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 9f71376..a8d1557 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -67,11 +67,6 @@ extra-y += eabi_compat.o endif asflags-y += -DCONFIG_ARM_ASM_UNIFIED -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy) -asflags-y += -D__LINUX_ARM_ARCH__=4 -else -asflags-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) -endif # some files can only build in ARM or THUMB2, not THUMB1 diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 3ffb296..2c94a6b 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -38,16 +38,6 @@ struct exynos5_sysreg { #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) /* - * Data Synchronization Barrier acts as a special kind of memory barrier. - * No instruction in program order after this instruction executes until - * this instruction completes. This instruction completes when: - * - All explicit memory accesses before this instruction complete. - * - All Cache, Branch predictor and TLB maintenance operations before - * this instruction complete. - */ -#define dsb() __asm__ __volatile__ ("dsb\n\t" : : ); - -/* * This instruction causes an event to be signaled to all cores * within a multiprocessor system. If SEV is implemented, * WFE must also be implemented. diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 20b430f..95143d1 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -32,7 +32,7 @@ bool mctl_mem_matches(u32 offset) /* Try to write different values to RAM at two addresses */ writel(0, CONFIG_SYS_SDRAM_BASE); writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); - DSB; + dsb(); /* Check if the same value is actually observed when reading back */ return readl(CONFIG_SYS_SDRAM_BASE) == readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c index 876ccba..a7583d4 100644 --- a/arch/arm/mach-tegra/board186.c +++ b/arch/arm/mach-tegra/board186.c @@ -16,11 +16,16 @@ int board_early_init_f(void) return 0; } -int board_init(void) +__weak int tegra_board_init(void) { return 0; } +int board_init(void) +{ + return tegra_board_init(); +} + int board_late_init(void) { return 0; diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 17c1990..72d82a5 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -10,7 +10,8 @@ endif # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_warmboot_avp.o += -march=armv4t +CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \ + -D__LINUX_ARM_ARCH__=4 obj-y += clock.o funcmux.o pinmux.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o |