diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/cpu/armv8/start.S | 2 | ||||
-rw-r--r-- | arch/arm/dts/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/dts/tegra20.dtsi | 57 | ||||
-rw-r--r-- | arch/arm/dts/tegra210-p2371-2180.dts | 60 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tegra/clock.h | 7 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tegra/gpio.h | 9 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tegra114/clock-tables.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tegra114/clock.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tegra124/clock-tables.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tegra124/clock.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tegra20/clock-tables.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tegra210/clock-tables.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tegra30/clock-tables.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-tegra/clock.c | 21 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra114/clock.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra124/clock.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra210/Kconfig | 9 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra210/clock.c | 21 |
18 files changed, 194 insertions, 22 deletions
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e70bed4..da45d98 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -54,8 +54,10 @@ reset: orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ msr scr_el3, x0 msr cptr_el3, xzr /* Enable FP/SIMD */ +#ifdef COUNTER_FREQUENCY ldr x0, =COUNTER_FREQUENCY msr cntfrq_el0, x0 /* Initialize CNTFRQ */ +#endif b 0f 2: msr vbar_el2, x0 mov x0, #0x33ff diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0a8c88d..5afe8a9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-venice2.dtb \ tegra210-e2220-1170.dtb \ tegra210-p2371-0000.dtb \ + tegra210-p2371-2180.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-ld4-ref.dtb \ diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index b8c8a92..e68d7be 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -320,6 +320,63 @@ clocks = <&tegra_car 47>, <&tegra_car 124>; }; + spi@7000d400 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d400 0x200>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d600 0x200>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d800 0x200>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000da00 0x200>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + kbc@7000e200 { compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x0078>; diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts new file mode 100644 index 0000000..5d9adcf --- /dev/null +++ b/arch/arm/dts/tegra210-p2371-2180.dts @@ -0,0 +1,60 @@ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA P2371-2180"; + compatible = "nvidia,p2371-2180", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@0,7000d000"; + sdhci0 = "/sdhci@0,700b0600"; + sdhci1 = "/sdhci@0,700b0000"; + usb0 = "/usb@0,7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + sdhci@0,700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_LOW>; + bus-width = <4>; + }; + + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + usb@0,7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index d570d7f..e56031d 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -44,6 +44,9 @@ enum { /* return the current oscillator clock frequency */ enum clock_osc_freq clock_get_osc_freq(void); +/* return the clk_m frequency */ +unsigned int clk_m_get_rate(unsigned int parent_rate); + /** * Start PLL using the provided configuration parameters. * @@ -338,8 +341,8 @@ void arch_timer_init(void); void tegra30_set_up_pllp(void); -/* Number of PLL-based clocks (i.e. not OSC or 32KHz) */ -#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2) +/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */ +#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3) struct clk_pll_info { u32 m_shift:5; /* DIVM_SHIFT */ diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index 7334e0c..daf5698 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -28,15 +28,6 @@ struct tegra_gpio_config { }; /** - * tegra_spl_gpio_direction_output() - set the output value of a GPIO - * - * This function is only used from SPL on seaboard, which needs to enable a - * GPIO to get the UART running. It could be done in U-Boot rather than SPL, - * but for now, this gets it working - */ -int tegra_spl_gpio_direction_output(int gpio, int value); - -/** * Configure a list of GPIOs * * @param config List of GPIO configurations diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h index d8fa0e1..3f910f5 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -38,6 +38,7 @@ enum clock_id { /* These are the base clocks (inputs to the Tegra SOC) */ CLOCK_ID_32KHZ, CLOCK_ID_OSC, + CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of PLLs */ CLOCK_ID_DISPLAY2, /* placeholder */ diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h index abbefcd..9bee397 100644 --- a/arch/arm/include/asm/arch-tegra114/clock.h +++ b/arch/arm/include/asm/arch-tegra114/clock.h @@ -25,4 +25,7 @@ #define OSC_FREQ_SHIFT 28 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ +#define PLLC_IDDQ (1 << 26) + #endif /* _TEGRA114_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h index 3c67e72..9466b4f 100644 --- a/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -30,6 +30,7 @@ enum clock_id { /* These are the base clocks (inputs to the Tegra SoC) */ CLOCK_ID_32KHZ, CLOCK_ID_OSC, + CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of PLLs */ diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h index e202cc5..ff99b9d 100644 --- a/arch/arm/include/asm/arch-tegra124/clock.h +++ b/arch/arm/include/asm/arch-tegra124/clock.h @@ -16,6 +16,9 @@ #define OSC_FREQ_SHIFT 28 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ +#define PLLC_IDDQ (1 << 26) + /* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */ #define SOR0_CLK_SEL0 (1 << 14) #define SOR0_CLK_SEL1 (1 << 15) diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h index 894be08..812e876 100644 --- a/arch/arm/include/asm/arch-tegra20/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h @@ -29,6 +29,7 @@ enum clock_id { /* These are the base clocks (inputs to the Tegra SOC) */ CLOCK_ID_32KHZ, CLOCK_ID_OSC, + CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of clocks */ CLOCK_ID_NONE = -1, diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h index 175040d..a612485 100644 --- a/arch/arm/include/asm/arch-tegra210/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h @@ -30,6 +30,7 @@ enum clock_id { /* These are the base clocks (inputs to the Tegra SoC) */ CLOCK_ID_32KHZ, CLOCK_ID_OSC, + CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of PLLs */ diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h index cb619f1..f7c7af8 100644 --- a/arch/arm/include/asm/arch-tegra30/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h @@ -38,6 +38,7 @@ enum clock_id { /* These are the base clocks (inputs to the Tegra SOC) */ CLOCK_ID_32KHZ, CLOCK_ID_OSC, + CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of PLLs */ CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */ diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index f9dfcd0..f75c6c6 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -461,6 +461,11 @@ void reset_cmplx_set_enable(int cpu, int which, int reset) writel(mask, &clkrst->crc_cpu_cmplx_clr); } +unsigned int __weak clk_m_get_rate(unsigned int parent_rate) +{ + return parent_rate; +} + unsigned clock_get_rate(enum clock_id clkid) { struct clk_pll *pll; @@ -472,6 +477,9 @@ unsigned clock_get_rate(enum clock_id clkid) if (clkid == CLOCK_ID_OSC) return parent_rate; + if (clkid == CLOCK_ID_CLK_M) + return clk_m_get_rate(parent_rate); + pll = get_pll(clkid); if (!pll) return 0; @@ -483,7 +491,16 @@ unsigned clock_get_rate(enum clock_id clkid) * PLLU uses p_mask/p_shift for VCO on all but T210, * T210 uses normal DIVP. Handled in pllinfo table. */ - divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; +#ifdef CONFIG_TEGRA210 + /* + * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is + * not applied. pllP_out2 does have divp applied. All other pllP_outN + * are divided down from pllP_out0. We only support pllP_out0 in + * U-Boot at the time of writing this comment. + */ + if (clkid != CLOCK_ID_PERIPH) +#endif + divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; do_div(rate, divm); return rate; } @@ -613,8 +630,10 @@ void clock_init(void) pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); + pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M); debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); + debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]); debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 5e805a7..e6ef873 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -629,6 +629,11 @@ void clock_early_init(void) tegra30_set_up_pllp(); + /* clear IDDQ before accessing any other PLLC registers */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); + udelay(2); + /* * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz @@ -679,8 +684,8 @@ void arch_timer_init(void) struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; u32 freq, val; - freq = clock_get_rate(CLOCK_ID_OSC); - debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + freq = clock_get_rate(CLOCK_ID_CLK_M); + debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); /* ARM CNTFRQ */ asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 61e8ab7..1e71146 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -809,6 +809,11 @@ void clock_early_init(void) tegra30_set_up_pllp(); + /* clear IDDQ before accessing any other PLLC registers */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); + udelay(2); + /* * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz @@ -859,8 +864,8 @@ void arch_timer_init(void) struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; u32 freq, val; - freq = clock_get_rate(CLOCK_ID_OSC); - debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + freq = clock_get_rate(CLOCK_ID_CLK_M); + debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); /* ARM CNTFRQ */ asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index bd34db7..b07363a 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -18,6 +18,14 @@ config TARGET_P2371_0000 HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, a GPIO expansion header, and an analog audio jack. +config TARGET_P2371_2180 + bool "NVIDIA Tegra210 P2371-2180 board" + help + P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The + combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB + micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and + two GPIO expansion headers. + config TARGET_P2571 bool "NVIDIA Tegra210 P2571 base board" help @@ -30,6 +38,7 @@ config SYS_SOC source "board/nvidia/e2220-1170/Kconfig" source "board/nvidia/p2371-0000/Kconfig" +source "board/nvidia/p2371-2180/Kconfig" source "board/nvidia/p2571/Kconfig" endif diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 830a33f..6d75d37 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -998,18 +998,27 @@ void clock_early_init(void) udelay(2); } +unsigned int clk_m_get_rate(unsigned parent_rate) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 value, div; + + value = readl(&clkrst->crc_spare_reg0); + div = ((value >> 2) & 0x3) + 1; + + return parent_rate / div; +} + void arch_timer_init(void) { struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; u32 freq, val; - freq = clock_get_rate(CLOCK_ID_OSC); - debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + freq = clock_get_rate(CLOCK_ID_CLK_M); + debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); - /* ARM CNTFRQ */ -#ifndef CONFIG_ARM64 - asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); -#endif + if (current_el() == 3) + asm("msr cntfrq_el0, %0\n" : : "r" (freq)); /* Only Tegra114+ has the System Counter regs */ debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); |