diff options
Diffstat (limited to 'arch/arm')
63 files changed, 3569 insertions, 371 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 72558b8..109d49f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -141,6 +141,12 @@ config ARCH_DAVINCI config KIRKWOOD bool "Marvell Kirkwood" +config TARGET_DB_MV784MP_GP + bool "Support db-mv784mp-gp" + +config TARGET_MAXBCM + bool "Support maxbcm" + config TARGET_DEVKIT3250 bool "Support devkit3250" @@ -567,6 +573,7 @@ source "board/BuS/eb_cpux9k2/Kconfig" source "board/BuS/vl_ma2sc/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" +source "board/Marvell/db-mv784mp-gp/Kconfig" source "board/Marvell/dkb/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/afeb9260/Kconfig" @@ -648,6 +655,7 @@ source "board/jornada/Kconfig" source "board/karo/tx25/Kconfig" source "board/logicpd/imx27lite/Kconfig" source "board/logicpd/imx31_litekit/Kconfig" +source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" source "board/palmld/Kconfig" diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile index c230ce8..df4756e 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile +++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile @@ -7,7 +7,5 @@ # obj-y = cpu.o -obj-y += dram.o -obj-y += mpp.o -obj-y += timer.o obj-y += cache.o +obj-y += mpp.o diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index 881e2de..9e412bb 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -9,14 +9,11 @@ #include <common.h> #include <netdev.h> #include <asm/cache.h> -#include <u-boot/md5.h> #include <asm/io.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <mvebu_mmc.h> -#define BUFLEN 16 - void reset_cpu(unsigned long ignored) { struct kwcpu_registers *cpureg = @@ -30,31 +27,6 @@ void reset_cpu(unsigned long ignored) } /* - * Generates Ramdom hex number reading some time varient system registers - * and using md5 algorithm - */ -unsigned char get_random_hex(void) -{ - int i; - u32 inbuf[BUFLEN]; - u8 outbuf[BUFLEN]; - - /* - * in case of 88F6281/88F6282/88F6192 A0, - * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470 - * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are - * reserved regs and does not have names at this moment - * (no errata available) - */ - writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478); - for (i = 0; i < BUFLEN; i++) { - inbuf[i] = readl(KW_REG_UNDOC_0x1470); - } - md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf); - return outbuf[outbuf[7] % 0x0f]; -} - -/* * Window Size * Used with the Base register to set the address window size and location. * Must be programmed from LSB to MSB as sequence of ones followed by @@ -140,50 +112,6 @@ int kw_config_adr_windows(void) } /* - * kw_config_gpio - GPIO configuration - */ -void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe) -{ - struct kwgpio_registers *gpio0reg = - (struct kwgpio_registers *)KW_GPIO0_BASE; - struct kwgpio_registers *gpio1reg = - (struct kwgpio_registers *)KW_GPIO1_BASE; - - /* Init GPIOS to default values as per board requirement */ - writel(gpp0_oe_val, &gpio0reg->dout); - writel(gpp1_oe_val, &gpio1reg->dout); - writel(gpp0_oe, &gpio0reg->oe); - writel(gpp1_oe, &gpio1reg->oe); -} - -/* - * kw_config_mpp - Multi-Purpose Pins Functionality configuration - * - * Each MPP can be configured to different functionality through - * MPP control register, ref (sec 6.1 of kirkwood h/w specification) - * - * There are maximum 64 Multi-Pourpose Pins on Kirkwood - * Each MPP functionality can be configuration by a 4bit value - * of MPP control reg, the value and associated functionality depends - * upon used SoC varient - */ -int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31, - u32 mpp32_39, u32 mpp40_47, u32 mpp48_55) -{ - u32 *mppreg = (u32 *) KW_MPP_BASE; - - /* program mpp registers */ - writel(mpp0_7, &mppreg[0]); - writel(mpp8_15, &mppreg[1]); - writel(mpp16_23, &mppreg[2]); - writel(mpp24_31, &mppreg[3]); - writel(mpp32_39, &mppreg[4]); - writel(mpp40_47, &mppreg[5]); - writel(mpp48_55, &mppreg[6]); - return 0; -} - -/* * SYSRSTn Duration Counter Support * * Kirkwood SoC implements a hardware-based SYSRSTn duration counter. diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c index 0ba6f09..7222504 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c @@ -12,7 +12,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> static u32 kirkwood_variant(void) diff --git a/arch/arm/cpu/armv7/armada-xp/Makefile b/arch/arm/cpu/armv7/armada-xp/Makefile new file mode 100644 index 0000000..885dcee --- /dev/null +++ b/arch/arm/cpu/armv7/armada-xp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = cpu.o diff --git a/arch/arm/cpu/armv7/armada-xp/cpu.c b/arch/arm/cpu/armv7/armada-xp/cpu.c new file mode 100644 index 0000000..1cf70a9 --- /dev/null +++ b/arch/arm/cpu/armv7/armada-xp/cpu.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) + +static struct mbus_win windows[] = { + /* PCIE MEM address space */ + { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM }, + + /* PCIE IO address space */ + { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO }, + + /* SPI */ + { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, + CPU_ATTR_SPIFLASH }, + + /* NOR */ + { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, + CPU_ATTR_BOOTROM }, +}; + +void reset_cpu(unsigned long ignored) +{ + struct mvebu_system_registers *reg = + (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; + + writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); + writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); + while (1) + ; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; + u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; + + puts("SoC: "); + + switch (devid) { + case SOC_MV78460_ID: + puts("MV78460-"); + break; + default: + puts("Unknown-"); + break; + } + + switch (revid) { + case 1: + puts("A0\n"); + break; + case 2: + puts("B0\n"); + break; + default: + puts("??\n"); + break; + } + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +/* + * This function initialize Controller DRAM Fastpath windows. + * It takes the CS size information from the 0x1500 scratch registers + * and sets the correct windows sizes and base addresses accordingly. + * + * These values are set in the scratch registers by the Marvell + * DDR3 training code, which is executed by the BootROM before the + * main payload (U-Boot) is executed. This training code is currently + * only available in the Marvell U-Boot version. It needs to be + * ported to mainline U-Boot SPL at some point. + */ +static void update_sdram_window_sizes(void) +{ + u64 base = 0; + u32 size, temp; + int i; + + for (i = 0; i < SDRAM_MAX_CS; i++) { + size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; + if (size != 0) { + size |= ~(SDRAM_ADDR_MASK); + + /* Set Base Address */ + temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); + writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); + + /* + * Check if out of max window size and resize + * the window + */ + temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & + ~(SDRAM_ADDR_MASK)) | 1; + temp |= (size & SDRAM_ADDR_MASK); + writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); + + base += ((u64)size + 1); + } else { + /* + * Disable window if not used, otherwise this + * leads to overlapping enabled windows with + * pretty strange results + */ + clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); + } + } +} + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + /* Linux expects the internal registers to be at 0xf1000000 */ + writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); + + /* + * We need to call mvebu_mbus_probe() before calling + * update_sdram_window_sizes() as it disables all previously + * configured mbus windows and then configures them as + * required for U-Boot. Calling update_sdram_window_sizes() + * without this configuration will not work, as the internal + * registers can't be accessed reliably because of potenial + * double mapping. + * After updating the SDRAM access windows we need to call + * mvebu_mbus_probe() again, as this now correctly configures + * the SDRAM areas that are later used by the MVEBU drivers + * (e.g. USB, NETA). + */ + + /* + * First disable all windows + */ + mvebu_mbus_probe(NULL, 0); + + /* + * Now the SDRAM access windows can be reconfigured using + * the information in the SDRAM scratch pad registers + */ + update_sdram_window_sizes(); + + /* + * Finally the mbus windows can be configured with the + * updated SDRAM sizes + */ + mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); + + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + +/* + * SOC specific misc init + */ +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + /* Nothing yet, perhaps we need something here later */ + return 0; +} +#endif /* CONFIG_ARCH_MISC_INIT */ + +#ifdef CONFIG_MVNETA +int cpu_eth_init(bd_t *bis) +{ + mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0); + mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1); + mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2); + mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3); + + return 0; +} +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index b929486..3d95dc3 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -7,7 +7,7 @@ #include <common.h> #include <fdtdec.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/sromc.h> @@ -172,6 +172,9 @@ static int exynos5420_mmc_config(int peripheral, int flags) * this same assumption. */ if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { +#ifndef CONFIG_SPL_BUILD + gpio_request(i, "sdmmc0_vdden"); +#endif gpio_set_value(i, 1); gpio_cfg_pin(i, S5P_GPIO_OUTPUT); } else { diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index bcae2d6..3ea6d76 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -17,6 +17,9 @@ config TEGRA124 endchoice +config USE_PRIVATE_LIBGCC + default y if SPL_BUILD + config SYS_CPU default "arm720t" if SPL_BUILD default "armv7" if !SPL_BUILD diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi index 110eb43..77fad48 100644 --- a/arch/arm/dts/exynos4.dtsi +++ b/arch/arm/dts/exynos4.dtsi @@ -7,9 +7,16 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x10440000 0x1000>; + }; + serial@13800000 { compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x3c>; diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts index 15059d2..dd2476c 100644 --- a/arch/arm/dts/exynos4210-origen.dts +++ b/arch/arm/dts/exynos4210-origen.dts @@ -8,8 +8,8 @@ */ /dts-v1/; -/include/ "skeleton.dtsi" -/include/ "exynos4.dtsi" +#include "skeleton.dtsi" +#include "exynos4210.dtsi" / { model = "Insignal Origen evaluation board based on Exynos4210"; diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi new file mode 100644 index 0000000..ee071c1 --- /dev/null +++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi @@ -0,0 +1,27 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + pinctrl_0: pinctrl@11400000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos4210-pinctrl"; + }; + + pinctrl_1: pinctrl@11000000 { + #address-cells = <1>; + #size-cells = <0>; + gpy0: gpy0 { + reg = <0xc00>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos4210-pinctrl.dtsi b/arch/arm/dts/exynos4210-pinctrl.dtsi new file mode 100644 index 0000000..bda17f7 --- /dev/null +++ b/arch/arm/dts/exynos4210-pinctrl.dtsi @@ -0,0 +1,304 @@ +/* + * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2011-2012 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@11400000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe2: gpe2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe3: gpe3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe4: gpe4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@11000000 { + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl1: gpl1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl2: gpl2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/exynos4210-smdkv310.dts b/arch/arm/dts/exynos4210-smdkv310.dts index c390c8f..00cad04 100644 --- a/arch/arm/dts/exynos4210-smdkv310.dts +++ b/arch/arm/dts/exynos4210-smdkv310.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "exynos4.dtsi" +#include "exynos4.dtsi" / { model = "Samsung SMDKV310 on Exynos4210"; diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts index 0ff6939..81188bc 100644 --- a/arch/arm/dts/exynos4210-trats.dts +++ b/arch/arm/dts/exynos4210-trats.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "exynos4.dtsi" +#include "exynos4210.dtsi" / { model = "Samsung Trats based on Exynos4210"; diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts index 6941906..9139810 100644 --- a/arch/arm/dts/exynos4210-universal_c210.dts +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "exynos4.dtsi" +#include "exynos4210.dtsi" / { model = "Samsung Universal C210 based on Exynos4210 rev0"; @@ -41,6 +41,19 @@ status = "disabled"; }; + soft-spi { + compatible = "u-boot,soft-spi"; + cs-gpio = <&gpio 235 0>; /* Y43 */ + sclk-gpio = <&gpio 225 0>; /* Y31 */ + mosi-gpio = <&gpio 227 0>; /* Y33 */ + miso-gpio = <&gpio 224 0>; /* Y30 */ + spi-delay-us = <1>; + #address-cells = <1>; + #size-cells = <0>; + cs@0 { + }; + }; + fimd@11c00000 { compatible = "samsung,exynos-fimd"; reg = <0x11c00000 0xa4>; diff --git a/arch/arm/dts/exynos4210.dtsi b/arch/arm/dts/exynos4210.dtsi new file mode 100644 index 0000000..634a5c1 --- /dev/null +++ b/arch/arm/dts/exynos4210.dtsi @@ -0,0 +1,156 @@ +/* + * Samsung's Exynos4210 SoC device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "exynos4.dtsi" +#include "exynos4210-pinctrl.dtsi" +#include "exynos4210-pinctrl-uboot.dtsi" + +/ { + compatible = "samsung,exynos4210"; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + }; + + pd_lcd1: lcd1-power-domain@10023CA0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CA0 0x20>; + }; + + gic: interrupt-controller@10490000 { + cpu-offset = <0x8000>; + }; + + combiner: interrupt-controller@10440000 { + samsung,combiner-nr = <16>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + }; + + mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>; + clocks = <&clock 3>, <&clock 344>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &gic 0 69 0>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 0 42 0>, + <5 &gic 0 48 0>; + }; + }; + + clock: clock-controller@10030000 { + compatible = "samsung,exynos4210-clock"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&combiner>; + interrupts = <2 2>, <3 2>; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 46 0>; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x03860000 0x1000>; + }; + + tmu@100C0000 { + compatible = "samsung,exynos4210-tmu"; + interrupt-parent = <&combiner>; + reg = <0x100C0000 0x100>; + interrupts = <2 4>; + clocks = <&clock 383>; + clock-names = "tmu_apbif"; + status = "disabled"; + }; + + g2d@12800000 { + compatible = "samsung,s5pv210-g2d"; + reg = <0x12800000 0x1000>; + interrupts = <0 89 0>; + clocks = <&clock 177>, <&clock 277>; + clock-names = "sclk_fimg2d", "fimg2d"; + status = "disabled"; + }; + + camera { + clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; + + fimc_0: fimc@11800000 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,cam-if; + }; + + fimc_1: fimc@11810000 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,cam-if; + }; + + fimc_2: fimc@11820000 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,lcd-wb; + }; + + fimc_3: fimc@11830000 { + samsung,pix-limits = <1920 8192 1366 1920>; + samsung,rotators = <0>; + samsung,mainscaler-ext; + samsung,lcd-wb; + }; + }; +}; diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index 24d0bf1..4c5e2b3 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "exynos4.dtsi" +#include "exynos4.dtsi" / { model = "Odroid based on Exynos4412"; diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts index cc58c87..3b1e458 100644 --- a/arch/arm/dts/exynos4412-trats2.dts +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "exynos4.dtsi" +#include "exynos4412.dtsi" / { model = "Samsung Trats2 based on Exynos4412"; diff --git a/arch/arm/dts/exynos4412.dtsi b/arch/arm/dts/exynos4412.dtsi new file mode 100644 index 0000000..87b339c --- /dev/null +++ b/arch/arm/dts/exynos4412.dtsi @@ -0,0 +1,38 @@ +/* + * Samsung's Exynos4412 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4412"; + + gic: interrupt-controller@10490000 { + cpu-offset = <0x4000>; + }; + + interrupt-controller@10440000 { + samsung,combiner-nr = <20>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; + }; + +}; diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi new file mode 100644 index 0000000..c02796d --- /dev/null +++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi @@ -0,0 +1,46 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + pinctrl_0: pinctrl@11400000 { + #address-cells = <1>; + #size-cells = <0>; + gpf0: gpf0 { + reg = <0xc180>; + }; + gpj0: gpj0 { + reg = <0x240>; + }; + }; + + pinctrl_1: pinctrl@11000000 { + #address-cells = <1>; + #size-cells = <0>; + gpk0: gpk0 { + reg = <0x40>; + }; + gpm0: gpm0 { + reg = <0x260>; + }; + gpy0: gpy0 { + reg = <0x120>; + }; + gpx0: gpx0 { + reg = <0xc00>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + + pinctrl_3: pinctrl@106E0000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos4x12-pinctrl.dtsi b/arch/arm/dts/exynos4x12-pinctrl.dtsi new file mode 100644 index 0000000..93f3998 --- /dev/null +++ b/arch/arm/dts/exynos4x12-pinctrl.dtsi @@ -0,0 +1,344 @@ +/* + * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@11400000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl@11000000 { + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl1: gpl1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl2: gpl2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl@106E0000 { + gpv0: gpv0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm/dts/exynos4x12.dtsi b/arch/arm/dts/exynos4x12.dtsi new file mode 100644 index 0000000..5d58c6e --- /dev/null +++ b/arch/arm/dts/exynos4x12.dtsi @@ -0,0 +1,115 @@ +/* + * Samsung's Exynos4x12 SoCs device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as +` * published by the Free Software Foundation. +*/ + +#include "exynos4.dtsi" +#include "exynos4x12-pinctrl.dtsi" +#include "exynos4x12-pinctrl-uboot.dtsi" + +/ { + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + mshc0 = &mshc_0; + }; + + pd_isp: isp-power-domain@10023CA0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CA0 0x20>; + }; + + clock: clock-controller@10030000 { + compatible = "samsung,exynos4412-clock"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + + mct@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>; + clocks = <&clock 3>, <&clock 344>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &combiner 12 5>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 1 12 0>; + }; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 46 0>; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x03860000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 0>; + }; + + pinctrl_3: pinctrl@106E0000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x106E0000 0x1000>; + interrupts = <0 72 0>; + }; + + g2d@10800000 { + compatible = "samsung,exynos4212-g2d"; + reg = <0x10800000 0x1000>; + interrupts = <0 89 0>; + clocks = <&clock 177>, <&clock 277>; + clock-names = "sclk_fimg2d", "fimg2d"; + status = "disabled"; + }; + + mshc_0: mmc@12550000 { + compatible = "samsung,exynos4412-dw-mshc"; + reg = <0x12550000 0x1000>; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <0x80>; + clocks = <&clock 301>, <&clock 149>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi index a2b533a..e539068 100644 --- a/arch/arm/dts/exynos5.dtsi +++ b/arch/arm/dts/exynos5.dtsi @@ -5,11 +5,38 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "samsung,exynos5"; + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + samsung,combiner-nr = <32>; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + sromc@12250000 { compatible = "samsung,exynos-sromc"; reg = <0x12250000 0x20>; @@ -17,6 +44,33 @@ #size-cells = <0>; }; + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + samsung,combiner-nr = <32>; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + i2c@12c60000 { #address-cells = <1>; #size-cells = <0>; @@ -190,6 +244,7 @@ compatible = "samsung,exynos4210-uart"; reg = <0x12C30000 0x100>; interrupts = <0 54 0>; + u-boot,dm-pre-reloc; id = <3>; }; diff --git a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi new file mode 100644 index 0000000..7edb0ca --- /dev/null +++ b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi @@ -0,0 +1,40 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + pinctrl_0: pinctrl@11400000 { + #address-cells = <1>; + #size-cells = <0>; + gpc4: gpc4 { + reg = <0x2e0>; + }; + gpx0: gpx0 { + reg = <0xc00>; + }; + }; + + pinctrl_1: pinctrl@13400000 { + #address-cells = <1>; + #size-cells = <0>; + }; + + pinctrl_2: pinctrl@10d10000 { + #address-cells = <1>; + #size-cells = <0>; + gpv2: gpv2 { + reg = <0x060>; + }; + gpv4: gpv4 { + reg = <0xc0>; + }; + }; + + pinctrl_3: pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos5250-pinctrl.dtsi b/arch/arm/dts/exynos5250-pinctrl.dtsi new file mode 100644 index 0000000..67755a1 --- /dev/null +++ b/arch/arm/dts/exynos5250-pinctrl.dtsi @@ -0,0 +1,331 @@ +/* + * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@11400000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, <24 0>, <25 0>, <25 1>, + <26 0>, <26 1>, <27 0>, <27 1>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, <28 1>, <29 0>, <29 1>, + <30 0>, <30 1>, <31 0>, <31 1>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl@13400000 { + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@10d10000 { + gpv0: gpv0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts index 9020382..8850409 100644 --- a/arch/arm/dts/exynos5250-smdk5250.dts +++ b/arch/arm/dts/exynos5250-smdk5250.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "exynos5250.dtsi" +#include "exynos5250.dtsi" / { model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index ab4f2f8..6fd9275 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "exynos5250.dtsi" +#include "exynos5250.dtsi" / { model = "Google Snow"; @@ -53,6 +53,14 @@ }; }; + spi@12d30000 { + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + compatible = "spi-flash"; + reg = <0>; + }; + }; + spi@131b0000 { spi-max-frequency = <1000000>; spi-deactivate-delay = <100>; diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index 0c644e7..ccbafe9 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -5,9 +5,48 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/include/ "exynos5.dtsi" +#include "exynos5.dtsi" +#include "exynos5250-pinctrl.dtsi" +#include "exynos5250-pinctrl-uboot.dtsi" / { + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 46 0>; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_1: pinctrl@13400000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; + }; + + pinctrl_2: pinctrl@10d10000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x10d10000 0x1000>; + interrupts = <0 50 0>; + }; + + pinctrl_3: pinctrl@03860000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 47 0>; + }; + i2c@12ca0000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 995e62b..fde863d 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "exynos54xx.dtsi" +#include "exynos54xx.dtsi" / { model = "Samsung/Google Peach Pit board based on Exynos5420"; @@ -140,6 +140,7 @@ spi@12d30000 { /* spi1 */ spi-max-frequency = <50000000>; firmware_storage_spi: flash@0 { + compatible = "spi-flash"; reg = <0>; /* diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts index 1bc6256..6855027 100644 --- a/arch/arm/dts/exynos5420-smdk5420.dts +++ b/arch/arm/dts/exynos5420-smdk5420.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "exynos54xx.dtsi" +#include "exynos54xx.dtsi" / { model = "SAMSUNG SMDK5420 board based on EXYNOS5420"; diff --git a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi new file mode 100644 index 0000000..5a86211 --- /dev/null +++ b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi @@ -0,0 +1,40 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + /* + * Replicate the ordering of arch/arm/include/asm/arch-exynos/gpio.h + * TODO(sjg@chromium.org): This ordering ceases to matter once GPIO + * numbers are not needed in U-Boot for exynos. + */ + pinctrl@14010000 { + #address-cells = <1>; + #size-cells = <0>; + }; + pinctrl@13400000 { + #address-cells = <1>; + #size-cells = <0>; + gpy7 { + }; + + gpx0 { + reg = <0xc00>; + }; + }; + pinctrl@13410000 { + #address-cells = <1>; + #size-cells = <0>; + }; + pinctrl@14000000 { + #address-cells = <1>; + #size-cells = <0>; + }; + pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos54xx-pinctrl.dtsi b/arch/arm/dts/exynos54xx-pinctrl.dtsi new file mode 100644 index 0000000..775d956 --- /dev/null +++ b/arch/arm/dts/exynos54xx-pinctrl.dtsi @@ -0,0 +1,305 @@ +/* + * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "exynos54xx-pinctrl-uboot.dtsi" + +/ { + pinctrl@13400000 { + gpy7: gpy7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, <24 0>, <25 0>, <25 1>, + <26 0>, <26 1>, <27 0>, <27 1>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, <28 1>, <29 0>, <29 1>, + <30 0>, <30 1>, <31 0>, <31 1>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@13410000 { + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + }; + + pinctrl@14000000 { + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@14010000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index c21d798..916cf3a 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -5,7 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/include/ "exynos5.dtsi" +#include "exynos5.dtsi" +#include "exynos54xx-pinctrl.dtsi" / { config { @@ -24,6 +25,11 @@ i2c8 = "/i2c@12e00000"; i2c9 = "/i2c@12e10000"; i2c10 = "/i2c@12e20000"; + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; spi0 = "/spi@12d20000"; spi1 = "/spi@12d30000"; spi2 = "/spi@12d40000"; @@ -123,6 +129,42 @@ reg = <0x14680000 0x100>; }; + pinctrl_0: pinctrl@13400000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_1: pinctrl@13410000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13410000 0x1000>; + interrupts = <0 78 0>; + }; + + pinctrl_2: pinctrl@14000000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14000000 0x1000>; + interrupts = <0 46 0>; + }; + + pinctrl_3: pinctrl@14010000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14010000 0x1000>; + interrupts = <0 50 0>; + }; + + pinctrl_4: pinctrl@03860000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 47 0>; + }; + fimd@14400000 { /* sysmmu is not used in U-Boot */ samsung,disable-sysmmu; diff --git a/arch/arm/dts/s5pc100-pinctrl.dtsi b/arch/arm/dts/s5pc100-pinctrl.dtsi new file mode 100644 index 0000000..bd9f97c --- /dev/null +++ b/arch/arm/dts/s5pc100-pinctrl.dtsi @@ -0,0 +1,180 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/ { + pinctrl@e0300000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc: gpc { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd: gpd { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpi: gpi { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj2: gpj2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj3: gpj3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl1: gpl1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl2: gpl2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl3: gpl3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl4: gpl4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph2: gph2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph3: gph3 { + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/s5pc110-pinctrl.dtsi b/arch/arm/dts/s5pc110-pinctrl.dtsi new file mode 100644 index 0000000..d21b6ab --- /dev/null +++ b/arch/arm/dts/s5pc110-pinctrl.dtsi @@ -0,0 +1,273 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/ { + pinctrl@e0200000 { + #address-cells = <1>; + #size-cells = <0>; + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpi: gpi { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj2: gpj2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj3: gpj3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp01: gpmp01 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp02: gpmp02 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp03: gpmp03 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp04: gpmp04 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp05: gpmp05 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp06: gpmp06 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp07: gpmp07 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp10: gpmp10 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp11: gpmp11 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp12: gpmp12 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp13: gpmp13 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp14: gpmp14 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp15: gpmp15 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp16: gpmp16 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp17: gpmp17 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp18: gpmp18 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp20: gpmp20 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp21: gpmp21 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp22: gpmp22 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp23: gpmp23 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp24: gpmp24 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp25: gpmp25 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp26: gpmp26 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp27: gpmp27 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp28: gpmp28 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph0: gph0 { + reg = <0xc00>; + gpio-controller; + #gpio-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph2: gph2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph3: gph3 { + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts index 2e671bb..7bbfe59 100644 --- a/arch/arm/dts/s5pc1xx-goni.dts +++ b/arch/arm/dts/s5pc1xx-goni.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "skeleton.dtsi" +#include "s5pc110-pinctrl.dtsi" / { model = "Samsung Goni based on S5PC110"; @@ -17,6 +18,12 @@ aliases { serial2 = "/serial@e2900800"; console = "/serial@e2900800"; + pinctrl0 = &pinctrl0; + }; + + pinctrl0: pinctrl@e0200000 { + compatible = "samsung,s5pc110-pinctrl"; + reg = <0xe0200000 0x1000>; }; serial@e2900800 { diff --git a/arch/arm/dts/s5pc1xx-smdkc100.dts b/arch/arm/dts/s5pc1xx-smdkc100.dts index 42754ce..95f15ed 100644 --- a/arch/arm/dts/s5pc1xx-smdkc100.dts +++ b/arch/arm/dts/s5pc1xx-smdkc100.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "skeleton.dtsi" +#include "s5pc100-pinctrl.dtsi" / { model = "Samsung SMDKC100 based on S5PC100"; @@ -17,6 +18,12 @@ aliases { serial0 = "/serial@ec000000"; console = "/serial@ec000000"; + pinctrl0 = &pinctrl0; + }; + + pinctrl0: pinctrl@e0300000 { + compatible = "samsung,s5pc100-pinctrl"; + reg = <0xe0200000 0x1000>; }; serial@ec000000 { diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index cee5cfe..74e8a16 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -15,6 +15,7 @@ usb1 = "/usb@c5000000"; sdhci0 = "/sdhci@c8000600"; sdhci1 = "/sdhci@c8000000"; + spi0 = "/spi@7000c380"; }; memory { diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index ad140de..9acd84d 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -18,6 +18,7 @@ i2c4 = "/i2c@7000c700"; sdhci0 = "/sdhci@78000600"; sdhci1 = "/sdhci@78000000"; + spi0 = "/spi@7000da00"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d008000"; }; diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts index b4fbe71..1b8ed73 100644 --- a/arch/arm/dts/tegra30-cardhu.dts +++ b/arch/arm/dts/tegra30-cardhu.dts @@ -18,6 +18,7 @@ i2c4 = "/i2c@7000c700"; sdhci0 = "/sdhci@78000600"; sdhci1 = "/sdhci@78000000"; + spi0 = "/spi@7000da00"; usb0 = "/usb@7d008000"; }; diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts index dd6009a..572520a 100644 --- a/arch/arm/dts/tegra30-colibri.dts +++ b/arch/arm/dts/tegra30-colibri.dts @@ -16,6 +16,7 @@ i2c2 = "/i2c@7000c700"; sdhci0 = "/sdhci@78000600"; sdhci1 = "/sdhci@78000200"; + spi0 = "/spi@7000d400"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d004000"; /* on module only, for ASIX */ usb2 = "/usb@7d008000"; diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c index a580873..34f5387 100644 --- a/arch/arm/imx-common/i2c-mxv7.c +++ b/arch/arm/imx-common/i2c-mxv7.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <malloc.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/errno.h> @@ -69,15 +70,53 @@ static void * const i2c_bases[] = { }; /* i2c_index can be from 0 - 2 */ -void setup_i2c(unsigned i2c_index, int speed, int slave_addr, - struct i2c_pads_info *p) +int setup_i2c(unsigned i2c_index, int speed, int slave_addr, + struct i2c_pads_info *p) { + char *name1, *name2; + int ret; + if (i2c_index >= ARRAY_SIZE(i2c_bases)) - return; + return -EINVAL; + + name1 = malloc(9); + name2 = malloc(9); + if (!name1 || !name2) + return -ENOMEM; + + sprintf(name1, "i2c_sda%d", i2c_index); + sprintf(name2, "i2c_scl%d", i2c_index); + ret = gpio_request(p->sda.gp, name1); + if (ret) + goto err_req1; + + ret = gpio_request(p->scl.gp, name2); + if (ret) + goto err_req2; + /* Enable i2c clock */ - enable_i2c_clk(1, i2c_index); + ret = enable_i2c_clk(1, i2c_index); + if (ret) + goto err_clk; + /* Make sure bus is idle */ - force_idle_bus(p); + ret = force_idle_bus(p); + if (ret) + goto err_idle; + bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr, force_idle_bus, p); + + return 0; + +err_idle: +err_clk: + gpio_free(p->scl.gp); +err_req2: + gpio_free(p->sda.gp); +err_req1: + free(name1); + free(name2); + + return ret; } diff --git a/arch/arm/include/asm/arch-armada-xp/config.h b/arch/arm/include/asm/arch-armada-xp/config.h new file mode 100644 index 0000000..00ee775 --- /dev/null +++ b/arch/arm/include/asm/arch-armada-xp/config.h @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen <leiwen@marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file should be included in board config header file. + * + * It supports common definitions for Armada XP platforms + */ + +#ifndef _ARMADA_XP_CONFIG_H +#define _ARMADA_XP_CONFIG_H + +#include <asm/arch/soc.h> + +#define MV88F78X60 /* for the DDR training bin_hdr code */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * By default kwbimage.cfg from board specific folder is used + * If for some board, different configuration file need to be used, + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file + */ +#ifndef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg +#endif /* CONFIG_SYS_KWD_CONFIG */ + +/* Add target to build it automatically upon "make" */ +#define CONFIG_BUILD_TARGET "u-boot.kwb" + +/* end of 16M scrubbed by training in bootrom */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000 +#define CONFIG_NR_DRAM_BANKS_MAX 2 + +#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE + +/* + * SPI Flash configuration + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_HARD_SPI 1 +#define CONFIG_KIRKWOOD_SPI 1 +#ifndef CONFIG_ENV_SPI_BUS +# define CONFIG_ENV_SPI_BUS 0 +#endif +#ifndef CONFIG_ENV_SPI_CS +# define CONFIG_ENV_SPI_CS 0 +#endif +#ifndef CONFIG_ENV_SPI_MAX_HZ +# define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif +#endif + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ +#define CONFIG_PHYLIB +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ +#endif /* CONFIG_CMD_NET */ + +/* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#ifndef CONFIG_SYS_I2C_SOFT +#define CONFIG_I2C_MVTWSI +#endif +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#endif /* _ARMADA_XP_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-armada-xp/cpu.h b/arch/arm/include/asm/arch-armada-xp/cpu.h new file mode 100644 index 0000000..6b60c21 --- /dev/null +++ b/arch/arm/include/asm/arch-armada-xp/cpu.h @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ARMADA_XP_CPU_H +#define _ARMADA_XP_CPU_H + +#include <asm/system.h> + +#ifndef __ASSEMBLY__ + +#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) +#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) + +enum memory_bank { + BANK0, + BANK1, + BANK2, + BANK3 +}; + +enum cpu_winen { + CPU_WIN_DISABLE, + CPU_WIN_ENABLE +}; + +enum cpu_target { + CPU_TARGET_DRAM = 0x0, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1, + CPU_TARGET_ETH23 = 0x3, + CPU_TARGET_PCIE02 = 0x4, + CPU_TARGET_ETH01 = 0x7, + CPU_TARGET_PCIE13 = 0x8, + CPU_TARGET_SASRAM = 0x9, + CPU_TARGET_NAND = 0xd, +}; + +enum cpu_attrib { + CPU_ATTR_SASRAM = 0x01, + CPU_ATTR_DRAM_CS0 = 0x0e, + CPU_ATTR_DRAM_CS1 = 0x0d, + CPU_ATTR_DRAM_CS2 = 0x0b, + CPU_ATTR_DRAM_CS3 = 0x07, + CPU_ATTR_NANDFLASH = 0x2f, + CPU_ATTR_SPIFLASH = 0x1e, + CPU_ATTR_BOOTROM = 0x1d, + CPU_ATTR_PCIE_IO = 0xe0, + CPU_ATTR_PCIE_MEM = 0xe8, + CPU_ATTR_DEV_CS0 = 0x3e, + CPU_ATTR_DEV_CS1 = 0x3d, + CPU_ATTR_DEV_CS2 = 0x3b, + CPU_ATTR_DEV_CS3 = 0x37, +}; + +/* + * Default Device Address MAP BAR values + */ +#define DEFADR_PCI_MEM 0x90000000 +#define DEFADR_PCI_IO 0xC0000000 +#define DEFADR_SPIF 0xF4000000 +#define DEFADR_BOOTROM 0xF8000000 + +struct mbus_win { + u32 base; + u32 size; + u8 target; + u8 attr; +}; + +/* + * System registers + * Ref: Datasheet sec:A.28 + */ +struct mvebu_system_registers { + u8 pad1[0x60]; + u32 rstoutn_mask; /* 0x60 */ + u32 sys_soft_rst; /* 0x64 */ +}; + +/* + * GPIO Registers + * Ref: Datasheet sec:A.19 + */ +struct kwgpio_registers { + u32 dout; + u32 oe; + u32 blink_en; + u32 din_pol; + u32 din; + u32 irq_cause; + u32 irq_mask; + u32 irq_level; +}; + +/* + * functions + */ +unsigned int mvebu_sdram_bar(enum memory_bank bank); +unsigned int mvebu_sdram_bs(enum memory_bank bank); +void mvebu_sdram_size_adjust(enum memory_bank bank); +int mvebu_mbus_probe(struct mbus_win windows[], int count); +#endif /* __ASSEMBLY__ */ +#endif /* _ARMADA_XP_CPU_H */ diff --git a/arch/arm/include/asm/arch-armada-xp/soc.h b/arch/arm/include/asm/arch-armada-xp/soc.h new file mode 100644 index 0000000..963e7ac --- /dev/null +++ b/arch/arm/include/asm/arch-armada-xp/soc.h @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * Header file for the Marvell's Feroceon CPU core. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_ARMADA_XP_H +#define _ASM_ARCH_ARMADA_XP_H + +#define SOC_MV78460_ID 0x7846 + +/* TCLK Core Clock definition */ +#ifndef CONFIG_SYS_TCLK +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#endif + +/* SOC specific definations */ +#define INTREG_BASE 0xd0000000 +#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) +#define SOC_REGS_PHY_BASE 0xf1000000 +#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x) + +#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) +#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600)) +#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) +#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000)) +#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100)) +#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) +#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) +#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) +#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180)) +#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200)) +#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) +#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) +#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) +#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000)) +#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000)) +#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) +#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) +#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) + +#define SDRAM_MAX_CS 4 +#define SDRAM_ADDR_MASK 0xFF000000 + +/* Armada XP GbE controller has 4 ports */ +#define MAX_MVNETA_DEVS 4 + +/* Kirkwood CPU memory windows */ +#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA +#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE +#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE + +#endif /* _ASM_ARCH_ARMADA_XP_H */ diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/include/asm/arch-bcm2835/gpio.h index 9a49b6e..db42896 100644 --- a/arch/arm/include/asm/arch-bcm2835/gpio.h +++ b/arch/arm/include/asm/arch-bcm2835/gpio.h @@ -52,4 +52,13 @@ struct bcm2835_gpio_regs { u32 gppudclk[2]; }; +/** + * struct bcm2835_gpio_platdata - GPIO platform description + * + * @base: Base address of GPIO controller + */ +struct bcm2835_gpio_platdata { + unsigned long base; +}; + #endif /* _BCM2835_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 8fb5c23..ad2ece6 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -284,7 +284,7 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_Y65, EXYNOS4_GPIO_Y66, EXYNOS4_GPIO_Y67, - EXYNOS4_GPIO_X00 = 896, /* 896 0x380 */ + EXYNOS4_GPIO_X00, /* 256 0x100 */ EXYNOS4_GPIO_X01, EXYNOS4_GPIO_X02, EXYNOS4_GPIO_X03, @@ -292,7 +292,7 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X05, EXYNOS4_GPIO_X06, EXYNOS4_GPIO_X07, - EXYNOS4_GPIO_X10, /* 904 0x388 */ + EXYNOS4_GPIO_X10, /* 264 0x108 */ EXYNOS4_GPIO_X11, EXYNOS4_GPIO_X12, EXYNOS4_GPIO_X13, @@ -300,7 +300,7 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X15, EXYNOS4_GPIO_X16, EXYNOS4_GPIO_X17, - EXYNOS4_GPIO_X20, /* 912 0x390 */ + EXYNOS4_GPIO_X20, /* 272 0x110 */ EXYNOS4_GPIO_X21, EXYNOS4_GPIO_X22, EXYNOS4_GPIO_X23, @@ -308,7 +308,7 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X25, EXYNOS4_GPIO_X26, EXYNOS4_GPIO_X27, - EXYNOS4_GPIO_X30, /* 920 0x398 */ + EXYNOS4_GPIO_X30, /* 280 0x118 */ EXYNOS4_GPIO_X31, EXYNOS4_GPIO_X32, EXYNOS4_GPIO_X33, @@ -318,7 +318,7 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X37, /* GPIO_PART3_STARTS */ - EXYNOS4_GPIO_MAX_PORT_PART_2, /* 928 0x3A0 */ + EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */ EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2, EXYNOS4_GPIO_Z1, EXYNOS4_GPIO_Z2, @@ -389,7 +389,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_D15, EXYNOS4X12_GPIO_D16, EXYNOS4X12_GPIO_D17, - EXYNOS4X12_GPIO_F00 = 96, /* 96 0x60 */ + EXYNOS4X12_GPIO_F00, /* 56 0x38 */ EXYNOS4X12_GPIO_F01, EXYNOS4X12_GPIO_F02, EXYNOS4X12_GPIO_F03, @@ -397,7 +397,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F05, EXYNOS4X12_GPIO_F06, EXYNOS4X12_GPIO_F07, - EXYNOS4X12_GPIO_F10, /* 104 0x68 */ + EXYNOS4X12_GPIO_F10, /* 64 0x40 */ EXYNOS4X12_GPIO_F11, EXYNOS4X12_GPIO_F12, EXYNOS4X12_GPIO_F13, @@ -405,7 +405,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F15, EXYNOS4X12_GPIO_F16, EXYNOS4X12_GPIO_F17, - EXYNOS4X12_GPIO_F20, /* 112 0x70 */ + EXYNOS4X12_GPIO_F20, /* 72 0x48 */ EXYNOS4X12_GPIO_F21, EXYNOS4X12_GPIO_F22, EXYNOS4X12_GPIO_F23, @@ -413,7 +413,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F25, EXYNOS4X12_GPIO_F26, EXYNOS4X12_GPIO_F27, - EXYNOS4X12_GPIO_F30, /* 120 0x78 */ + EXYNOS4X12_GPIO_F30, /* 80 0x50 */ EXYNOS4X12_GPIO_F31, EXYNOS4X12_GPIO_F32, EXYNOS4X12_GPIO_F33, @@ -421,7 +421,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F35, EXYNOS4X12_GPIO_F36, EXYNOS4X12_GPIO_F37, - EXYNOS4X12_GPIO_J00 = 144, /* 144 0x90 */ + EXYNOS4X12_GPIO_J00, /* 88 0x58 */ EXYNOS4X12_GPIO_J01, EXYNOS4X12_GPIO_J02, EXYNOS4X12_GPIO_J03, @@ -429,7 +429,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_J05, EXYNOS4X12_GPIO_J06, EXYNOS4X12_GPIO_J07, - EXYNOS4X12_GPIO_J10, /* 152 0x98 */ + EXYNOS4X12_GPIO_J10, /* 96 0x60 */ EXYNOS4X12_GPIO_J11, EXYNOS4X12_GPIO_J12, EXYNOS4X12_GPIO_J13, @@ -439,8 +439,8 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_J17, /* GPIO_PART2_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 160 0xA0 */ - EXYNOS4X12_GPIO_K00 = 176, /* 176 0xB0 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */ + EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1, EXYNOS4X12_GPIO_K01, EXYNOS4X12_GPIO_K02, EXYNOS4X12_GPIO_K03, @@ -448,7 +448,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_K05, EXYNOS4X12_GPIO_K06, EXYNOS4X12_GPIO_K07, - EXYNOS4X12_GPIO_K10, /* 184 0xB8 */ + EXYNOS4X12_GPIO_K10, /* 112 0x70 */ EXYNOS4X12_GPIO_K11, EXYNOS4X12_GPIO_K12, EXYNOS4X12_GPIO_K13, @@ -456,7 +456,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_K15, EXYNOS4X12_GPIO_K16, EXYNOS4X12_GPIO_K17, - EXYNOS4X12_GPIO_K20, /* 192 0xC0 */ + EXYNOS4X12_GPIO_K20, /* 120 0x78 */ EXYNOS4X12_GPIO_K21, EXYNOS4X12_GPIO_K22, EXYNOS4X12_GPIO_K23, @@ -464,7 +464,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_K25, EXYNOS4X12_GPIO_K26, EXYNOS4X12_GPIO_K27, - EXYNOS4X12_GPIO_K30, /* 200 0xC8 */ + EXYNOS4X12_GPIO_K30, /* 128 0x80 */ EXYNOS4X12_GPIO_K31, EXYNOS4X12_GPIO_K32, EXYNOS4X12_GPIO_K33, @@ -472,7 +472,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_K35, EXYNOS4X12_GPIO_K36, EXYNOS4X12_GPIO_K37, - EXYNOS4X12_GPIO_L00, /* 208 0xD0 */ + EXYNOS4X12_GPIO_L00, /* 136 0x88 */ EXYNOS4X12_GPIO_L01, EXYNOS4X12_GPIO_L02, EXYNOS4X12_GPIO_L03, @@ -480,7 +480,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_L05, EXYNOS4X12_GPIO_L06, EXYNOS4X12_GPIO_L07, - EXYNOS4X12_GPIO_L10, /* 216 0xD8 */ + EXYNOS4X12_GPIO_L10, /* 144 0x90 */ EXYNOS4X12_GPIO_L11, EXYNOS4X12_GPIO_L12, EXYNOS4X12_GPIO_L13, @@ -488,7 +488,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_L15, EXYNOS4X12_GPIO_L16, EXYNOS4X12_GPIO_L17, - EXYNOS4X12_GPIO_L20, /* 224 0xE0 */ + EXYNOS4X12_GPIO_L20, /* 152 0x98 */ EXYNOS4X12_GPIO_L21, EXYNOS4X12_GPIO_L22, EXYNOS4X12_GPIO_L23, @@ -496,7 +496,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_L25, EXYNOS4X12_GPIO_L26, EXYNOS4X12_GPIO_L27, - EXYNOS4X12_GPIO_Y00, /* 232 0xE8 */ + EXYNOS4X12_GPIO_Y00, /* 160 0xa0 */ EXYNOS4X12_GPIO_Y01, EXYNOS4X12_GPIO_Y02, EXYNOS4X12_GPIO_Y03, @@ -504,7 +504,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y05, EXYNOS4X12_GPIO_Y06, EXYNOS4X12_GPIO_Y07, - EXYNOS4X12_GPIO_Y10, /* 240 0xF0 */ + EXYNOS4X12_GPIO_Y10, /* 168 0xa8 */ EXYNOS4X12_GPIO_Y11, EXYNOS4X12_GPIO_Y12, EXYNOS4X12_GPIO_Y13, @@ -512,7 +512,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y15, EXYNOS4X12_GPIO_Y16, EXYNOS4X12_GPIO_Y17, - EXYNOS4X12_GPIO_Y20, /* 248 0xF8 */ + EXYNOS4X12_GPIO_Y20, /* 176 0xb0 */ EXYNOS4X12_GPIO_Y21, EXYNOS4X12_GPIO_Y22, EXYNOS4X12_GPIO_Y23, @@ -520,7 +520,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y25, EXYNOS4X12_GPIO_Y26, EXYNOS4X12_GPIO_Y27, - EXYNOS4X12_GPIO_Y30, /* 256 0x100 */ + EXYNOS4X12_GPIO_Y30, /* 184 0xb8 */ EXYNOS4X12_GPIO_Y31, EXYNOS4X12_GPIO_Y32, EXYNOS4X12_GPIO_Y33, @@ -528,7 +528,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y35, EXYNOS4X12_GPIO_Y36, EXYNOS4X12_GPIO_Y37, - EXYNOS4X12_GPIO_Y40, /* 264 0x108 */ + EXYNOS4X12_GPIO_Y40, /* 192 0xc0 */ EXYNOS4X12_GPIO_Y41, EXYNOS4X12_GPIO_Y42, EXYNOS4X12_GPIO_Y43, @@ -536,7 +536,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y45, EXYNOS4X12_GPIO_Y46, EXYNOS4X12_GPIO_Y47, - EXYNOS4X12_GPIO_Y50, /* 272 0x110 */ + EXYNOS4X12_GPIO_Y50, /* 200 0xc8 */ EXYNOS4X12_GPIO_Y51, EXYNOS4X12_GPIO_Y52, EXYNOS4X12_GPIO_Y53, @@ -544,7 +544,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y55, EXYNOS4X12_GPIO_Y56, EXYNOS4X12_GPIO_Y57, - EXYNOS4X12_GPIO_Y60, /* 280 0x118 */ + EXYNOS4X12_GPIO_Y60, /* 208 0xd0 */ EXYNOS4X12_GPIO_Y61, EXYNOS4X12_GPIO_Y62, EXYNOS4X12_GPIO_Y63, @@ -552,7 +552,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y65, EXYNOS4X12_GPIO_Y66, EXYNOS4X12_GPIO_Y67, - EXYNOS4X12_GPIO_M00 = 312, /* 312 0xF0 */ + EXYNOS4X12_GPIO_M00, /* 216 0xd8 */ EXYNOS4X12_GPIO_M01, EXYNOS4X12_GPIO_M02, EXYNOS4X12_GPIO_M03, @@ -560,7 +560,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M05, EXYNOS4X12_GPIO_M06, EXYNOS4X12_GPIO_M07, - EXYNOS4X12_GPIO_M10, /* 320 0xF8 */ + EXYNOS4X12_GPIO_M10, /* 224 0xe0 */ EXYNOS4X12_GPIO_M11, EXYNOS4X12_GPIO_M12, EXYNOS4X12_GPIO_M13, @@ -568,7 +568,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M15, EXYNOS4X12_GPIO_M16, EXYNOS4X12_GPIO_M17, - EXYNOS4X12_GPIO_M20, /* 328 0x100 */ + EXYNOS4X12_GPIO_M20, /* 232 0xe8 */ EXYNOS4X12_GPIO_M21, EXYNOS4X12_GPIO_M22, EXYNOS4X12_GPIO_M23, @@ -576,7 +576,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M25, EXYNOS4X12_GPIO_M26, EXYNOS4X12_GPIO_M27, - EXYNOS4X12_GPIO_M30, /* 336 0x108 */ + EXYNOS4X12_GPIO_M30, /* 240 0xf0 */ EXYNOS4X12_GPIO_M31, EXYNOS4X12_GPIO_M32, EXYNOS4X12_GPIO_M33, @@ -584,7 +584,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M35, EXYNOS4X12_GPIO_M36, EXYNOS4X12_GPIO_M37, - EXYNOS4X12_GPIO_M40, /* 344 0x110 */ + EXYNOS4X12_GPIO_M40, /* 248 0xf8 */ EXYNOS4X12_GPIO_M41, EXYNOS4X12_GPIO_M42, EXYNOS4X12_GPIO_M43, @@ -592,7 +592,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M45, EXYNOS4X12_GPIO_M46, EXYNOS4X12_GPIO_M47, - EXYNOS4X12_GPIO_X00 = 928, /* 928 0x3A0 */ + EXYNOS4X12_GPIO_X00, /* 256 0x100 */ EXYNOS4X12_GPIO_X01, EXYNOS4X12_GPIO_X02, EXYNOS4X12_GPIO_X03, @@ -600,7 +600,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X05, EXYNOS4X12_GPIO_X06, EXYNOS4X12_GPIO_X07, - EXYNOS4X12_GPIO_X10, /* 936 0x3A8 */ + EXYNOS4X12_GPIO_X10, /* 264 0x108 */ EXYNOS4X12_GPIO_X11, EXYNOS4X12_GPIO_X12, EXYNOS4X12_GPIO_X13, @@ -608,7 +608,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X15, EXYNOS4X12_GPIO_X16, EXYNOS4X12_GPIO_X17, - EXYNOS4X12_GPIO_X20, /* 944 0x3B0 */ + EXYNOS4X12_GPIO_X20, /* 272 0x110 */ EXYNOS4X12_GPIO_X21, EXYNOS4X12_GPIO_X22, EXYNOS4X12_GPIO_X23, @@ -616,7 +616,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X25, EXYNOS4X12_GPIO_X26, EXYNOS4X12_GPIO_X27, - EXYNOS4X12_GPIO_X30, /* 952 0x3B8 */ + EXYNOS4X12_GPIO_X30, /* 280 0x118 */ EXYNOS4X12_GPIO_X31, EXYNOS4X12_GPIO_X32, EXYNOS4X12_GPIO_X33, @@ -626,7 +626,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X37, /* GPIO_PART3_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 960 0x3C0 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */ EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2, EXYNOS4X12_GPIO_Z1, EXYNOS4X12_GPIO_Z2, @@ -637,7 +637,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Z7, /* GPIO_PART4_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 968 0x3C8 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */ EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, EXYNOS4X12_GPIO_V01, EXYNOS4X12_GPIO_V02, @@ -646,7 +646,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_V05, EXYNOS4X12_GPIO_V06, EXYNOS4X12_GPIO_V07, - EXYNOS4X12_GPIO_V10, /* 976 0x3D0 */ + EXYNOS4X12_GPIO_V10, /* 304 0x130 */ EXYNOS4X12_GPIO_V11, EXYNOS4X12_GPIO_V12, EXYNOS4X12_GPIO_V13, @@ -654,7 +654,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_V15, EXYNOS4X12_GPIO_V16, EXYNOS4X12_GPIO_V17, - EXYNOS4X12_GPIO_V20 = 992, /* 992 0x3E0 */ + EXYNOS4X12_GPIO_V20, /* 312 0x138 */ EXYNOS4X12_GPIO_V21, EXYNOS4X12_GPIO_V22, EXYNOS4X12_GPIO_V23, @@ -662,7 +662,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_V25, EXYNOS4X12_GPIO_V26, EXYNOS4X12_GPIO_V27, - EXYNOS4X12_GPIO_V30 = 1000, /* 1000 0x3E8 */ + EXYNOS4X12_GPIO_V30, /* 320 0x140 */ EXYNOS4X12_GPIO_V31, EXYNOS4X12_GPIO_V32, EXYNOS4X12_GPIO_V33, @@ -670,7 +670,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_V35, EXYNOS4X12_GPIO_V36, EXYNOS4X12_GPIO_V37, - EXYNOS4X12_GPIO_V40 = 1016, /* 1016 0x3F8 */ + EXYNOS4X12_GPIO_V40, /* 328 0x148 */ EXYNOS4X12_GPIO_V41, EXYNOS4X12_GPIO_V42, EXYNOS4X12_GPIO_V43, @@ -1504,12 +1504,7 @@ static const struct gpio_name_num_table exynos5420_gpio_table[] = { void gpio_cfg_pin(int gpio, int cfg); void gpio_set_pull(int gpio, int mode); void gpio_set_drv(int gpio, int mode); -int gpio_direction_input(unsigned gpio); -int gpio_direction_output(unsigned gpio, int value); -int gpio_set_value(unsigned gpio, int value); -int gpio_get_value(unsigned gpio); void gpio_set_rate(int gpio, int mode); -struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio); int s5p_gpio_get_pin(unsigned gpio); #endif diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index f7bfa0e..ccc8e4e 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -23,7 +23,7 @@ #error "SOC Name not defined" #endif /* CONFIG_KW88F6281 */ -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_SYS_CACHELINE_SIZE 32 /* default Dcache Line length for kirkwood */ diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index 97daa40..926d347 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -140,11 +140,11 @@ struct kwgpio_registers { * functions */ unsigned char get_random_hex(void); -unsigned int kw_sdram_bar(enum memory_bank bank); -unsigned int kw_sdram_bs(enum memory_bank bank); -void kw_sdram_size_adjust(enum memory_bank bank); +unsigned int mvebu_sdram_bar(enum memory_bank bank); +unsigned int mvebu_sdram_bs(enum memory_bank bank); +void mvebu_sdram_size_adjust(enum memory_bank bank); int kw_config_adr_windows(void); -void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, +void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, unsigned int mpp16_23, unsigned int mpp24_31, diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h index 5f4d786..aa8c5da 100644 --- a/arch/arm/include/asm/arch-kirkwood/gpio.h +++ b/arch/arm/include/asm/arch-kirkwood/gpio.h @@ -21,14 +21,14 @@ #define GPIO_MAX 50 #define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) -#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00) -#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04) -#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08) -#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) -#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10) -#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14) -#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18) -#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) +#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) +#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) +#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) +#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) +#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) +#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) +#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) +#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) /* * Kirkwood-specific GPIO API diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/soc.h index 3ea51d7..58ed71b 100644 --- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h +++ b/arch/arm/include/asm/arch-kirkwood/soc.h @@ -22,18 +22,19 @@ #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) +#define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500)) #define KW_TWSI_BASE (KW_REGISTER(0x11000)) #define KW_UART0_BASE (KW_REGISTER(0x12000)) #define KW_UART1_BASE (KW_REGISTER(0x12100)) #define KW_MPP_BASE (KW_REGISTER(0x10000)) -#define KW_GPIO0_BASE (KW_REGISTER(0x10100)) -#define KW_GPIO1_BASE (KW_REGISTER(0x10140)) +#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100)) +#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140)) #define KW_RTC_BASE (KW_REGISTER(0x10300)) #define KW_NANDF_BASE (KW_REGISTER(0x10418)) -#define KW_SPI_BASE (KW_REGISTER(0x10600)) +#define MVEBU_SPI_BASE (KW_REGISTER(0x10600)) #define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) #define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) -#define KW_TIMER_BASE (KW_REGISTER(0x20300)) +#define MVEBU_TIMER_BASE (KW_REGISTER(0x20300)) #define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) #define KW_USB20_BASE (KW_REGISTER(0x50000)) #define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a500b5b..f2c9687 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -19,6 +19,8 @@ #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) @@ -66,6 +68,7 @@ #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE +#define CONFIG_SYS_FSL_SEC_LE #define DCU_LAYER_MAX_NUM 16 @@ -76,6 +79,7 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h index e512dce..e512dce 100644 --- a/arch/arm/include/asm/arch-kirkwood/spi.h +++ b/arch/arm/include/asm/arch-mvebu/spi.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index d5dbc22..2de205e 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -682,8 +682,7 @@ enum s5pc110_gpio_pin { S5PC110_GPIO_MP285, S5PC110_GPIO_MP286, S5PC110_GPIO_MP287, - S5PC110_GPIO_RES, - S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)), + S5PC110_GPIO_H00, S5PC110_GPIO_H01, S5PC110_GPIO_H02, S5PC110_GPIO_H03, @@ -815,11 +814,7 @@ static const struct gpio_name_num_table s5pc110_gpio_table[] = { void gpio_cfg_pin(int gpio, int cfg); void gpio_set_pull(int gpio, int mode); void gpio_set_drv(int gpio, int mode); -int gpio_direction_output(unsigned gpio, int value); -int gpio_set_value(unsigned gpio, int value); -int gpio_get_value(unsigned gpio); void gpio_set_rate(int gpio, int mode); -struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio); int s5p_gpio_get_pin(unsigned gpio); /* GPIO pins per bank */ diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h deleted file mode 100644 index 48197bc..0000000 --- a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra SPI controller - * - * Copyright 2010-2013 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA114_SPI_H_ -#define _TEGRA114_SPI_H_ - -#include <asm/types.h> - -int tegra114_spi_init(int *node_list, int count); -int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra114_spi_free_slave(struct spi_slave *slave); -int tegra114_spi_claim_bus(struct spi_slave *slave); -void tegra114_spi_cs_activate(struct spi_slave *slave); -void tegra114_spi_cs_deactivate(struct spi_slave *slave); -int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA114_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h deleted file mode 100644 index e8cc68c..0000000 --- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra20 SPI-FLASH controller - * - * Copyright 2010-2012 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA20_SPI_H_ -#define _TEGRA20_SPI_H_ - -#include <asm/types.h> - -int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra20_spi_free_slave(struct spi_slave *slave); -int tegra20_spi_init(int *node_list, int count); -int tegra20_spi_claim_bus(struct spi_slave *slave); -void tegra20_spi_cs_activate(struct spi_slave *slave); -void tegra20_spi_cs_deactivate(struct spi_slave *slave); -int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA20_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h deleted file mode 100644 index 5aa74dd..0000000 --- a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra SPI-SLINK controller - * - * Copyright 2010-2013 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA30_SPI_H_ -#define _TEGRA30_SPI_H_ - -#include <asm/types.h> - -int tegra30_spi_init(int *node_list, int count); -int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra30_spi_free_slave(struct spi_slave *slave); -int tegra30_spi_claim_bus(struct spi_slave *slave); -void tegra30_spi_cs_activate(struct spi_slave *slave); -void tegra30_spi_cs_deactivate(struct spi_slave *slave); -int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA30_SPI_H_ */ diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h index 182c2f3..af86163 100644 --- a/arch/arm/include/asm/imx-common/mxc_i2c.h +++ b/arch/arm/include/asm/imx-common/mxc_i2c.h @@ -52,8 +52,8 @@ struct i2c_pads_info { &mx6q_##name : &mx6s_##name #endif -void setup_i2c(unsigned i2c_index, int speed, int slave_addr, - struct i2c_pads_info *p); +int setup_i2c(unsigned i2c_index, int speed, int slave_addr, + struct i2c_pads_info *p); void bus_i2c_init(void *base, int speed, int slave_addr, int (*idle_bus_fn)(void *p), void *p); int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile new file mode 100644 index 0000000..9dcab69 --- /dev/null +++ b/arch/arm/mvebu-common/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = dram.o +obj-y += gpio.o +obj-$(CONFIG_ARMADA_XP) += mbus.o +obj-y += timer.o diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/mvebu-common/dram.c index d73ae47..db18791 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ b/arch/arm/mvebu-common/dram.c @@ -10,31 +10,31 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> DECLARE_GLOBAL_DATA_PTR; -struct kw_sdram_bank { +struct sdram_bank { u32 win_bar; u32 win_sz; }; -struct kw_sdram_addr_dec { - struct kw_sdram_bank sdram_bank[4]; +struct sdram_addr_dec { + struct sdram_bank sdram_bank[4]; }; -#define KW_REG_CPUCS_WIN_ENABLE (1 << 0) -#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1) -#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2) -#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24) +#define REG_CPUCS_WIN_ENABLE (1 << 0) +#define REG_CPUCS_WIN_WR_PROTECT (1 << 1) +#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2) +#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24) /* - * kw_sdram_bar - reads SDRAM Base Address Register + * mvebu_sdram_bar - reads SDRAM Base Address Register */ -u32 kw_sdram_bar(enum memory_bank bank) +u32 mvebu_sdram_bar(enum memory_bank bank) { - struct kw_sdram_addr_dec *base = - (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); + struct sdram_addr_dec *base = + (struct sdram_addr_dec *)MVEBU_SDRAM_BASE; u32 result = 0; u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); @@ -46,31 +46,31 @@ u32 kw_sdram_bar(enum memory_bank bank) } /* - * kw_sdram_bs_set - writes SDRAM Bank size + * mvebu_sdram_bs_set - writes SDRAM Bank size */ -static void kw_sdram_bs_set(enum memory_bank bank, u32 size) +static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size) { - struct kw_sdram_addr_dec *base = - (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); + struct sdram_addr_dec *base = + (struct sdram_addr_dec *)MVEBU_SDRAM_BASE; /* Read current register value */ u32 reg = readl(&base->sdram_bank[bank].win_sz); /* Clear window size */ - reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF); + reg &= ~REG_CPUCS_WIN_SIZE(0xFF); /* Set new window size */ - reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24); + reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24); writel(reg, &base->sdram_bank[bank].win_sz); } /* - * kw_sdram_bs - reads SDRAM Bank size + * mvebu_sdram_bs - reads SDRAM Bank size */ -u32 kw_sdram_bs(enum memory_bank bank) +u32 mvebu_sdram_bs(enum memory_bank bank) { - struct kw_sdram_addr_dec *base = - (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); + struct sdram_addr_dec *base = + (struct sdram_addr_dec *)MVEBU_SDRAM_BASE; u32 result = 0; u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); @@ -81,15 +81,16 @@ u32 kw_sdram_bs(enum memory_bank bank) return result; } -void kw_sdram_size_adjust(enum memory_bank bank) +void mvebu_sdram_size_adjust(enum memory_bank bank) { u32 size; /* probe currently equipped RAM size */ - size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank)); + size = get_ram_size((void *)mvebu_sdram_bar(bank), + mvebu_sdram_bs(bank)); /* adjust SDRAM window size accordingly */ - kw_sdram_bs_set(bank, size); + mvebu_sdram_bs_set(bank, size); } #ifndef CONFIG_SYS_BOARD_DRAM_INIT @@ -99,8 +100,8 @@ int dram_init(void) gd->ram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); + gd->bd->bi_dram[i].start = mvebu_sdram_bar(i); + gd->bd->bi_dram[i].size = mvebu_sdram_bs(i); /* * It is assumed that all memory banks are consecutive * and without gaps. @@ -110,7 +111,13 @@ int dram_init(void) if (gd->bd->bi_dram[i].start != gd->ram_size) break; - gd->ram_size += gd->bd->bi_dram[i].size; + /* + * Don't report more than 3GiB of SDRAM, otherwise there is no + * address space left for the internal registers etc. + */ + if ((gd->ram_size + gd->bd->bi_dram[i].size != 0) && + (gd->ram_size + gd->bd->bi_dram[i].size <= (3 << 30))) + gd->ram_size += gd->bd->bi_dram[i].size; } diff --git a/arch/arm/mvebu-common/gpio.c b/arch/arm/mvebu-common/gpio.c new file mode 100644 index 0000000..56e54e0 --- /dev/null +++ b/arch/arm/mvebu-common/gpio.c @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +/* + * mvebu_config_gpio - GPIO configuration + */ +void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, + u32 gpp0_oe, u32 gpp1_oe) +{ + struct kwgpio_registers *gpio0reg = + (struct kwgpio_registers *)MVEBU_GPIO0_BASE; + struct kwgpio_registers *gpio1reg = + (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + + /* Init GPIOS to default values as per board requirement */ + writel(gpp0_oe_val, &gpio0reg->dout); + writel(gpp1_oe_val, &gpio1reg->dout); + writel(gpp0_oe, &gpio0reg->oe); + writel(gpp1_oe, &gpio1reg->oe); +} diff --git a/arch/arm/mvebu-common/mbus.c b/arch/arm/mvebu-common/mbus.c new file mode 100644 index 0000000..05c9ef2 --- /dev/null +++ b/arch/arm/mvebu-common/mbus.c @@ -0,0 +1,471 @@ +/* + * Address map functions for Marvell EBU SoCs (Kirkwood, Armada + * 370/XP, Dove, Orion5x and MV78xx0) + * + * Ported from the Barebox version to U-Boot by: + * Stefan Roese <sr@denx.de> + * + * The Barebox version is: + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * + * based on mbus driver from Linux + * (C) Copyright 2008 Marvell Semiconductor + * + * SPDX-License-Identifier: GPL-2.0 + * + * The Marvell EBU SoCs have a configurable physical address space: + * the physical address at which certain devices (PCIe, NOR, NAND, + * etc.) sit can be configured. The configuration takes place through + * two sets of registers: + * + * - One to configure the access of the CPU to the devices. Depending + * on the families, there are between 8 and 20 configurable windows, + * each can be use to create a physical memory window that maps to a + * specific device. Devices are identified by a tuple (target, + * attribute). + * + * - One to configure the access to the CPU to the SDRAM. There are + * either 2 (for Dove) or 4 (for other families) windows to map the + * SDRAM into the physical address space. + * + * This driver: + * + * - Reads out the SDRAM address decoding windows at initialization + * time, and fills the mbus_dram_info structure with these + * informations. The exported function mv_mbus_dram_info() allow + * device drivers to get those informations related to the SDRAM + * address decoding windows. This is because devices also have their + * own windows (configured through registers that are part of each + * device register space), and therefore the drivers for Marvell + * devices have to configure those device -> SDRAM windows to ensure + * that DMA works properly. + * + * - Provides an API for platform code or device drivers to + * dynamically add or remove address decoding windows for the CPU -> + * device accesses. This API is mvebu_mbus_add_window_by_id(), + * mvebu_mbus_add_window_remap_by_id() and + * mvebu_mbus_del_window(). + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <linux/mbus.h> + +#define BIT(nr) (1UL << (nr)) + +/* DDR target is the same on all platforms */ +#define TARGET_DDR 0 + +/* CPU Address Decode Windows registers */ +#define WIN_CTRL_OFF 0x0000 +#define WIN_CTRL_ENABLE BIT(0) +#define WIN_CTRL_TGT_MASK 0xf0 +#define WIN_CTRL_TGT_SHIFT 4 +#define WIN_CTRL_ATTR_MASK 0xff00 +#define WIN_CTRL_ATTR_SHIFT 8 +#define WIN_CTRL_SIZE_MASK 0xffff0000 +#define WIN_CTRL_SIZE_SHIFT 16 +#define WIN_BASE_OFF 0x0004 +#define WIN_BASE_LOW 0xffff0000 +#define WIN_BASE_HIGH 0xf +#define WIN_REMAP_LO_OFF 0x0008 +#define WIN_REMAP_LOW 0xffff0000 +#define WIN_REMAP_HI_OFF 0x000c + +#define ATTR_HW_COHERENCY (0x1 << 4) + +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_BASE_CS_HIGH_MASK 0xf +#define DDR_BASE_CS_LOW_MASK 0xff000000 +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) +#define DDR_SIZE_ENABLED BIT(0) +#define DDR_SIZE_CS_MASK 0x1c +#define DDR_SIZE_CS_SHIFT 2 +#define DDR_SIZE_MASK 0xff000000 + +#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4) + +struct mvebu_mbus_state; + +struct mvebu_mbus_soc_data { + unsigned int num_wins; + unsigned int num_remappable_wins; + unsigned int (*win_cfg_offset)(const int win); + void (*setup_cpu_target)(struct mvebu_mbus_state *s); +}; + +struct mvebu_mbus_state mbus_state + __attribute__ ((section(".data"))); +static struct mbus_dram_target_info mbus_dram_info + __attribute__ ((section(".data"))); + +/* + * Functions to manipulate the address decoding windows + */ + +static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus, + int win, int *enabled, u64 *base, + u32 *size, u8 *target, u8 *attr, + u64 *remap) +{ + void __iomem *addr = mbus->mbuswins_base + + mbus->soc->win_cfg_offset(win); + u32 basereg = readl(addr + WIN_BASE_OFF); + u32 ctrlreg = readl(addr + WIN_CTRL_OFF); + + if (!(ctrlreg & WIN_CTRL_ENABLE)) { + *enabled = 0; + return; + } + + *enabled = 1; + *base = ((u64)basereg & WIN_BASE_HIGH) << 32; + *base |= (basereg & WIN_BASE_LOW); + *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1; + + if (target) + *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT; + + if (attr) + *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT; + + if (remap) { + if (win < mbus->soc->num_remappable_wins) { + u32 remap_low = readl(addr + WIN_REMAP_LO_OFF); + u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF); + *remap = ((u64)remap_hi << 32) | remap_low; + } else { + *remap = 0; + } + } +} + +static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus, + int win) +{ + void __iomem *addr; + + addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); + + writel(0, addr + WIN_BASE_OFF); + writel(0, addr + WIN_CTRL_OFF); + if (win < mbus->soc->num_remappable_wins) { + writel(0, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } +} + +/* Checks whether the given window number is available */ +static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus, + const int win) +{ + void __iomem *addr = mbus->mbuswins_base + + mbus->soc->win_cfg_offset(win); + u32 ctrl = readl(addr + WIN_CTRL_OFF); + return !(ctrl & WIN_CTRL_ENABLE); +} + +/* + * Checks whether the given (base, base+size) area doesn't overlap an + * existing region + */ +static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus, + phys_addr_t base, size_t size, + u8 target, u8 attr) +{ + u64 end = (u64)base + size; + int win; + + for (win = 0; win < mbus->soc->num_wins; win++) { + u64 wbase, wend; + u32 wsize; + u8 wtarget, wattr; + int enabled; + + mvebu_mbus_read_window(mbus, win, + &enabled, &wbase, &wsize, + &wtarget, &wattr, NULL); + + if (!enabled) + continue; + + wend = wbase + wsize; + + /* + * Check if the current window overlaps with the + * proposed physical range + */ + if ((u64)base < wend && end > wbase) + return 0; + + /* + * Check if target/attribute conflicts + */ + if (target == wtarget && attr == wattr) + return 0; + } + + return 1; +} + +static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus, + phys_addr_t base, size_t size) +{ + int win; + + for (win = 0; win < mbus->soc->num_wins; win++) { + u64 wbase; + u32 wsize; + int enabled; + + mvebu_mbus_read_window(mbus, win, + &enabled, &wbase, &wsize, + NULL, NULL, NULL); + + if (!enabled) + continue; + + if (base == wbase && size == wsize) + return win; + } + + return -ENODEV; +} + +static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus, + int win, phys_addr_t base, size_t size, + phys_addr_t remap, u8 target, + u8 attr) +{ + void __iomem *addr = mbus->mbuswins_base + + mbus->soc->win_cfg_offset(win); + u32 ctrl, remap_addr; + + ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | + (attr << WIN_CTRL_ATTR_SHIFT) | + (target << WIN_CTRL_TGT_SHIFT) | + WIN_CTRL_ENABLE; + + writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF); + writel(ctrl, addr + WIN_CTRL_OFF); + if (win < mbus->soc->num_remappable_wins) { + if (remap == MVEBU_MBUS_NO_REMAP) + remap_addr = base; + else + remap_addr = remap; + writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } + + return 0; +} + +static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus, + phys_addr_t base, size_t size, + phys_addr_t remap, u8 target, + u8 attr) +{ + int win; + + if (remap == MVEBU_MBUS_NO_REMAP) { + for (win = mbus->soc->num_remappable_wins; + win < mbus->soc->num_wins; win++) + if (mvebu_mbus_window_is_free(mbus, win)) + return mvebu_mbus_setup_window(mbus, win, base, + size, remap, + target, attr); + } + + + for (win = 0; win < mbus->soc->num_wins; win++) + if (mvebu_mbus_window_is_free(mbus, win)) + return mvebu_mbus_setup_window(mbus, win, base, size, + remap, target, attr); + + return -ENOMEM; +} + +/* + * SoC-specific functions and definitions + */ + +static unsigned int armada_370_xp_mbus_win_offset(int win) +{ + /* The register layout is a bit annoying and the below code + * tries to cope with it. + * - At offset 0x0, there are the registers for the first 8 + * windows, with 4 registers of 32 bits per window (ctrl, + * base, remap low, remap high) + * - Then at offset 0x80, there is a hole of 0x10 bytes for + * the internal registers base address and internal units + * sync barrier register. + * - Then at offset 0x90, there the registers for 12 + * windows, with only 2 registers of 32 bits per window + * (ctrl, base). + */ + if (win < 8) + return win << 4; + else + return 0x90 + ((win - 8) << 3); +} + +static unsigned int orion5x_mbus_win_offset(int win) +{ + return win << 4; +} + +static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) +{ + int i; + int cs; + + mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); + u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); + + /* + * We only take care of entries for which the chip + * select is enabled, and that don't have high base + * address bits set (devices can only access the first + * 32 bits of the memory). + */ + if ((size & DDR_SIZE_ENABLED) && + !(base & DDR_BASE_CS_HIGH_MASK)) { + struct mbus_dram_window *w; + + w = &mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); +#if defined(CONFIG_ARMADA_XP) + w->mbus_attr |= ATTR_HW_COHERENCY; +#endif + w->base = base & DDR_BASE_CS_LOW_MASK; + w->size = (size | ~DDR_SIZE_MASK) + 1; + } + } + mbus_dram_info.num_cs = cs; +} + +static const struct mvebu_mbus_soc_data +armada_370_xp_mbus_data __maybe_unused = { + .num_wins = 20, + .num_remappable_wins = 8, + .win_cfg_offset = armada_370_xp_mbus_win_offset, + .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, +}; + +static const struct mvebu_mbus_soc_data +kirkwood_mbus_data __maybe_unused = { + .num_wins = 8, + .num_remappable_wins = 4, + .win_cfg_offset = orion5x_mbus_win_offset, + .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, +}; + +/* + * Public API of the driver + */ +const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) +{ + return &mbus_dram_info; +} + +int mvebu_mbus_add_window_remap_by_id(unsigned int target, + unsigned int attribute, + phys_addr_t base, size_t size, + phys_addr_t remap) +{ + struct mvebu_mbus_state *s = &mbus_state; + + if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) { + printf("Cannot add window '%x:%x', conflicts with another window\n", + target, attribute); + return -EINVAL; + } + + return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute); +} + +int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, + phys_addr_t base, size_t size) +{ + return mvebu_mbus_add_window_remap_by_id(target, attribute, base, + size, MVEBU_MBUS_NO_REMAP); +} + +int mvebu_mbus_del_window(phys_addr_t base, size_t size) +{ + int win; + + win = mvebu_mbus_find_window(&mbus_state, base, size); + if (win < 0) + return win; + + mvebu_mbus_disable_window(&mbus_state, win); + return 0; +} + +int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, + u32 base, u32 size, u8 target, u8 attr) +{ + if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) { + printf("Cannot add window '%04x:%04x', conflicts with another window\n", + target, attr); + return -EBUSY; + } + + /* + * In U-Boot we first try to add the mbus window to the remap windows. + * If this fails, lets try to add the windows to the non-remap windows. + */ + if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) { + if (mvebu_mbus_alloc_window(mbus, base, size, + MVEBU_MBUS_NO_REMAP, target, attr)) + return -ENOMEM; + } + + return 0; +} + +int mvebu_mbus_probe(struct mbus_win windows[], int count) +{ + int win; + int ret; + int i; + +#if defined(CONFIG_KIRKWOOD) + mbus_state.soc = &kirkwood_mbus_data; +#endif +#if defined(CONFIG_ARMADA_XP) + mbus_state.soc = &armada_370_xp_mbus_data; +#endif + + mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE; + mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE; + + for (win = 0; win < mbus_state.soc->num_wins; win++) + mvebu_mbus_disable_window(&mbus_state, win); + + mbus_state.soc->setup_cpu_target(&mbus_state); + + /* Setup statically declared windows in the DT */ + for (i = 0; i < count; i++) { + u32 base, size; + u8 target, attr; + + target = windows[i].target; + attr = windows[i].attr; + base = windows[i].base; + size = windows[i].size; + ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr); + if (ret < 0) + return ret; + } + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/mvebu-common/timer.c index a08f4a1..40c4bc2 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c +++ b/arch/arm/mvebu-common/timer.c @@ -7,75 +7,68 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> -#define UBOOT_CNTR 0 /* counter to use for uboot timer */ - -/* Timer reload and current value registers */ -struct kwtmr_val { - u32 reload; /* Timer reload reg */ - u32 val; /* Timer value reg */ -}; - -/* Timer registers */ -struct kwtmr_registers { - u32 ctrl; /* Timer control reg */ - u32 pad[3]; - struct kwtmr_val tmr[2]; - u32 wdt_reload; - u32 wdt_val; -}; - -struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE; +#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */ /* * ARM Timers Registers Map */ -#define CNTMR_CTRL_REG &kwtmr_regs->ctrl -#define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload -#define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val +#define CNTMR_CTRL_REG &tmr_regs->ctrl +#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload +#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val /* * ARM Timers Control Register * CPU_TIMERS_CTRL_REG (CTCR) */ #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -/* - * ARM Timer\Watchdog Reload Register - * CNTMR_RELOAD_REG (TRR) - */ -#define TRG_ARM_TIMER_REL_OFFS 0 -#define TRG_ARM_TIMER_REL_MASK 0xffffffff +/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */ +#if defined(CONFIG_ARMADA_XP) +#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11) +#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr)) +#else +#define CTCR_ARM_TIMER_25MHZ(cntr) 0 +#endif -/* - * ARM Timer\Watchdog Register - * CNTMR_VAL_REG (TVRG) - */ -#define TVR_ARM_TIMER_OFFS 0 -#define TVR_ARM_TIMER_MASK 0xffffffff -#define TVR_ARM_TIMER_MAX 0xffffffff #define TIMER_LOAD_VAL 0xffffffff -#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \ - (CONFIG_SYS_TCLK / 1000)) +#define timestamp gd->arch.tbl +#define lastdec gd->arch.lastinc + +/* Timer reload and current value registers */ +struct kwtmr_val { + u32 reload; /* Timer reload reg */ + u32 val; /* Timer value reg */ +}; + +/* Timer registers */ +struct kwtmr_registers { + u32 ctrl; /* Timer control reg */ + u32 pad[3]; + struct kwtmr_val tmr[4]; + u32 wdt_reload; + u32 wdt_val; +}; DECLARE_GLOBAL_DATA_PTR; -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc +static struct kwtmr_registers *tmr_regs = + (struct kwtmr_registers *)MVEBU_TIMER_BASE; + +static inline ulong read_timer(void) +{ + return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000); +} ulong get_timer_masked(void) { - ulong now = READ_TIMER; + ulong now = read_timer(); if (lastdec >= now) { /* normal mode */ @@ -119,20 +112,17 @@ void __udelay(unsigned long usec) */ int timer_init(void) { - unsigned int cntmrctrl; - /* load value into timer */ writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); /* enable timer in auto reload mode */ - cntmrctrl = readl(CNTMR_CTRL_REG); - cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); - cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); - writel(cntmrctrl, CNTMR_CTRL_REG); + clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR), + CTCR_ARM_TIMER_EN(UBOOT_CNTR) | + CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR)); /* init the timestamp and lastdec value */ - lastdec = READ_TIMER; + lastdec = read_timer(); timestamp = 0; return 0; |