diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/config.mk | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/cache_v7.c | 21 | ||||
| -rw-r--r-- | arch/arm/cpu/u-boot.lds | 27 | ||||
| -rw-r--r-- | arch/arm/include/asm/system.h | 7 | ||||
| -rw-r--r-- | arch/arm/lib/cache-cp15.c | 2 |
5 files changed, 40 insertions, 18 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index a3e14a8..8fa57ec 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -107,6 +107,7 @@ ALL-y += checkarmreloc # instruction. Relocation is not supported for that case, so disable # such usage by requiring word relocations. PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations) +PLATFORM_CPPFLAGS += $(call cc-option, -fno-pic) endif # limit ourselves to the sections we want in the .bin. diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index a5aa4fa..94ff488 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -16,6 +16,23 @@ #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 #ifndef CONFIG_SYS_DCACHE_OFF +static int check_cache_range(unsigned long start, unsigned long stop) +{ + int ok = 1; + + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (!ok) + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + start, stop); + + return ok; +} + /* * Write the level and type you want to Cache Size Selection Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { + check_cache_range(start, stop); + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); v7_outer_cache_inval_range(start, stop); @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) */ void flush_dcache_range(unsigned long start, unsigned long stop) { + check_cache_range(start, stop); + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); v7_outer_cache_flush_range(start, stop); diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index d48a905..e148ab7 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -14,23 +14,24 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { +#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) /* - * Discard the relocation entries for secure text. - * The secure code is bundled with u-boot image, so there will - * be relocations entries for the secure code, since we use - * "-mword-relocations" to compile and "-pie" to link into the - * final image. We do not need the relocation entries for secure - * code, because secure code will not be relocated, it only needs - * to be copied from loading address to CONFIG_ARMV7_SECURE_BASE, - * which is the linking and running address for secure code. - * If keep the relocation entries in .rel.dyn section, - * "relocation offset + linking address" may locates into an - * address that is reserved by SoC, then will trigger data abort. + * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not + * bundle with u-boot, and code offsets are fixed. Secure zone + * only needs to be copied from the loading address to + * CONFIG_ARMV7_SECURE_BASE, which is the linking and running + * address for secure code. * - * The reason that move .rel._secure at the beginning, is to - * avoid hole in the final image. + * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will + * be included in u-boot address space, and some absolute address + * were used in secure code. The absolute addresses of the secure + * code also needs to be relocated along with the accompanying u-boot + * code. + * + * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. */ /DISCARD/ : { *(.rel._secure*) } +#endif . = 0x00000000; . = ALIGN(4); diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 67cbbc2..026e7ef 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -259,7 +259,7 @@ static inline void set_dacr(unsigned int val) isb(); } -#ifdef CONFIG_ARMV7 +#ifdef CONFIG_CPU_V7 /* Short-Descriptor Translation Table Level 1 Bits */ #define TTB_SECT_NS_MASK (1 << 19) #define TTB_SECT_NG_MASK (1 << 17) @@ -274,8 +274,7 @@ static inline void set_dacr(unsigned int val) /* options available for data cache on each page */ enum dcache_option { - DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) | - TTB_SECT_XN_MASK | TTB_SECT, + DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), @@ -296,7 +295,7 @@ enum { MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, }; -#ifdef CONFIG_ARMV7 +#ifdef CONFIG_CPU_V7 /* TTBR0 bits */ #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 #define TTBR0_RGN_NC (0 << 3) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index c65e068..8e18538 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -96,7 +96,7 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); } -#ifdef CONFIG_ARMV7 +#ifdef CONFIG_CPU_V7 /* Set TTBR0 */ reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |