diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/s5p-common/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/s5p-common/sromc.c (renamed from arch/arm/cpu/armv7/s5pc1xx/sromc.c) | 22 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/s5pc1xx/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc1xx/sromc.h (renamed from arch/arm/include/asm/arch-s5pc1xx/smc.h) | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/sromc.h | 51 |
5 files changed, 68 insertions, 17 deletions
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index ce0a41e..1705399 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -27,7 +27,8 @@ LIB = $(obj)libs5p-common.o COBJS-y += cpu_info.o COBJS-y += timer.o -COBJS-$(CONFIG_PWM) += pwm.o +COBJS-y += sromc.o +COBJS-$(CONFIG_PWM) += pwm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5p-common/sromc.c index 044d122..091e8d1 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/sromc.c +++ b/arch/arm/cpu/armv7/s5p-common/sromc.c @@ -23,27 +23,27 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/smc.h> +#include <asm/arch/sromc.h> /* - * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the - * band width control and bank control registers - * srom_bank - SROM Bank 0 to 5 - * smc_bw_conf - SMC Band witdh reg configuration value - * smc_bc_conf - SMC Bank Control reg configuration value + * s5p_config_sromc() - select the proper SROMC Bank and configure the + * band width control and bank control registers + * srom_bank - SROM + * srom_bw_conf - SMC Band witdh reg configuration value + * srom_bc_conf - SMC Bank Control reg configuration value */ -void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf) +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf) { u32 tmp; - struct s5pc1xx_smc *srom = - (struct s5pc1xx_smc *)samsung_get_base_sromc(); + struct s5p_sromc *srom = + (struct s5p_sromc *)samsung_get_base_sromc(); /* Configure SMC_BW register to handle proper SROMC bank */ tmp = srom->bw; tmp &= ~(0xF << (srom_bank * 4)); - tmp |= smc_bw_conf; + tmp |= srom_bw_conf; srom->bw = tmp; /* Configure SMC_BC register */ - srom->bc[srom_bank] = smc_bc_conf; + srom->bc[srom_bank] = srom_bc_conf; } diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile index b182bf5..d66314e 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Makefile +++ b/arch/arm/cpu/armv7/s5pc1xx/Makefile @@ -32,7 +32,6 @@ SOBJS = cache.o SOBJS += reset.o COBJS += clock.o -COBJS += sromc.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/include/asm/arch-s5pc1xx/smc.h b/arch/arm/include/asm/arch-s5pc1xx/sromc.h index 88f4ffe..3800a8d 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/smc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/sromc.h @@ -23,8 +23,8 @@ * Only SROMC is defined as of now */ -#ifndef __ASM_ARCH_SMC_H_ -#define __ASM_ARCH_SMC_H_ +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ #define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) #define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ @@ -41,13 +41,13 @@ #define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ #ifndef __ASSEMBLY__ -struct s5pc1xx_smc { +struct s5p_sromc { unsigned int bw; unsigned int bc[6]; }; #endif /* __ASSEMBLY__ */ /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ -void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf); +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); #endif /* __ASM_ARCH_SMC_H_ */ diff --git a/arch/arm/include/asm/arch-s5pc2xx/sromc.h b/arch/arm/include/asm/arch-s5pc2xx/sromc.h new file mode 100644 index 0000000..f616bcb --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc2xx/sromc.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for SROMC + * + */ + +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ + +#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SROMC_BC_TACS(x) (x << 28) /* address set-up */ +#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ +#define SROMC_BC_TACC(x) (x << 16) /* access cycle */ +#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ +#define SROMC_BC_TAH(x) (x << 8) /* address holding time */ +#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ +#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5p_sromc { + unsigned int bw; + unsigned int bc[4]; +}; +#endif /* __ASSEMBLY__ */ + +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); + +#endif /* __ASM_ARCH_SROMC_H_ */ |