diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/Kconfig | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 12 | ||||
| -rw-r--r-- | arch/arm/include/asm/imx-common/iomux-v3.h | 2 |
4 files changed, 18 insertions, 3 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 42f3df2..1972de8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -1221,8 +1221,8 @@ void mxs_power_init(void) debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n"); mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150); - debug("SPL: Setting VDDD to 1V5 (brownout @ 1v0)\n"); - mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000); + debug("SPL: Setting VDDD to 1V5 (brownout @ 1v315)\n"); + mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1315); #ifdef CONFIG_MX23 debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n"); mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700); diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 273e209..8489182 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -46,6 +46,9 @@ config TARGET_ARISTAINETOS2B config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" + select SUPPORT_SPL + select DM + select DM_THERMAL config TARGET_CM_FX6 bool "CM-FX6" diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 67e0f32..d325191 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg) MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); +#if defined(CONFIG_MX6SX) + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); + + clrsetbits_le32(&imx_ccm->cs2cdr, + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK, + cfg); + + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); +#else clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); clrsetbits_le32(&imx_ccm->cs2cdr, @@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg) cfg); setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); +#endif setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 1a80a96..2e49968 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -236,7 +236,7 @@ void imx_iomux_gpio_get_function(unsigned int gpio, #if defined(CONFIG_MX6QDL) #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x) #define SETUP_IOMUX_PAD(def) \ -if (is_cpu_type(MXC_CPU_MX6Q)) { \ +if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \ imx_iomux_v3_setup_pad(MX6Q_##def); \ } else { \ imx_iomux_v3_setup_pad(MX6DL_##def); \ |