diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 54 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 14 |
2 files changed, 54 insertions, 14 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 28589ae..94ec8d5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,24 +1,33 @@ config ARCH_LS1012A bool select FSL_LSCH2 + select SYS_FSL_DDR_BE select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315 config ARCH_LS1043A bool select FSL_LSCH2 + select SYS_FSL_DDR_BE + select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 config ARCH_LS1046A bool select FSL_LSCH2 + select SYS_FSL_DDR_BE + select SYS_FSL_DDR4 + select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_SRDS_2 config ARCH_LS2080A bool select FSL_LSCH3 + select SYS_FSL_DDR4 + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 select SYS_FSL_HAS_DP_DDR select SYS_FSL_SRDS_2 @@ -81,4 +90,49 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool +config SYS_FSL_DDR + bool "Freescale DDR driver" + help + Select Freescale General DDR driver, shared between most Freescale + PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- + based Layerscape SoCs (such as ls2080a). + +config SYS_FSL_DDR_BE + bool + help + Access DDR registers in big-endian. + +config SYS_FSL_DDR_LE + bool + help + Access DDR registers in little-endian. + +config SYS_FSL_DDR_VER + int + default 50 if SYS_FSL_DDR_VER_50 + +config SYS_FSL_DDR_VER_50 + bool + +config SYS_FSL_DDRC_ARM_GEN3 + bool + +config SYS_FSL_DDRC_GEN4 + bool + +config SYS_FSL_DDR3 + bool "Freescale DDR3 controller" + depends on !SYS_FSL_DDR4 + select SYS_FSL_DDR + select SYS_FSL_DDRC_ARM_GEN3 + help + Enable Freescale DDR3 controller on ARM-based SoCs. + +config SYS_FSL_DDR4 + bool "Freescale DDR4 controller" + select SYS_FSL_DDR + select SYS_FSL_DDRC_GEN4 + help + Enable Freescale DDR4 controller. + endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 3039e72..4201e0f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -12,17 +12,6 @@ #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#else -#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ -#endif - -#ifndef CONFIG_ARCH_LS1012A -#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -#endif - /* * Reserve secure memory * To be aligned with MMU block size @@ -42,7 +31,6 @@ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ /* DDR */ -#define CONFIG_SYS_FSL_DDR_LE #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE @@ -166,7 +154,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -204,7 +191,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE |