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-rw-r--r--arch/arm/cpu/arm720t/tegra-common/cpu.c89
-rw-r--r--arch/arm/cpu/tegra-common/ap.c1
-rw-r--r--arch/arm/include/asm/arch-tegra/clock.h6
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra.h1
4 files changed, 69 insertions, 28 deletions
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 9294611..72c69b9 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -49,33 +49,68 @@ int get_num_cpus(void)
* Timing tables for each SOC for all four oscillator options.
*/
struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
- /* T20: 1 GHz */
- /* n, m, p, cpcon */
- {{ 1000, 13, 0, 12}, /* OSC 13M */
- { 625, 12, 0, 8}, /* OSC 19.2M */
- { 1000, 12, 0, 12}, /* OSC 12M */
- { 1000, 26, 0, 12}, /* OSC 26M */
+ /*
+ * T20: 1 GHz
+ *
+ * Register Field Bits Width
+ * ------------------------------
+ * PLLX_BASE p 22:20 3
+ * PLLX_BASE n 17: 8 10
+ * PLLX_BASE m 4: 0 5
+ * PLLX_MISC cpcon 11: 8 4
+ */
+ {
+ { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+ { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
+ { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+ { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
},
-
- /* T25: 1.2 GHz */
- {{ 923, 10, 0, 12},
- { 750, 12, 0, 8},
- { 600, 6, 0, 12},
- { 600, 13, 0, 12},
+ /*
+ * T25: 1.2 GHz
+ *
+ * Register Field Bits Width
+ * ------------------------------
+ * PLLX_BASE p 22:20 3
+ * PLLX_BASE n 17: 8 10
+ * PLLX_BASE m 4: 0 5
+ * PLLX_MISC cpcon 11: 8 4
+ */
+ {
+ { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+ { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
+ { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+ { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
},
-
- /* T30: 1.4 GHz */
- {{ 862, 8, 0, 8},
- { 583, 8, 0, 4},
- { 700, 6, 0, 8},
- { 700, 13, 0, 8},
+ /*
+ * T30: 1.4 GHz
+ *
+ * Register Field Bits Width
+ * ------------------------------
+ * PLLX_BASE p 22:20 3
+ * PLLX_BASE n 17: 8 10
+ * PLLX_BASE m 4: 0 5
+ * PLLX_MISC cpcon 11: 8 4
+ */
+ {
+ { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
+ { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
+ { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
+ { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
},
-
- /* T114: 1.4 GHz */
- {{ 862, 8, 0, 8},
- { 583, 8, 0, 4},
- { 696, 12, 0, 8},
- { 700, 13, 0, 8},
+ /*
+ * T114: 700 MHz
+ *
+ * Register Field Bits Width
+ * ------------------------------
+ * PLLX_BASE p 23:20 4
+ * PLLX_BASE n 15: 8 8
+ * PLLX_BASE m 7: 0 8
+ */
+ {
+ { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+ { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
},
};
@@ -100,6 +135,7 @@ void adjust_pllp_out_freqs(void)
int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
u32 divp, u32 cpcon)
{
+ int chip = tegra_get_chip();
u32 reg;
/* If PLLX is already enabled, just return */
@@ -116,7 +152,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */
- reg = (cpcon << PLL_CPCON_SHIFT);
+ if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
+ reg = (cpcon << PLL_CPCON_SHIFT);
+ else
+ reg = 0;
/* Set dccon to PLLX_MISC if freq > 600MHz */
if (divn > 600)
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 6fb11cb..60d71a6 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -71,6 +71,7 @@ int tegra_get_chip_sku(void)
switch (sku_id) {
case SKU_ID_T33:
case SKU_ID_T30:
+ case SKU_ID_TM30MQS_P_A3:
return TEGRA_SOC_T30;
}
break;
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index c3174bd..e7d0fd4 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -113,9 +113,9 @@ void reset_set_enable(enum periph_id periph_id, int enable);
enum crc_reset_id {
/* Things we can hold in reset for each CPU */
crc_rst_cpu = 1,
- crc_rst_de = 1 << 2, /* What is de? */
- crc_rst_watchdog = 1 << 3,
- crc_rst_debug = 1 << 4,
+ crc_rst_de = 1 << 4, /* What is de? */
+ crc_rst_watchdog = 1 << 8,
+ crc_rst_debug = 1 << 12,
};
/**
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 25d1fc4..e99f681 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -65,6 +65,7 @@ enum {
SKU_ID_T25E = 0x1c,
SKU_ID_T33 = 0x80,
SKU_ID_T30 = 0x81, /* Cardhu value */
+ SKU_ID_TM30MQS_P_A3 = 0xb1,
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
SKU_ID_T114_1 = 0x01,
};