diff options
Diffstat (limited to 'arch/arm')
43 files changed, 448 insertions, 269 deletions
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 8873fb7..93f429c 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <div64.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/io.h> @@ -30,16 +31,17 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq) { u32 mfi = GET_PLL_MFI(reg); - u32 mfn = GET_PLL_MFN(reg); + s32 mfn = GET_PLL_MFN(reg); u32 mfd = GET_PLL_MFD(reg); u32 pd = GET_PLL_PD(reg); mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1; - return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / - (mfd * pd)) << 10; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); } static u32 mx31_get_mpl_dpdgck_clk(void) @@ -47,9 +49,9 @@ static u32 mx31_get_mpl_dpdgck_clk(void) u32 infreq; if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) - infreq = CONFIG_MX31_CLK32 * 1024; + infreq = MXC_CLK32 * 1024; else - infreq = CONFIG_MX31_HCLK_FREQ; + infreq = MXC_HCLK; return mx31_decode_pll(readl(CCM_MPCTL), infreq); } diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index 72081a8..36266da 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> #include <div64.h> #include <watchdog.h> #include <asm/io.h> @@ -53,28 +54,27 @@ DECLARE_GLOBAL_DATA_PTR; static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX31_CLK32); + do_div(tick, MXC_CLK32); return tick; } static inline unsigned long long time_to_tick(unsigned long long time) { - time *= CONFIG_MX31_CLK32; + time *= MXC_CLK32; do_div(time, CONFIG_SYS_HZ); return time; } static inline unsigned long long us_to_tick(unsigned long long us) { - us = us * CONFIG_MX31_CLK32 + 999999; + us = us * MXC_CLK32 + 999999; do_div(us, 1000000); return us; } #else /* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \ - / CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) +#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / MXC_CLK32) static inline unsigned long long tick_to_time(unsigned long long tick) { @@ -128,7 +128,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -159,7 +159,7 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return CONFIG_MX31_CLK32; + return MXC_CLK32; } void reset_cpu(ulong addr) diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index d435e8a..ef65176 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -24,6 +24,7 @@ */ #include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> @@ -129,15 +130,17 @@ static int get_ahb_div(u32 pdr0) static u32 decode_pll(u32 reg, u32 infreq) { u32 mfi = (reg >> 10) & 0xf; - u32 mfn = reg & 0x3f; - u32 mfd = (reg >> 16) & 0x3f; + s32 mfn = reg & 0x3ff; + u32 mfd = (reg >> 16) & 0x3ff; u32 pd = (reg >> 26) & 0xf; mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1; - return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); } static u32 get_mcu_main_clk(void) @@ -146,9 +149,7 @@ static u32 get_mcu_main_clk(void) struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); - fi *= - decode_pll(readl(&ccm->mpctl), - CONFIG_MX35_HCLK_FREQ); + fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); return fi / (arm_div * fd); } @@ -171,17 +172,14 @@ static u32 get_ipg_per_clk(void) u32 pdr4 = readl(&ccm->pdr4); u32 div; if (pdr0 & MXC_CCM_PDR0_PER_SEL) { - div = (CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_PER0_PRDF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + div = CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_PER0_PODF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; } else { div = CCM_GET_DIVIDER(pdr0, MXC_CCM_PDR0_PER_PODF_MASK, MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; - freq /= get_ahb_div(pdr0); + div *= get_ahb_div(pdr0); } return freq / div; } @@ -193,25 +191,20 @@ u32 imx_get_uartclk(void) (struct ccm_regs *)IMX_CCM_BASE; u32 pdr4 = readl(&ccm->pdr4); - if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) { + if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) freq = get_mcu_main_clk(); - } else { - freq = decode_pll(readl(&ccm->ppctl), - CONFIG_MX35_HCLK_FREQ); - } - freq /= ((CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_UART_PRDF_MASK, - MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + else + freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK); + freq /= CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_UART_PODF_MASK, - MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; return freq; } unsigned int mxc_get_main_clock(enum mxc_main_clock clk) { u32 nfc_pdf, hsp_podf; - u32 pll, ret_val = 0, usb_prdf, usb_podf; + u32 pll, ret_val = 0, usb_podf; struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; @@ -255,16 +248,13 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) ret_val = pll / (nfc_pdf + 1); break; case USB_CLK: - usb_prdf = (reg4 >> 25) & 0x7; - usb_podf = (reg4 >> 22) & 0x7; - if (reg4 & 0x200) { + usb_podf = (reg4 >> 22) & 0x3F; + if (reg4 & 0x200) pll = get_mcu_main_clk(); - } else { - pll = decode_pll(readl(&ccm->ppctl), - CONFIG_MX35_HCLK_FREQ); - } + else + pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK); - ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); + ret_val = pll / (usb_podf + 1); break; default: printf("Unknown clock: %d\n", clk); @@ -287,18 +277,16 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) case UART2_BAUD: case UART3_BAUD: clk_sel = mpdr3 & (1 << 14); - pre_pdf = (mpdr4 >> 13) & 0x7; - pdf = (mpdr4 >> 10) & 0x7; + pdf = (mpdr4 >> 10) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case SSI1_BAUD: pre_pdf = (mpdr2 >> 24) & 0x7; pdf = mpdr2 & 0x3F; clk_sel = mpdr2 & (1 << 6); ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case SSI2_BAUD: @@ -306,16 +294,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) pdf = (mpdr2 >> 8) & 0x3F; clk_sel = mpdr2 & (1 << 6); ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case CSI_BAUD: clk_sel = mpdr2 & (1 << 7); - pre_pdf = (mpdr2 >> 16) & 0x7; - pdf = (mpdr2 >> 19) & 0x7; + pdf = (mpdr2 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case MSHC_CLK: pre_pdf = readl(&ccm->pdr1); @@ -323,39 +309,33 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) pdf = (pre_pdf >> 22) & 0x3F; pre_pdf = (pre_pdf >> 28) & 0x7; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case ESDHC1_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = mpdr3 & 0x7; - pdf = (mpdr3>>3) & 0x7; + pdf = mpdr3 & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case ESDHC2_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 8) & 0x7; - pdf = (mpdr3 >> 11) & 0x7; + pdf = (mpdr3 >> 8) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case ESDHC3_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 16) & 0x7; - pdf = (mpdr3 >> 19) & 0x7; + pdf = (mpdr3 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case SPDIF_CLK: clk_sel = mpdr3 & 0x400000; pre_pdf = (mpdr3 >> 29) & 0x7; pdf = (mpdr3 >> 23) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; default: diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c index 04937a1..9680b7f 100644 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -27,6 +27,7 @@ #include <asm/io.h> #include <div64.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> DECLARE_GLOBAL_DATA_PTR; @@ -37,43 +38,52 @@ DECLARE_GLOBAL_DATA_PTR; /* General purpose timers bitfields */ #define GPTCR_SWR (1<<15) /* Software reset */ #define GPTCR_FRR (1<<9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ -#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ #define GPTCR_TEN (1) /* Timer enable */ -#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK) - +/* + * "time" is measured in 1 / CONFIG_SYS_HZ seconds, + * "tick" is internal timer period + */ +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ_HZ); + do_div(tick, MXC_CLK32); return tick; } -static inline unsigned long long us_to_tick(unsigned long long usec) +static inline unsigned long long us_to_tick(unsigned long long us) { - usec *= TIMER_FREQ_HZ; - do_div(usec, 1000000); + us = us * MXC_CLK32 + 999999; + do_div(us, 1000000); - return usec; + return us; } +/* + * nothing really to do with interrupts, just starts up a counter. + * The 32KHz 32-bit timer overruns in 134217 seconds + */ int timer_init(void) { int i; struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR; /* setup GP Timer 1 */ writel(GPTCR_SWR, &gpt->ctrl); - for (i = 0; i < 100; i++) - writel(0, &gpt->ctrl); /* We have no udelay by now */ - writel(0, &gpt->pre); - /* Freerun Mode, PERCLK1 input */ - writel(readl(&gpt->ctrl) | - GPTCR_CLKSOURCE_IPG | GPTCR_TEN, - &gpt->ctrl); + writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1); + + for (i = 0; i < 100; i++) + writel(0, &gpt->ctrl); /* We have no udelay by now */ + writel(0, &gpt->pre); /* prescaler = 1 */ + /* Freerun Mode, 32KHz input */ + writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, + &gpt->ctrl); + writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); return 0; } @@ -101,7 +111,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -132,5 +142,5 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return TIMER_FREQ_HZ; + return MXC_CLK32; } diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c index 6d4d66b..ddf8d97 100644 --- a/arch/arm/cpu/arm720t/tegra20/cpu.c +++ b/arch/arm/cpu/arm720t/tegra20/cpu.c @@ -105,14 +105,14 @@ static void enable_cpu_clock(int enable) static int is_cpu_powered(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; } static void remove_cpu_io_clamps(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; /* Remove the clamps on the CPU I/O signals */ @@ -126,7 +126,7 @@ static void remove_cpu_io_clamps(void) static void powerup_cpu(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; int timeout = IO_STABILIZATION_DELAY; @@ -157,7 +157,7 @@ static void powerup_cpu(void) static void enable_cpu_power_rail(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; reg = readl(&pmc->pmc_cntrl); diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index a412a8f..90e584a 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -64,7 +64,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) static ulong imx_get_mpllclk(void) { struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong fref = 24000000; + ulong fref = MXC_HCLK; return imx_decode_pll(readl(&ccm->mpctl), fref); } diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c index 1cfd02b..4dc4041 100644 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ b/arch/arm/cpu/arm926ejs/mx25/timer.c @@ -40,6 +40,7 @@ #include <div64.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,28 +56,27 @@ DECLARE_GLOBAL_DATA_PTR; static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX25_CLK32); + do_div(tick, MXC_CLK32); return tick; } static inline unsigned long long time_to_tick(unsigned long long time) { - time *= CONFIG_MX25_CLK32; + time *= MXC_CLK32; do_div(time, CONFIG_SYS_HZ); return time; } static inline unsigned long long us_to_tick(unsigned long long us) { - us = us * CONFIG_MX25_CLK32 + 999999; + us = us * MXC_CLK32 + 999999; do_div(us, 1000000); return us; } #else /* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \ - CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32) +#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / MXC_CLK32) static inline unsigned long long tick_to_time(unsigned long long tick) { @@ -144,7 +144,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -177,6 +177,6 @@ ulong get_tbclk(void) { ulong tbclk; - tbclk = CONFIG_MX25_CLK32; + tbclk = MXC_CLK32; return tbclk; } diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index ddafddb..ad66c57 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -38,12 +38,14 @@ * takes a few seconds to roll. The boot doesn't take that long, so to keep the * code simple, it doesn't take rolling into consideration. */ -#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0 void early_delay(int delay) { - uint32_t st = readl(HW_DIGCTRL_MICROSECONDS); + struct mxs_digctl_regs *digctl_regs = + (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; + + uint32_t st = readl(&digctl_regs->hw_digctl_microseconds); st += delay; - while (st > readl(HW_DIGCTRL_MICROSECONDS)) + while (st > readl(&digctl_regs->hw_digctl_microseconds)) ; } diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 792b11d..c3948d3 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -292,7 +292,9 @@ int arch_misc_init(void) writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00); writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04); writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50); + writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00); writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04); + writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c); /* initialize timer */ timer_init_r(); diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index b387ac2..ecc2671 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -37,7 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; static const struct gpio_bank gpio_bank_am33xx[4] = { @@ -119,22 +118,6 @@ static int read_eeprom(void) #define UART_SMART_IDLE_EN (0x1 << 0x3) #endif -#ifdef CONFIG_SPL_BUILD -/* Initialize timer */ -static void init_timer(void) -{ - /* Reset the Timer */ - writel(0x2, (&timer_base->tscir)); - - /* Wait until the reset is done */ - while (readl(&timer_base->tiocp_cfg) & 1) - ; - - /* Start the Timer */ - writel(0x1, (&timer_base->tclr)); -} -#endif - /* * Determine what type of DDR we have. */ @@ -183,9 +166,6 @@ void s_init(void) regVal |= UART_SMART_IDLE_EN; writel(regVal, &uart_base->uartsyscfg); - /* Initialize the Timer */ - init_timer(); - preloader_console_init(); /* Initalize the board header */ diff --git a/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c b/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c index 75cadb0..925f841 100644 --- a/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c +++ b/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c @@ -46,7 +46,7 @@ static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; puts("Entering RCM...\n"); udelay(50000); diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c index 178bb13..cac0918 100644 --- a/arch/arm/cpu/armv7/tegra20/usb.c +++ b/arch/arm/cpu/armv7/tegra20/usb.c @@ -137,24 +137,29 @@ static const u8 utmip_elastic_limit = 16; /* UTMIP High Speed Sync Start Delay */ static const u8 utmip_hs_sync_start_delay = 9; -/* Put the port into host mode (this only works for OTG ports) */ +/* Put the port into host mode */ static void set_host_mode(struct fdt_usb *config) { - if (config->dr_mode == DR_MODE_OTG) { - /* Check whether remote host from USB1 is driving VBus */ - if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS) - return; - - /* - * If not driving, we set the GPIO to enable VBUS. We assume - * that the pinmux is set up correctly for this. - */ - if (fdt_gpio_isvalid(&config->vbus_gpio)) { - fdtdec_setup_gpio(&config->vbus_gpio); - gpio_direction_output(config->vbus_gpio.gpio, 1); - debug("set_host_mode: GPIO %d high\n", - config->vbus_gpio.gpio); - } + /* + * If we are an OTG port, check if remote host is driving VBus and + * bail out in this case. + */ + if (config->dr_mode == DR_MODE_OTG && + (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) + return; + + /* + * If not driving, we set the GPIO to enable VBUS. We assume + * that the pinmux is set up correctly for this. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + fdtdec_setup_gpio(&config->vbus_gpio); + gpio_direction_output(config->vbus_gpio.gpio, + (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? + 0 : 1); + debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, + (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? + "low" : "high"); } } diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile index 43c96c6..9e91e5c 100644 --- a/arch/arm/cpu/tegra20-common/Makefile +++ b/arch/arm/cpu/tegra20-common/Makefile @@ -33,7 +33,7 @@ LIB = $(obj)lib$(SOC)-common.o SOBJS += lowlevel_init.o COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o -COBJS-$(CONFIG_TEGRA20_LP0) += warmboot.o crypto.o warmboot_avp.o +COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o COBJS-$(CONFIG_TEGRA_PMU) += pmu.o diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c index 00588da..c0ca6eb 100644 --- a/arch/arm/cpu/tegra20-common/ap20.c +++ b/arch/arm/cpu/tegra20-common/ap20.c @@ -32,7 +32,7 @@ int tegra_get_chip_type(void) { struct apb_misc_gp_ctlr *gp; - struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; uint tegra_sku_id, rev; /* @@ -40,7 +40,7 @@ int tegra_get_chip_type(void) * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for * Tegra30 */ - gp = (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE; + gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; tegra_sku_id = readl(&fuse->sku_info) & 0xff; @@ -101,7 +101,7 @@ static u32 get_odmdata(void) static void init_pmc_scratch(void) { - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 odmdata; int i; diff --git a/arch/arm/cpu/tegra20-common/board.c b/arch/arm/cpu/tegra20-common/board.c index 598023a..8a8d338 100644 --- a/arch/arm/cpu/tegra20-common/board.c +++ b/arch/arm/cpu/tegra20-common/board.c @@ -47,7 +47,7 @@ enum { unsigned int query_sdram_size(void) { - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; reg = readl(&pmc->pmc_scratch20); @@ -81,11 +81,11 @@ int checkboard(void) #endif /* CONFIG_DISPLAY_BOARDINFO */ static int uart_configs[] = { -#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB) +#if defined(CONFIG_TEGRA_UARTA_UAA_UAB) FUNCMUX_UART1_UAA_UAB, -#elif defined(CONFIG_TEGRA20_UARTA_GPU) +#elif defined(CONFIG_TEGRA_UARTA_GPU) FUNCMUX_UART1_GPU, -#elif defined(CONFIG_TEGRA20_UARTA_SDIO1) +#elif defined(CONFIG_TEGRA_UARTA_SDIO1) FUNCMUX_UART1_SDIO1, #else FUNCMUX_UART1_IRRX_IRTX, @@ -125,13 +125,13 @@ void board_init_uart_f(void) { int uart_ids = 0; /* bit mask of which UART ids to enable */ -#ifdef CONFIG_TEGRA20_ENABLE_UARTA +#ifdef CONFIG_TEGRA_ENABLE_UARTA uart_ids |= UARTA; #endif -#ifdef CONFIG_TEGRA20_ENABLE_UARTB +#ifdef CONFIG_TEGRA_ENABLE_UARTB uart_ids |= UARTB; #endif -#ifdef CONFIG_TEGRA20_ENABLE_UARTD +#ifdef CONFIG_TEGRA_ENABLE_UARTD uart_ids |= UARTD; #endif setup_uarts(uart_ids); diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c index 8cfed64..b2129ad 100644 --- a/arch/arm/cpu/tegra20-common/funcmux.c +++ b/arch/arm/cpu/tegra20-common/funcmux.c @@ -234,6 +234,13 @@ int funcmux_select(enum periph_id id, int config) } break; + case PERIPH_ID_NDFLASH: + if (config == FUNCMUX_NDFLASH_ATC) { + pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND); + pinmux_tristate_disable(PINGRP_ATC); + } + break; + default: debug("%s: invalid periph_id %d", __func__, id); return -1; diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c index 809ea01..6ce995e 100644 --- a/arch/arm/cpu/tegra20-common/warmboot.c +++ b/arch/arm/cpu/tegra20-common/warmboot.c @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_TEGRA_CLOCK_SCALING -#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0" +#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0" #endif /* @@ -139,9 +139,9 @@ int warmboot_save_sdram_params(void) u32 ram_code; struct sdram_params sdram; struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE; + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob); union scratch2_reg scratch2; union scratch4_reg scratch4; @@ -205,7 +205,7 @@ static u32 get_major_version(void) { u32 major_id; struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE; + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >> HIDREV_MAJORPREV_SHIFT; @@ -229,7 +229,7 @@ static int is_failure_analysis_mode(struct fuse_regs *fuse) static int ap20_is_odm_production_mode(void) { - struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; if (!is_failure_analysis_mode(fuse) && is_odm_production_mode_fuse_set(fuse)) @@ -240,7 +240,7 @@ static int ap20_is_odm_production_mode(void) static int ap20_is_production_mode(void) { - struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; if (get_major_version() == 0) return 1; @@ -257,7 +257,7 @@ static enum fuse_operating_mode fuse_get_operation_mode(void) { u32 chip_id; struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE; + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c index cd01908..80a5a15 100644 --- a/arch/arm/cpu/tegra20-common/warmboot_avp.c +++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c @@ -38,7 +38,7 @@ void wb_start(void) { struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index f95be58..d936b1e 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -204,4 +204,11 @@ compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x0078>; }; + + nand: nand-controller@70008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + }; }; diff --git a/arch/arm/cpu/armv7/imx-common/Makefile b/arch/arm/imx-common/Makefile index 16fba8d..b3e608e 100644 --- a/arch/arm/cpu/armv7/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -27,8 +27,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)libimx-common.o +ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) COBJS-y = iomux-v3.o timer.o cpu.o speed.o -COBJS-$(CONFIG_I2C_MXC) += i2c.o +COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o +endif COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o COBJS := $(sort $(COBJS-y)) diff --git a/arch/arm/cpu/armv7/imx-common/cmd_bmode.c b/arch/arm/imx-common/cmd_bmode.c index 02fe72e..02fe72e 100644 --- a/arch/arm/cpu/armv7/imx-common/cmd_bmode.c +++ b/arch/arm/imx-common/cmd_bmode.c diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index fa1d468..fa1d468 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c diff --git a/arch/arm/cpu/armv7/imx-common/i2c.c b/arch/arm/imx-common/i2c-mxv7.c index da2b26f..da2b26f 100644 --- a/arch/arm/cpu/armv7/imx-common/i2c.c +++ b/arch/arm/imx-common/i2c-mxv7.c diff --git a/arch/arm/cpu/armv7/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index da093fb..da093fb 100644 --- a/arch/arm/cpu/armv7/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c diff --git a/arch/arm/cpu/armv7/imx-common/speed.c b/arch/arm/imx-common/speed.c index 80989c4..80989c4 100644 --- a/arch/arm/cpu/armv7/imx-common/speed.c +++ b/arch/arm/imx-common/speed.c diff --git a/arch/arm/cpu/armv7/imx-common/timer.c b/arch/arm/imx-common/timer.c index e2725e1..e2725e1 100644 --- a/arch/arm/cpu/armv7/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h index c79bed7..113f258 100644 --- a/arch/arm/include/asm/arch-kirkwood/spi.h +++ b/arch/arm/include/asm/arch-kirkwood/spi.h @@ -49,6 +49,7 @@ struct kwspi_registers { #define MISO_MPP11 (1 << 2) #define KWSPI_CLKPRESCL_MASK 0x1f +#define KWSPI_CLKPRESCL_MIN 0x12 #define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ #define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ #define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h index 0f47eaf..a313b80 100644 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ b/arch/arm/include/asm/arch-mx25/clock.h @@ -26,6 +26,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include <common.h> + +#ifdef CONFIG_MX25_HCLK_FREQ +#define MXC_HCLK CONFIG_MX25_HCLK_FREQ +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_MX25_CLK32 +#define MXC_CLK32 CONFIG_MX25_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_CSI_CLK, MXC_EPIT_CLK, diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 852c19c..9468b45 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -24,6 +24,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include <common.h> + +#ifdef CONFIG_MX31_HCLK_FREQ +#define MXC_HCLK CONFIG_MX31_HCLK_FREQ +#else +#define MXC_HCLK 26000000 +#endif + +#ifdef CONFIG_MX31_CLK32 +#define MXC_CLK32 CONFIG_MX31_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_ARM_CLK, MXC_IPG_CLK, diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h index e94f124..eb7458a 100644 --- a/arch/arm/include/asm/arch-mx35/clock.h +++ b/arch/arm/include/asm/arch-mx35/clock.h @@ -24,6 +24,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include <common.h> + +#ifdef CONFIG_MX35_HCLK_FREQ +#define MXC_HCLK CONFIG_MX35_HCLK_FREQ +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_MX35_CLK32 +#define MXC_CLK32 CONFIG_MX35_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_ARM_CLK, MXC_AHB_CLK, diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h index 7a2d1bb..3fcde0b 100644 --- a/arch/arm/include/asm/arch-mx35/crm_regs.h +++ b/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -32,8 +32,8 @@ #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) #define MXC_CCM_CCMR_ROMW_OFFSET 18 #define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) -#define MXC_CCM_CCMR_RAMW_OFFSET 21 -#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) +#define MXC_CCM_CCMR_RAMW_OFFSET 16 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) #define MXC_CCM_CCMR_LPM_OFFSET 14 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) #define MXC_CCM_CCMR_UPE (1 << 9) @@ -47,7 +47,7 @@ #define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) #define MXC_CCM_PDR0_CKIL_SEL (1 << 15) #define MXC_CCM_PDR0_PER_PODF_OFFSET 12 -#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) +#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) #define MXC_CCM_PDR0_AUTO_CON 0x1 @@ -62,10 +62,8 @@ #define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 #define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) -#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 -#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) #define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 -#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 #define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) #define MXC_CCM_PDR2_CSI_M_U (1 << 7) @@ -78,35 +76,23 @@ #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 #define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) #define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) -#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 -#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 -#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) -#define MXC_CCM_PDR3_UART_M_U (1 << 15) -#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 -#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 14) #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 -#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) #define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) -#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 -#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 -#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) #define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 #define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) -#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 -#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) #define MXC_CCM_PDR4_USB_PODF_OFFSET 22 -#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) -#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 -#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) #define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 -#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) -#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 -#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR4_UART_PODF_OFFSET 10 -#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) +#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) #define MXC_CCM_PDR4_USB_M_U (1 << 9) /* Bit definitions for RCSR */ @@ -144,6 +130,12 @@ #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) /* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR_CG_MASK 0x3 +#define MXC_CCM_CGR_CG_OFF 0x0 +#define MXC_CCM_CGR_CG_RUN_ON 0x1 +#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 +#define MXC_CCM_CGR_CG_ON 0x3 + #define MXC_CCM_CGR0_ASRC_OFFSET 0 #define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) #define MXC_CCM_CGR0_ATA_OFFSET 2 @@ -251,10 +243,8 @@ #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 #define MXC_CCM_COSR_CLKOEN (1 << 5) #define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) -#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) -#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 -#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) -#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 +#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) +#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index a1255f9..d23abd7 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -34,21 +34,21 @@ #define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) #define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19) #define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15) #define IOMUXC_GPR13_SATA_SPEED_3G (1<<15) @@ -63,55 +63,55 @@ #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11) #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2) #define IOMUXC_GPR13_SATA_PHY_1_FAST 0 #define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1 diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index a830c43..54add4b 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -142,7 +142,6 @@ struct venc_regs { }; /* Few Register Offsets */ -#define FRAME_MODE_SHIFT 1 #define TFTSTN_SHIFT 3 #define DATALINES_SHIFT 8 @@ -182,6 +181,16 @@ struct panel_config { void *frame_buffer; }; +#define DSS_HBP(bp) (((bp) - 1) << 20) +#define DSS_HFP(fp) (((fp) - 1) << 8) +#define DSS_HSW(sw) ((sw) - 1) +#define DSS_VBP(bp) ((bp) << 20) +#define DSS_VFP(fp) ((fp) << 8) +#define DSS_VSW(sw) ((sw) - 1) + +#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw)) +#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw)) + /* Generic DSS Functions */ void omap3_dss_venc_config(const struct venc_regs *venc_cfg, u32 height, u32 width); diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 71f183d..6e92b23 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -451,6 +451,11 @@ #define CONTROL_PADCONF_GPIO128 0x0A58 #define CONTROL_PADCONF_GPIO129 0x0A5A +/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration + * of the extended drain cells */ +#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C) +#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6) + #define MUX_VAL(OFFSET,VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); diff --git a/arch/arm/include/asm/arch-tegra20/ap20.h b/arch/arm/include/asm/arch-tegra20/ap20.h index c84d22f..70d94c5 100644 --- a/arch/arm/include/asm/arch-tegra20/ap20.h +++ b/arch/arm/include/asm/arch-tegra20/ap20.h @@ -95,9 +95,6 @@ #define HALT_COP_EVENT_IRQ_1 (1 << 11) #define HALT_COP_EVENT_FIQ_1 (1 << 9) -/* Start up the tegra20 SOC */ -void tegra20_start(void); - /* This is the main entry into U-Boot, used by the Cortex-A9 */ extern void _start(void); diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h index 258f7b6..bd511db 100644 --- a/arch/arm/include/asm/arch-tegra20/funcmux.h +++ b/arch/arm/include/asm/arch-tegra20/funcmux.h @@ -57,6 +57,9 @@ enum { /* Serial Flash configs */ FUNCMUX_SPI1_GMC_GMD = 0, + + /* NAND flags */ + FUNCMUX_NDFLASH_ATC = 0, }; /** diff --git a/arch/arm/include/asm/arch-tegra20/mmc.h b/arch/arm/include/asm/arch-tegra20/mmc.h index 916a353..5c95047 100644 --- a/arch/arm/include/asm/arch-tegra20/mmc.h +++ b/arch/arm/include/asm/arch-tegra20/mmc.h @@ -19,9 +19,9 @@ * MA 02111-1307 USA */ -#ifndef _TEGRA20_MMC_H_ -#define _TEGRA20_MMC_H_ +#ifndef _TEGRA_MMC_H_ +#define _TEGRA_MMC_H_ -int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); +int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); -#endif /* TEGRA20_MMC_H_ */ +#endif /* _TEGRA_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/sys_proto.h b/arch/arm/include/asm/arch-tegra20/sys_proto.h index 643d542..919aec7 100644 --- a/arch/arm/include/asm/arch-tegra20/sys_proto.h +++ b/arch/arm/include/asm/arch-tegra20/sys_proto.h @@ -24,12 +24,12 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -struct tegra20_sysinfo { +struct tegra_sysinfo { char *board_string; }; void invalidate_dcache(void); -extern const struct tegra20_sysinfo sysinfo; +extern const struct tegra_sysinfo sysinfo; #endif diff --git a/arch/arm/include/asm/arch-tegra20/tegra20.h b/arch/arm/include/asm/arch-tegra20/tegra20.h index 6750754..c9485a1 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra20.h +++ b/arch/arm/include/asm/arch-tegra20/tegra20.h @@ -33,21 +33,22 @@ #define NV_PA_GPIO_BASE 0x6000D000 #define NV_PA_EVP_BASE 0x6000F000 #define NV_PA_APB_MISC_BASE 0x70000000 -#define TEGRA20_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) +#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) #define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) -#define TEGRA20_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) -#define TEGRA20_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) -#define TEGRA20_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) +#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) +#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) +#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) +#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) #define NV_PA_CSITE_BASE 0x70040000 #define TEGRA_USB1_BASE 0xC5000000 #define TEGRA_USB3_BASE 0xC5008000 #define TEGRA_USB_ADDR_MASK 0xFFFFC000 -#define TEGRA20_SDRC_CS0 NV_PA_SDRAM_BASE +#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE #define LOW_LEVEL_SRAM_STACK 0x4000FFFC #define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) #define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) @@ -85,7 +86,7 @@ enum { }; #else /* __ASSEMBLY__ */ -#define PRM_RSTCTRL TEGRA20_PMC_BASE +#define PRM_RSTCTRL NV_PA_PMC_BASE #endif #endif /* TEGRA20_H */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra_mmc.h b/arch/arm/include/asm/arch-tegra20/tegra_mmc.h new file mode 100644 index 0000000..dd746ca --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/tegra_mmc.h @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * Portions Copyright (C) 2011-2012 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __TEGRA_MMC_H_ +#define __TEGRA_MMC_H_ + +#define TEGRA_SDMMC1_BASE 0xC8000000 +#define TEGRA_SDMMC2_BASE 0xC8000200 +#define TEGRA_SDMMC3_BASE 0xC8000400 +#define TEGRA_SDMMC4_BASE 0xC8000600 + +#ifndef __ASSEMBLY__ +struct tegra_mmc { + unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ + unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ + unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ + unsigned int argument; /* _ARGUMENT_0 */ + unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ + unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ + unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ + unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ + unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ + unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ + unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ + unsigned int prnsts; /* _PRESENT_STATE_0 */ + unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ + unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ + unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ + unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ + unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ + unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ + unsigned char swrst; /* _SW_RESET_ 31:24 */ + unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ + unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ + unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ + unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ + unsigned char res1[2]; /* _RESERVED 31:16 */ + unsigned int capareg; /* _CAPABILITIES_0 */ + unsigned char res2[4]; /* RESERVED, offset 44h-47h */ + unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ + unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ + unsigned short setacmd12err; /* offset 50h */ + unsigned short setinterr; /* offset 52h */ + unsigned char admaerr; /* offset 54h */ + unsigned char res4[3]; /* RESERVED, offset 55h-57h */ + unsigned long admaaddr; /* offset 58h-5Fh */ + unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ + unsigned short slotintstatus; /* offset FCh */ + unsigned short hcver; /* HOST Version */ + unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */ +}; + +#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) + +#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) +#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) +#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) +#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) +#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) + +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) + +#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) +#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) +#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) + +#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) +#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) + +#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) +#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) +#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) + +#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 +#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) + +#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) + +#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) +#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) +#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) +#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) +#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) + +#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) +#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) +#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) +#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) +#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) + +#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) + +struct mmc_host { + struct tegra_mmc *reg; + unsigned int version; /* SDHCI spec. version */ + unsigned int clock; /* Current clock (MHz) */ + unsigned int base; /* Base address, SDMMC1/2/3/4 */ + enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ + int pwr_gpio; /* Power GPIO */ + int cd_gpio; /* Change Detect GPIO */ +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __TEGRA_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra_spi.h b/arch/arm/include/asm/arch-tegra20/tegra_spi.h index 8978bea..d53a93f 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra_spi.h +++ b/arch/arm/include/asm/arch-tegra20/tegra_spi.h @@ -70,6 +70,6 @@ struct spi_tegra { #define SPI_STAT_CUR_BLKCNT (1 << 15) #define SPI_TIMEOUT 1000 -#define TEGRA20_SPI_MAX_FREQ 52000000 +#define TEGRA_SPI_MAX_FREQ 52000000 #endif /* _TEGRA_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/timer.h b/arch/arm/include/asm/arch-tegra20/timer.h index 43f7ab4..fdb99a7 100644 --- a/arch/arm/include/asm/arch-tegra20/timer.h +++ b/arch/arm/include/asm/arch-tegra20/timer.h @@ -21,8 +21,8 @@ /* Tegra20 timer functions */ -#ifndef _TEGRA20_TIMER_H -#define _TEGRA20_TIMER_H +#ifndef _TEGRA_TIMER_H +#define _TEGRA_TIMER_H /* returns the current monotonic timer value in microseconds */ unsigned long timer_get_us(void); diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index f1951e8..109a1ac 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -241,6 +241,9 @@ init_fnc_t *init_sequence[] = { fdtdec_check_fdt, #endif timer_init, /* initialize timer */ +#ifdef CONFIG_BOARD_POSTCLK_INIT + board_postclk_init, +#endif #ifdef CONFIG_FSL_ESDHC get_clocks, #endif |