diff options
Diffstat (limited to 'arch/arm/mach-uniphier')
79 files changed, 4720 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig new file mode 100644 index 0000000..8335685 --- /dev/null +++ b/arch/arm/mach-uniphier/Kconfig @@ -0,0 +1,89 @@ +menu "Panasonic UniPhier platform" + depends on ARCH_UNIPHIER + +config SYS_SOC + default "uniphier" + +config SYS_CONFIG_NAME + default "uniphier" + +config UNIPHIER_SMP + bool + +choice + prompt "UniPhier SoC select" + +config MACH_PH1_PRO4 + bool "PH1-Pro4" + select UNIPHIER_SMP + +config MACH_PH1_LD4 + bool "PH1-LD4" + +config MACH_PH1_SLD8 + bool "PH1-sLD8" + +endchoice + +choice + prompt "UniPhier Support Card select" + optional + +config PFC_MICRO_SUPPORT_CARD + bool "Support card with PFC CPLD" + help + This option provides support for the expansion board with PFC + original address mapping. + + Say Y to use the on-board UART, Ether, LED devices. + +config DCC_MICRO_SUPPORT_CARD + bool "Support card with DCC CPLD" + help + This option provides support for the expansion board with DCC- + arranged address mapping that is compatible with legacy UniPhier + reference boards. + + Say Y to use the on-board UART, Ether, LED devices. + +endchoice + +config SYS_MALLOC_F + default y + +config SYS_MALLOC_F_LEN + default 0x400 + +config CMD_PINMON + bool "Enable boot mode pins monitor command" + default y + help + The command "pinmon" shows the state of the boot mode pins. + The boot mode pins are latched when the system reset is deasserted + and determine which device the system should load a boot image from. + +config CMD_DDRPHY_DUMP + bool "Enable dump command of DDR PHY parameters" + help + The command "ddrphy" shows the resulting parameters of DDR PHY + training; it is useful for the evaluation of DDR PHY training. + +choice + prompt "DDR3 Frequency select" + +config DDR_FREQ_1600 + bool "DDR3 1600" + depends on MACH_PH1_PRO4 || MACH_PH1_LD4 + +config DDR_FREQ_1333 + bool "DDR3 1333" + depends on MACH_PH1_LD4 || MACH_PH1_SLD8 + +endchoice + +config DDR_FREQ + int + default 1333 if DDR_FREQ_1333 + default 1600 if DDR_FREQ_1600 + +endmenu diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile new file mode 100644 index 0000000..e7a801b --- /dev/null +++ b/arch/arm/mach-uniphier/Makefile @@ -0,0 +1,37 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD + +obj-y += lowlevel_init.o +obj-y += init_page_table.o +obj-y += spl.o +obj-y += memconf.o +obj-y += ddrphy_training.o + +else + +obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o +obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o +obj-y += dram_init.o +obj-y += board_common.o +obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o +obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o +obj-y += reset.o +obj-y += cache_uniphier.o +obj-$(CONFIG_UNIPHIER_SMP) += smp.o +obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o +obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o + +endif + +obj-y += timer.o + +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o + +obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/ +obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/ +obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/ diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c new file mode 100644 index 0000000..5f2d5f6 --- /dev/null +++ b/arch/arm/mach-uniphier/board_common.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mach/led.h> + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + led_write(U, B, O, O); + + return 0; +} + +#if CONFIG_NR_DRAM_BANKS >= 2 +void dram_init_banksize(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE; + gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE; + gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE; +} +#endif diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c new file mode 100644 index 0000000..7108740 --- /dev/null +++ b/arch/arm/mach-uniphier/board_early_init_f.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2012-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/led.h> +#include <mach/board.h> + +void pin_init(void); +void clkrst_init(void); + +int board_early_init_f(void) +{ + led_write(U, 0, , ); + + pin_init(); + + led_write(U, 1, , ); + + clkrst_init(); + + led_write(U, 2, , ); + + return 0; +} diff --git a/arch/arm/mach-uniphier/board_early_init_r.c b/arch/arm/mach-uniphier/board_early_init_r.c new file mode 100644 index 0000000..579fe70 --- /dev/null +++ b/arch/arm/mach-uniphier/board_early_init_r.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mach/board.h> + +int board_early_init_r(void) +{ + uniphier_board_late_init(); + return 0; +} diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c new file mode 100644 index 0000000..0622a1e --- /dev/null +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <nand.h> +#include <asm/io.h> +#include <../drivers/mtd/nand/denali.h> + +static void nand_denali_wp_disable(void) +{ +#ifdef CONFIG_NAND_DENALI + /* + * Since the boot rom enables the write protection for NAND boot mode, + * it must be disabled somewhere for "nand write", "nand erase", etc. + * The workaround is here to not disturb the Denali NAND controller + * driver just for a really SoC-specific thing. + */ + void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + + writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT); +#endif +} + +int board_late_init(void) +{ + puts("MODE: "); + + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: + printf("eMMC Boot\n"); + setenv("bootmode", "emmcboot"); + break; + case BOOT_DEVICE_NAND: + printf("NAND Boot\n"); + setenv("bootmode", "nandboot"); + nand_denali_wp_disable(); + break; + case BOOT_DEVICE_NOR: + printf("NOR Boot\n"); + setenv("bootmode", "norboot"); + break; + default: + printf("Unsupported Boot Mode\n"); + return -1; + } + + return 0; +} diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c new file mode 100644 index 0000000..52f3c7c --- /dev/null +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/armv7.h> +#include <mach/ssc-regs.h> + +#ifdef CONFIG_UNIPHIER_L2CACHE_ON +static void uniphier_cache_maint_all(u32 operation) +{ + /* try until the command is successfully set */ + do { + writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM); + } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE)); + + /* wait until the operation is completed */ + while (readl(SSCOLPQS) != SSCOLPQS_EF) + ; + + /* clear the complete notification flag */ + writel(SSCOLPQS_EF, SSCOLPQS); + + writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ + readl(SSCOPE); /* need a read back to confirm */ +} + +void v7_outer_cache_flush_all(void) +{ + uniphier_cache_maint_all(SSCOQM_CM_WB_INV); +} + +void v7_outer_cache_inval_all(void) +{ + uniphier_cache_maint_all(SSCOQM_CM_INV); +} + +static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation) +{ + /* try until the command is successfully set */ + do { + writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM); + writel(start, SSCOQAD); + writel(size, SSCOQSZ); + + } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE)); + + /* wait until the operation is completed */ + while (readl(SSCOLPQS) != SSCOLPQS_EF) + ; + + /* clear the complete notification flag */ + writel(SSCOLPQS_EF, SSCOLPQS); +} + +static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) +{ + u32 size; + + /* + * If start address is not aligned to cache-line, + * do cache operation for the first cache-line + */ + start = start & ~(SSC_LINE_SIZE - 1); + + if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) { + /* this means cache operation for all range */ + uniphier_cache_maint_all(operation); + return; + } + + /* + * If end address is not aligned to cache-line, + * do cache operation for the last cache-line + */ + size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1); + + while (size) { + u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ? + SSC_RANGE_OP_MAX_SIZE : size; + __uniphier_cache_maint_range(start, chunk_size, operation); + + start += chunk_size; + size -= chunk_size; + } + + writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ + readl(SSCOPE); /* need a read back to confirm */ +} + +void v7_outer_cache_flush_range(u32 start, u32 end) +{ + uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV); +} + +void v7_outer_cache_inval_range(u32 start, u32 end) +{ + uniphier_cache_maint_range(start, end, SSCOQM_CM_INV); +} + +void v7_outer_cache_enable(void) +{ + u32 tmp; + tmp = readl(SSCC); + tmp |= SSCC_ON; + writel(tmp, SSCC); +} +#endif + +void v7_outer_cache_disable(void) +{ + u32 tmp; + tmp = readl(SSCC); + tmp &= ~SSCC_ON; + writel(tmp, SSCC); +} + +void wakeup_secondary(void); + +void enable_caches(void) +{ + uint32_t reg; + +#ifdef CONFIG_UNIPHIER_SMP + /* + * The secondary CPU must move to DDR, + * before L2 disable. + * On SPL, the Page Table is located on the L2. + */ + wakeup_secondary(); +#endif + /* + * UniPhier SoCs must use L2 cache for init stack pointer. + * We disable L2 and L1 in this order. + * If CONFIG_SYS_DCACHE_OFF is not defined, + * caches are enabled again with a new page table. + */ + + /* L2 disable */ + v7_outer_cache_disable(); + + /* L1 disable */ + reg = get_cr(); + reg &= ~(CR_C | CR_M); + set_cr(reg); + +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} diff --git a/arch/arm/mach-uniphier/cmd_ddrphy.c b/arch/arm/mach-uniphier/cmd_ddrphy.c new file mode 100644 index 0000000..5f44927 --- /dev/null +++ b/arch/arm/mach-uniphier/cmd_ddrphy.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/ddrphy-regs.h> + +/* Select either decimal or hexadecimal */ +#if 1 +#define PRINTF_FORMAT "%2d" +#else +#define PRINTF_FORMAT "%02x" +#endif +/* field separator */ +#define FS " " + +static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index) +{ + return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f; +} + +static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *)) +{ + int ch, p, dx; + struct ddrphy __iomem *phy; + + for (ch = 0; ch < NR_DDRCH; ch++) { + for (p = 0; p < NR_DDRPHY_PER_CH; p++) { + phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p); + + for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + printf("CH%dP%dDX%d:", ch, p, dx); + (*callback)(&phy->dx[dx]); + printf("\n"); + } + } + } +} + +static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx) +{ + int i; + + for (i = 0; i < 10; i++) + printf(FS PRINTF_FORMAT, read_bdl(dx, i)); + + printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff); +} + +void wbdl_dump(void) +{ + printf("\n--- Write Bit Delay Line ---\n"); + printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n"); + + dump_loop(&__wbdl_dump); +} + +static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx) +{ + int i; + + for (i = 15; i < 24; i++) + printf(FS PRINTF_FORMAT, read_bdl(dx, i)); + + printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff); +} + +void rbdl_dump(void) +{ + printf("\n--- Read Bit Delay Line ---\n"); + printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n"); + + dump_loop(&__rbdl_dump); +} + +static void __wld_dump(struct ddrphy_datx8 __iomem *dx) +{ + int rank; + u32 lcdlr0 = readl(&dx->lcdlr[0]); + u32 gtr = readl(&dx->gtr); + + for (rank = 0; rank < 4; rank++) { + u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ + u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ + + printf(FS PRINTF_FORMAT "%sT", wld, + wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1"); + } +} + +void wld_dump(void) +{ + printf("\n--- Write Leveling Delay ---\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); + + dump_loop(&__wld_dump); +} + +static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx) +{ + int rank; + u32 lcdlr2 = readl(&dx->lcdlr[2]); + u32 gtr = readl(&dx->gtr); + + for (rank = 0; rank < 4; rank++) { + u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ + u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ + + printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl); + } +} + +void dqsgd_dump(void) +{ + printf("\n--- DQS Gating Delay ---\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); + + dump_loop(&__dqsgd_dump); +} + +static void __mdl_dump(struct ddrphy_datx8 __iomem *dx) +{ + int i; + u32 mdl = readl(&dx->mdlr); + for (i = 0; i < 3; i++) + printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff); +} + +void mdl_dump(void) +{ + printf("\n--- Master Delay Line ---\n"); + printf(" IPRD TPRD MDLD\n"); + + dump_loop(&__mdl_dump); +} + +#define REG_DUMP(x) \ + { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \ + p - (u32 *)phy, #x, p, readl(p)); } + +void reg_dump(void) +{ + int ch, p; + struct ddrphy __iomem *phy; + + printf("\n--- DDR PHY registers ---\n"); + + for (ch = 0; ch < NR_DDRCH; ch++) { + for (p = 0; p < NR_DDRPHY_PER_CH; p++) { + printf("== Ch%d, PHY%d ==\n", ch, p); + printf(" No: Name : Address : Data\n"); + + phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p); + + REG_DUMP(ridr); + REG_DUMP(pir); + REG_DUMP(pgcr[0]); + REG_DUMP(pgcr[1]); + REG_DUMP(pgsr[0]); + REG_DUMP(pgsr[1]); + REG_DUMP(pllcr); + REG_DUMP(ptr[0]); + REG_DUMP(ptr[1]); + REG_DUMP(ptr[2]); + REG_DUMP(ptr[3]); + REG_DUMP(ptr[4]); + REG_DUMP(acmdlr); + REG_DUMP(acbdlr); + REG_DUMP(dxccr); + REG_DUMP(dsgcr); + REG_DUMP(dcr); + REG_DUMP(dtpr[0]); + REG_DUMP(dtpr[1]); + REG_DUMP(dtpr[2]); + REG_DUMP(mr0); + REG_DUMP(mr1); + REG_DUMP(mr2); + REG_DUMP(mr3); + REG_DUMP(dx[0].gcr); + REG_DUMP(dx[0].gtr); + REG_DUMP(dx[1].gcr); + REG_DUMP(dx[1].gtr); + } + } +} + +static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *cmd = argv[1]; + + if (argc == 1) + cmd = "all"; + + if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all")) + wbdl_dump(); + + if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all")) + rbdl_dump(); + + if (!strcmp(cmd, "wld") || !strcmp(cmd, "all")) + wld_dump(); + + if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all")) + dqsgd_dump(); + + if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all")) + mdl_dump(); + + if (!strcmp(cmd, "reg") || !strcmp(cmd, "all")) + reg_dump(); + + return 0; +} + +U_BOOT_CMD( + ddr, 2, 1, do_ddr, + "UniPhier DDR PHY parameters dumper", + "- dump all of the followings\n" + "ddr wbdl - dump Write Bit Delay\n" + "ddr rbdl - dump Read Bit Delay\n" + "ddr wld - dump Write Leveling\n" + "ddr dqsgd - dump DQS Gating Delay\n" + "ddr mdl - dump Master Delay Line\n" + "ddr reg - dump registers\n" +); diff --git a/arch/arm/mach-uniphier/cmd_pinmon.c b/arch/arm/mach-uniphier/cmd_pinmon.c new file mode 100644 index 0000000..8be2ed4 --- /dev/null +++ b/arch/arm/mach-uniphier/cmd_pinmon.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mach/boot-device.h> +#include <mach/sbc-regs.h> + +static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int mode_sel, i; + + printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF"); + + mode_sel = get_boot_mode_sel(); + + puts("Boot Mode Pin:\n"); + + for (i = 0; boot_device_table[i].info; i++) + printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, + boot_device_table[i].info); + + return 0; +} + +U_BOOT_CMD( + pinmon, 1, 1, do_pinmon, + "pin monitor", + "" +); diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c new file mode 100644 index 0000000..13a0b1e --- /dev/null +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sg-regs.h> + +int print_cpuinfo(void) +{ + u32 revision, type, model, rev, required_model = 1, required_rev = 1; + + revision = readl(SG_REVISION); + type = (revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT; + model = (revision & SG_REVISION_MODEL_MASK) >> SG_REVISION_MODEL_SHIFT; + rev = (revision & SG_REVISION_REV_MASK) >> SG_REVISION_REV_SHIFT; + + puts("CPU: "); + + switch (type) { + case 0x25: + puts("PH1-sLD3 (MN2WS0220)"); + required_model = 2; + break; + case 0x26: + puts("PH1-LD4 (MN2WS0250)"); + required_rev = 2; + break; + case 0x28: + puts("PH1-Pro4 (MN2WS0230)"); + break; + case 0x29: + puts("PH1-sLD8 (MN2WS0270)"); + break; + default: + printf("Unknown Processor ID (0x%x)\n", revision); + return -1; + } + + if (model > 1) + printf(" model %d", model); + + printf(" (rev. %d)\n", rev); + + if (model < required_model) { + printf("Sorry, this model is not supported.\n"); + printf("Required model is %d.", required_model); + return -1; + } else if (rev < required_rev) { + printf("Sorry, this revision is not supported.\n"); + printf("Required revision is %d.", required_rev); + return -1; + } + + return 0; +} diff --git a/arch/arm/mach-uniphier/ddrphy_training.c b/arch/arm/mach-uniphier/ddrphy_training.c new file mode 100644 index 0000000..b1d46cf --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy_training.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/ddrphy-regs.h> + +void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) +{ + int dx; + u32 __iomem tmp, *p; + + for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + p = &phy->dx[dx].gcr; + + tmp = readl(p); + /* Specify the rank that should be write leveled */ + tmp &= ~DXGCR_WLRKEN_MASK; + tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK; + writel(tmp, p); + } + + p = &phy->dtcr; + + tmp = readl(p); + /* Specify the rank used during data bit deskew and eye centering */ + tmp &= ~DTCR_DTRANK_MASK; + tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK; + /* Use Multi-Purpose Register for DQS gate training */ + tmp |= DTCR_DTMPR; + /* Specify the rank enabled for data-training */ + tmp &= ~DTCR_RNKEN_MASK; + tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK; + writel(tmp, p); +} + +struct ddrphy_init_sequence { + char *description; + u32 init_flag; + u32 done_flag; + u32 err_flag; +}; + +static struct ddrphy_init_sequence init_sequence[] = { + { + "DRAM Initialization", + PIR_DRAMRST | PIR_DRAMINIT, + PGSR0_DIDONE, + PGSR0_DIERR + }, + { + "Write Leveling", + PIR_WL, + PGSR0_WLDONE, + PGSR0_WLERR + }, + { + "Read DQS Gate Training", + PIR_QSGATE, + PGSR0_QSGDONE, + PGSR0_QSGERR + }, + { + "Write Leveling Adjustment", + PIR_WLADJ, + PGSR0_WLADONE, + PGSR0_WLAERR + }, + { + "Read Bit Deskew", + PIR_RDDSKW, + PGSR0_RDDONE, + PGSR0_RDERR + }, + { + "Write Bit Deskew", + PIR_WRDSKW, + PGSR0_WDDONE, + PGSR0_WDERR + }, + { + "Read Eye Training", + PIR_RDEYE, + PGSR0_REDONE, + PGSR0_REERR + }, + { + "Write Eye Training", + PIR_WREYE, + PGSR0_WEDONE, + PGSR0_WEERR + } +}; + +int ddrphy_training(struct ddrphy __iomem *phy) +{ + int i; + u32 pgsr0; + u32 init_flag = PIR_INIT; + u32 done_flag = PGSR0_IDONE; + int timeout = 50000; /* 50 msec is long enough */ +#ifdef DISPLAY_ELAPSED_TIME + ulong start = get_timer(0); +#endif + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + init_flag |= init_sequence[i].init_flag; + done_flag |= init_sequence[i].done_flag; + } + + writel(init_flag, &phy->pir); + + do { + if (--timeout < 0) { +#ifndef CONFIG_SPL_BUILD + printf("%s: error: timeout during DDR training\n", + __func__); +#endif + return -1; + } + udelay(1); + pgsr0 = readl(&phy->pgsr[0]); + } while ((pgsr0 & done_flag) != done_flag); + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + if (pgsr0 & init_sequence[i].err_flag) { +#ifndef CONFIG_SPL_BUILD + printf("%s: error: %s failed\n", __func__, + init_sequence[i].description); +#endif + return -1; + } + } + +#ifdef DISPLAY_ELAPSED_TIME + printf("%s: info: elapsed time %ld msec\n", get_timer(start)); +#endif + + return 0; +} diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c new file mode 100644 index 0000000..4b8c938 --- /dev/null +++ b/arch/arm/mach-uniphier/dram_init.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} diff --git a/arch/arm/mach-uniphier/include/mach/arm-mpcore.h b/arch/arm/mach-uniphier/include/mach/arm-mpcore.h new file mode 100644 index 0000000..cf7cd46 --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/arm-mpcore.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_ARM_MPCORE_H +#define ARCH_ARM_MPCORE_H + +/* Snoop Control Unit */ +#define SCU_OFFSET 0x00 + +/* SCU Control Register */ +#define SCU_CTRL 0x00 +/* SCU Configuration Register */ +#define SCU_CONF 0x04 +/* SCU CPU Power Status Register */ +#define SCU_PWR_STATUS 0x08 +/* SCU Invalidate All Registers in Secure State */ +#define SCU_INV_ALL 0x0C +/* SCU Filtering Start Address Register */ +#define SCU_FILTER_START 0x40 +/* SCU Filtering End Address Register */ +#define SCU_FILTER_END 0x44 +/* SCU Access Control Register */ +#define SCU_SAC 0x50 +/* SCU Non-secure Access Control Register */ +#define SCU_SNSAC 0x54 + +/* Global Timer */ +#define GLOBAL_TIMER_OFFSET 0x200 + +/* Global Timer Counter Registers */ +#define GTIMER_CNT_L 0x00 +#define GTIMER_CNT_H 0x04 +/* Global Timer Control Register */ +#define GTIMER_CTRL 0x08 +/* Global Timer Interrupt Status Register */ +#define GTIMER_STAT 0x0C +/* Comparator Value Registers */ +#define GTIMER_CMP_L 0x10 +#define GTIMER_CMP_H 0x14 +/* Auto-increment Register */ +#define GTIMER_INC 0x18 + +#endif /* ARCH_ARM_MPCORE_H */ diff --git a/arch/arm/mach-uniphier/include/mach/bcu-regs.h b/arch/arm/mach-uniphier/include/mach/bcu-regs.h new file mode 100644 index 0000000..0dfd94e --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/bcu-regs.h @@ -0,0 +1,30 @@ +/* + * UniPhier BCU (Bus Control Unit) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_BCU_REGS_H +#define ARCH_BCU_REGS_H + +#define BCU_BASE 0x50080000 + +#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4) +#define BCSCR0 (BCSCR(0)) +#define BCSCR1 (BCSCR(1)) +#define BCSCR2 (BCSCR(2)) +#define BCSCR3 (BCSCR(3)) +#define BCSCR4 (BCSCR(4)) +#define BCSCR5 (BCSCR(5)) + +#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4) +#define BCIPPCCHR0 (BCIPPCCHR(0)) +#define BCIPPCCHR1 (BCIPPCCHR(1)) +#define BCIPPCCHR2 (BCIPPCCHR(2)) +#define BCIPPCCHR3 (BCIPPCCHR(3)) +#define BCIPPCCHR4 (BCIPPCCHR(4)) +#define BCIPPCCHR5 (BCIPPCCHR(5)) + +#endif /* ARCH_BCU_REGS_H */ diff --git a/arch/arm/mach-uniphier/include/mach/board.h b/arch/arm/mach-uniphier/include/mach/board.h new file mode 100644 index 0000000..e3cba5b --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/board.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_BOARD_H +#define ARCH_BOARD_H + +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \ + defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +void support_card_reset(void); +void support_card_init(void); +void support_card_late_init(void); +int check_support_card(void); +#else +#define support_card_reset() do {} while (0) +#define support_card_init() do {} while (0) +#define support_card_late_init() do {} while (0) +static inline int check_support_card(void) +{ + return 0; +} +#endif + +static inline void uniphier_board_reset(void) +{ + support_card_reset(); +} + +static inline void uniphier_board_init(void) +{ + support_card_init(); +} + +static inline void uniphier_board_late_init(void) +{ + support_card_late_init(); +} + +#endif /* ARCH_BOARD_H */ diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/include/mach/boot-device.h new file mode 100644 index 0000000..7a10f1c --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/boot-device.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_BOOT_DEVICE_H_ +#define _ASM_BOOT_DEVICE_H_ + +int get_boot_mode_sel(void); + +struct boot_device_info { + u32 type; + char *info; +}; + +extern struct boot_device_info boot_device_table[]; + +#endif /* _ASM_BOOT_DEVICE_H_ */ diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h new file mode 100644 index 0000000..6b7d600 --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -0,0 +1,172 @@ +/* + * UniPhier DDR PHY registers + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_DDRPHY_REGS_H +#define ARCH_DDRPHY_REGS_H + +#include <linux/compiler.h> + +#ifndef __ASSEMBLY__ + +struct ddrphy { + u32 ridr; /* Revision Identification Register */ + u32 pir; /* PHY Initialixation Register */ + u32 pgcr[2]; /* PHY General Configuration Register */ + u32 pgsr[2]; /* PHY General Status Register */ + u32 pllcr; /* PLL Control Register */ + u32 ptr[5]; /* PHY Timing Register */ + u32 acmdlr; /* AC Master Delay Line Register */ + u32 acbdlr; /* AC Bit Delay Line Register */ + u32 aciocr; /* AC I/O Configuration Register */ + u32 dxccr; /* DATX8 Common Configuration Register */ + u32 dsgcr; /* DDR System General Configuration Register */ + u32 dcr; /* DRAM Configuration Register */ + u32 dtpr[3]; /* DRAM Timing Parameters Register */ + u32 mr0; /* Mode Register 0 */ + u32 mr1; /* Mode Register 1 */ + u32 mr2; /* Mode Register 2 */ + u32 mr3; /* Mode Register 3 */ + u32 odtcr; /* ODT Configuration Register */ + u32 dtcr; /* Data Training Configuration Register */ + u32 dtar[4]; /* Data Training Address Register */ + u32 dtdr[2]; /* Data Training Data Register */ + u32 dtedr[2]; /* Data Training Eye Data Register */ + u32 rsv0[13]; /* Reserved */ + u32 dcuar; /* DCU Address Register */ + u32 dcudr; /* DCU Data Register */ + u32 dcurr; /* DCU Run Register */ + u32 dculr; /* DCU Loop Register */ + u32 dcugcr; /* DCU General Configuration Register */ + u32 dcutpr; /* DCU Timing Parameters Register */ + u32 dcusr[2]; /* DCU Status Register */ + u32 rsv1[8]; /* Reserved */ + u32 bistrr; /* BIST Run Register */ + u32 bistwcr; /* BIST Word Count Register */ + u32 bistmskr[3]; /* BIST Mask Register */ + u32 bistlsr; /* BIST LFSR Sed Register */ + u32 bistar[3]; /* BIST Address Register */ + u32 bistudpr; /* BIST User Data Pattern Register */ + u32 bistgsr; /* BIST General Status Register */ + u32 bistwer; /* BIST Word Error Register */ + u32 bistber[4]; /* BIST Bit Error Register */ + u32 bistwcsr; /* BIST Word Count Status Register */ + u32 bistfwr[3]; /* BIST Fail Word Register */ + u32 rsv2[10]; /* Reserved */ + u32 gpr[2]; /* General Purpose Register */ + struct ddrphy_zq { /* ZQ */ + u32 cr[2]; /* Impedance Control Register */ + u32 sr[2]; /* Impedance Status Register */ + } zq[4]; + struct ddrphy_datx8 { /* DATX8 */ + u32 gcr; /* General Configuration Register */ + u32 gsr[2]; /* General Status Register */ + u32 bdlr[5]; /* Bit Delay Line Register */ + u32 lcdlr[3]; /* Local Calibrated Delay Line Register */ + u32 mdlr; /* Master Delay Line Register */ + u32 gtr; /* General Timing Register */ + u32 rsv[3]; /* Reserved */ + } dx[9]; +}; + +#endif /* __ASSEMBLY__ */ + +#define PIR_INIT (1 << 0) /* Initialization Trigger */ +#define PIR_ZCAL (1 << 1) /* Impedance Calibration */ +#define PIR_PLLINIT (1 << 4) /* PLL Initialization */ +#define PIR_DCAL (1 << 5) /* DDL Calibration */ +#define PIR_PHYRST (1 << 6) /* PHY Reset */ +#define PIR_DRAMRST (1 << 7) /* DRAM Reset */ +#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */ +#define PIR_WL (1 << 9) /* Write Leveling */ +#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */ +#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */ +#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */ +#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */ +#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */ +#define PIR_WREYE (1 << 15) /* Write Data Eye Training */ +#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */ +#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */ +#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */ +#define PIR_INITBYP (1 << 31) /* Initialization Bypass */ + +#define PGSR0_IDONE (1 << 0) /* Initialization Done */ +#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */ +#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */ +#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */ +#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */ +#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */ +#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */ +#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */ +#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */ +#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */ +#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */ +#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */ +#define PGSR0_IERR (1 << 16) /* Initialization Error */ +#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */ +#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */ +#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */ +#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */ +#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */ +#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */ +#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */ +#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */ +#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */ +#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */ +#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */ +#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/ +#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT)) +#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */ + +#define DXCCR_DQSRES_OPEN (0 << 5) +#define DXCCR_DQSRES_688_OHM (1 << 5) +#define DXCCR_DQSRES_611_OHM (2 << 5) +#define DXCCR_DQSRES_550_OHM (3 << 5) +#define DXCCR_DQSRES_500_OHM (4 << 5) +#define DXCCR_DQSRES_458_OHM (5 << 5) +#define DXCCR_DQSRES_393_OHM (6 << 5) +#define DXCCR_DQSRES_344_OHM (7 << 5) + +#define DXCCR_DQSNRES_OPEN (0 << 9) +#define DXCCR_DQSNRES_688_OHM (1 << 9) +#define DXCCR_DQSNRES_611_OHM (2 << 9) +#define DXCCR_DQSNRES_550_OHM (3 << 9) +#define DXCCR_DQSNRES_500_OHM (4 << 9) +#define DXCCR_DQSNRES_458_OHM (5 << 9) +#define DXCCR_DQSNRES_393_OHM (6 << 9) +#define DXCCR_DQSNRES_344_OHM (7 << 9) + +#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ +#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT)) +#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */ +#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */ +#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT)) + +#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ +#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT)) + +/* SoC-specific parameters */ +#define NR_DATX8_PER_DDRPHY 2 + +#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#define NR_DDRPHY_PER_CH 1 +#else +#define NR_DDRPHY_PER_CH 2 +#endif + +#define NR_DDRCH 2 + +#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy)) + +#ifndef __ASSEMBLY__ +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); +int ddrphy_training(struct ddrphy __iomem *phy); +#endif + +#endif /* ARCH_DDRPHY_REGS_H */ diff --git a/arch/arm/mach-uniphier/include/mach/debug-uart.S b/arch/arm/mach-uniphier/include/mach/debug-uart.S new file mode 100644 index 0000000..af55fee --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/debug-uart.S @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/serial_reg.h> + +#if !defined(CONFIG_DEBUG_SEMIHOSTING) +#include CONFIG_DEBUG_LL_INCLUDE +#endif + +#define BAUDRATE 115200 +#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) +#define DIVISOR DIV_ROUND(UART_CLK, 16 * BAUDRATE) + + .macro init_debug_uart, ra, rb, rc + addruart \ra, \rb, \rc + mov \rb, #UART_LCR_WLEN8 + strb \rb, [\ra, #0x11] + ldr \rb, =DIVISOR + str \rb, [\ra, #0x24] + .endm diff --git a/arch/arm/mach-uniphier/include/mach/led.h b/arch/arm/mach-uniphier/include/mach/led.h new file mode 100644 index 0000000..21277da --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/led.h @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_LED_H +#define ARCH_LED_H + +#include <config.h> + +#define LED_CHAR_0 0x7e +#define LED_CHAR_1 0x0c +#define LED_CHAR_2 0xb6 +#define LED_CHAR_3 0x9e +#define LED_CHAR_4 0xcc +#define LED_CHAR_5 0xda +#define LED_CHAR_6 0xfa +#define LED_CHAR_7 0x4e +#define LED_CHAR_8 0xfe +#define LED_CHAR_9 0xde + +#define LED_CHAR_A 0xee +#define LED_CHAR_B 0xf8 +#define LED_CHAR_C 0x72 +#define LED_CHAR_D 0xbc +#define LED_CHAR_E 0xf2 +#define LED_CHAR_F 0xe2 +#define LED_CHAR_G 0x7a +#define LED_CHAR_H 0xe8 +#define LED_CHAR_I 0x08 +#define LED_CHAR_J 0x3c +#define LED_CHAR_K 0xea +#define LED_CHAR_L 0x70 +#define LED_CHAR_M 0x6e +#define LED_CHAR_N 0xa8 +#define LED_CHAR_O 0xb8 +#define LED_CHAR_P 0xe6 +#define LED_CHAR_Q 0xce +#define LED_CHAR_R 0xa0 +#define LED_CHAR_S 0xc8 +#define LED_CHAR_T 0x8c +#define LED_CHAR_U 0x7c +#define LED_CHAR_V 0x54 +#define LED_CHAR_W 0xfc +#define LED_CHAR_X 0xec +#define LED_CHAR_Y 0xdc +#define LED_CHAR_Z 0xa4 + +#define LED_CHAR_SPACE 0x00 +#define LED_CHAR_DOT 0x01 + +#define LED_CHAR_ (LED_CHAR_SPACE) + +/** Macro to translate 4 characters into integer to display led */ +#define LED_C2I(C0, C1, C2, C3) \ + (~( \ + (LED_CHAR_##C0 << 24) | \ + (LED_CHAR_##C1 << 16) | \ + (LED_CHAR_##C2 << 8) | \ + (LED_CHAR_##C3) \ + )) + +#if defined(CONFIG_SUPPORT_CARD_LED_BASE) + +#define LED_ADDR CONFIG_SUPPORT_CARD_LED_BASE + +#ifdef __ASSEMBLY__ + +#define led_write(C0, C1, C2, C3) raw_led_write LED_C2I(C0, C1, C2, C3) +.macro raw_led_write data + ldr r0, =\data + ldr r1, =LED_ADDR + str r0, [r1] +.endm + +#else /* __ASSEMBLY__ */ + +#include <asm/io.h> + +#define led_write(C0, C1, C2, C3) \ +do { \ + raw_led_write(LED_C2I(C0, C1, C2, C3)); \ +} while (0) + +static inline void raw_led_write(u32 data) +{ + writel(data, LED_ADDR); +} + +#endif /* __ASSEMBLY__ */ + +#else /* CONFIG_SUPPORT_CARD_LED_BASE */ + +#define led_write(C0, C1, C2, C3) +#define raw_led_write(x) + +#endif /* CONFIG_SUPPORT_CARD_LED_BASE */ + +#endif /* ARCH_LED_H */ diff --git a/arch/arm/mach-uniphier/include/mach/mio-regs.h b/arch/arm/mach-uniphier/include/mach/mio-regs.h new file mode 100644 index 0000000..3306934 --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/mio-regs.h @@ -0,0 +1,20 @@ +/* + * UniPhier MIO (Media I/O) registers + * + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_MIO_REGS_H +#define ARCH_MIO_REGS_H + +#define MIO_BASE 0x59810000 + +#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020) +#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110) +#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114) + +#define MIO_USB_RSTCTRL_XRST (0x1 << 0) + +#endif /* ARCH_MIO_REGS_H */ diff --git a/arch/arm/mach-uniphier/include/mach/platdevice.h b/arch/arm/mach-uniphier/include/mach/platdevice.h new file mode 100644 index 0000000..cdf7d13 --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/platdevice.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_PLATDEVICE_H +#define ARCH_PLATDEVICE_H + +#include <dm/platdata.h> +#include <dm/platform_data/serial-uniphier.h> + +#define SERIAL_DEVICE(n, ba, clk) \ +static struct uniphier_serial_platform_data serial_device##n = { \ + .base = ba, \ + .uartclk = clk \ +}; \ +U_BOOT_DEVICE(serial##n) = { \ + .name = DRIVER_NAME, \ + .platdata = &serial_device##n \ +}; + +#endif /* ARCH_PLATDEVICE_H */ diff --git a/arch/arm/mach-uniphier/include/mach/sbc-regs.h b/arch/arm/mach-uniphier/include/mach/sbc-regs.h new file mode 100644 index 0000000..efb68e8 --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/sbc-regs.h @@ -0,0 +1,109 @@ +/* + * UniPhier SBC (System Bus Controller) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SBC_REGS_H +#define ARCH_SBC_REGS_H + +#define SBBASE_BASE 0x58c00100 +#define SBBASE(x) (SBBASE_BASE + (x) * 0x10) + +#define SBBASE0 (SBBASE(0)) +#define SBBASE1 (SBBASE(1)) +#define SBBASE2 (SBBASE(2)) +#define SBBASE3 (SBBASE(3)) +#define SBBASE4 (SBBASE(4)) +#define SBBASE5 (SBBASE(5)) +#define SBBASE6 (SBBASE(6)) +#define SBBASE7 (SBBASE(7)) + +#define SBBASE_BANK_ENABLE (0x00000001) + +#define SBCTRL_BASE 0x58c00200 +#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4) + +#define SBCTRL00 SBCTRL(0, 0) +#define SBCTRL01 SBCTRL(0, 1) +#define SBCTRL02 SBCTRL(0, 2) +#define SBCTRL03 SBCTRL(0, 3) +#define SBCTRL04 (SBCTRL_BASE + 0x100) + +#define SBCTRL10 SBCTRL(1, 0) +#define SBCTRL11 SBCTRL(1, 1) +#define SBCTRL12 SBCTRL(1, 2) +#define SBCTRL13 SBCTRL(1, 3) +#define SBCTRL14 (SBCTRL_BASE + 0x110) + +#define SBCTRL20 SBCTRL(2, 0) +#define SBCTRL21 SBCTRL(2, 1) +#define SBCTRL22 SBCTRL(2, 2) +#define SBCTRL23 SBCTRL(2, 3) +#define SBCTRL24 (SBCTRL_BASE + 0x120) + +#define SBCTRL30 SBCTRL(3, 0) +#define SBCTRL31 SBCTRL(3, 1) +#define SBCTRL32 SBCTRL(3, 2) +#define SBCTRL33 SBCTRL(3, 3) +#define SBCTRL34 (SBCTRL_BASE + 0x130) + +#define SBCTRL40 SBCTRL(4, 0) +#define SBCTRL41 SBCTRL(4, 1) +#define SBCTRL42 SBCTRL(4, 2) +#define SBCTRL43 SBCTRL(4, 3) +#define SBCTRL44 (SBCTRL_BASE + 0x140) + +#define SBCTRL50 SBCTRL(5, 0) +#define SBCTRL51 SBCTRL(5, 1) +#define SBCTRL52 SBCTRL(5, 2) +#define SBCTRL53 SBCTRL(5, 3) +#define SBCTRL54 (SBCTRL_BASE + 0x150) + +#define SBCTRL60 SBCTRL(6, 0) +#define SBCTRL61 SBCTRL(6, 1) +#define SBCTRL62 SBCTRL(6, 2) +#define SBCTRL63 SBCTRL(6, 3) +#define SBCTRL64 (SBCTRL_BASE + 0x160) + +#define SBCTRL70 SBCTRL(7, 0) +#define SBCTRL71 SBCTRL(7, 1) +#define SBCTRL72 SBCTRL(7, 2) +#define SBCTRL73 SBCTRL(7, 3) +#define SBCTRL74 (SBCTRL_BASE + 0x170) + +/* slower but LED works */ +#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000 +#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00 +#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009 +#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110 + +/* faster but LED does not work */ +#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000 +#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700 +/* NOR flash needs more wait counts than SRAM */ +#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009 +#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210 + +#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000 +#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500 +#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020 + +#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000 +#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500 +#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010 + +#define PC0CTRL 0x598000c0 +#define ROM_BOOT_ROMRSV2 0x59801208 + +#ifndef __ASSEMBLY__ +#include <asm/io.h> +static inline int boot_is_swapped(void) +{ + return !(readl(SBBASE0) & SBBASE_BANK_ENABLE); +} +#endif + +#endif /* ARCH_SBC_REGS_H */ diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h new file mode 100644 index 0000000..20878e2 --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h @@ -0,0 +1,69 @@ +/* + * UniPhier SC (System Control) block registers + * + * Copyright (C) 2011-2015 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SC_REGS_H +#define ARCH_SC_REGS_H + +#define SC_BASE_ADDR 0x61840000 + +#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) +#define SC_DPLLCTRL_SSC_EN (0x1 << 31) +#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) +#define SC_DPLLCTRL_SSC_RATE (0x1 << 15) + +#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204) +#define SC_DPLLCTRL2_NRSTDS (0x1 << 28) + +#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208) +#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31) +#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31) + +#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210) + +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270) +#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274) +#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278) + +#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290) +#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294) +#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) + +#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) +#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */ +#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */ +#define SC_RSTCTRL_NRST_ETHER (0x1 << 12) +#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) +#define SC_RSTCTRL_NRST_GIO (0x1 << 6) +#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) +#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) +#define SC_RSTCTRL_NRST_NAND (0x1 << 2) + +#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) +#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */ +#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */ + +#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) + +#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) +#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ +#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ +#define SC_CLKCTRL_CEN_ETHER (0x1 << 12) +#define SC_CLKCTRL_CEN_MIO (0x1 << 11) +#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10) +#define SC_CLKCTRL_CEN_GIO (0x1 << 6) +#define SC_CLKCTRL_CEN_UMC (0x1 << 4) +#define SC_CLKCTRL_CEN_NAND (0x1 << 2) +#define SC_CLKCTRL_CEN_SBC (0x1 << 1) +#define SC_CLKCTRL_CEN_PERI (0x1 << 0) + +/* System reset control register */ +#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) +#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010) +#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014) + +#endif /* ARCH_SC_REGS_H */ diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h new file mode 100644 index 0000000..63408d5 --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h @@ -0,0 +1,121 @@ +/* + * UniPhier SG (SoC Glue) block registers + * + * Copyright (C) 2011-2015 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SG_REGS_H +#define ARCH_SG_REGS_H + +/* Base Address */ +#define SG_CTRL_BASE 0x5f800000 +#define SG_DBG_BASE 0x5f900000 + +/* Revision */ +#define SG_REVISION (SG_CTRL_BASE | 0x0000) +#define SG_REVISION_TYPE_SHIFT 16 +#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT) +#define SG_REVISION_MODEL_SHIFT 8 +#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT) +#define SG_REVISION_REV_SHIFT 0 +#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT) + +/* Memory Configuration */ +#define SG_MEMCONF (SG_CTRL_BASE | 0x0400) + +#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0)) +#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0)) +#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0)) +#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8) +#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8) + +#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2)) +#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2)) +#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2)) +#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) +#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9) + +#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16)) +#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) +#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) +#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) +#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) +#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) + +#define SG_MEMCONF_SPARSEMEM (0x1 << 4) + +/* Pin Control */ +#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000) + +#if defined(CONFIG_MACH_PH1_PRO4) +# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8) +#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4) +#endif + +#if defined(CONFIG_MACH_PH1_PRO4) +#define SG_PINSELBITS 4 +#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#define SG_PINSELBITS 8 +#endif + +#define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32)) +#define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \ + ((n) * (SG_PINSELBITS) % 32))) +#define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32)) + +/* Only for PH1-Pro4 */ +#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700) + +/* Input Enable */ +#define SG_IECTRL (SG_CTRL_BASE | 0x1d00) + +/* Pin Monitor */ +#define SG_PINMON0 (SG_DBG_BASE | 0x0100) + +#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19) +#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19) +#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19) +#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19) + +#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16) + +#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16) + +#ifdef __ASSEMBLY__ + + .macro set_pinsel, n, value, ra, rd + ldr \ra, =SG_PINSEL_ADDR(\n) + ldr \rd, [\ra] + and \rd, \rd, #SG_PINSEL_MASK(\n) + orr \rd, \rd, #SG_PINSEL_MODE(\n, \value) + str \rd, [\ra] + .endm + +#else + +#include <linux/types.h> +#include <asm/io.h> + +static inline void sg_set_pinsel(int n, int value) +{ + writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n)) + | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n)); +} + +#endif /* __ASSEMBLY__ */ + +#endif /* ARCH_SG_REGS_H */ diff --git a/arch/arm/mach-uniphier/include/mach/ssc-regs.h b/arch/arm/mach-uniphier/include/mach/ssc-regs.h new file mode 100644 index 0000000..02fca3b --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/ssc-regs.h @@ -0,0 +1,65 @@ +/* + * UniPhier System Cache (L2 Cache) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SSC_REGS_H +#define ARCH_SSC_REGS_H + +#define SSCC 0x500c0000 +#define SSCC_BST (0x1 << 20) +#define SSCC_ACT (0x1 << 19) +#define SSCC_WTG (0x1 << 18) +#define SSCC_PRD (0x1 << 17) +#define SSCC_WBWA (0x1 << 16) +#define SSCC_EX (0x1 << 13) +#define SSCC_ON (0x1 << 0) + +#define SSCLPDAWCR 0x500c0030 + +#define SSCOPE 0x506c0244 +#define SSCOPE_CM_SYNC 0x00000008 + +#define SSCOQM 0x506c0248 +#define SSCOQM_TID_MASK (0x3 << 21) +#define SSCOQM_TID_BY_WAY (0x2 << 21) +#define SSCOQM_TID_BY_INST_WAY (0x1 << 21) +#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21) +#define SSCOQM_S_MASK (0x3 << 17) +#define SSCOQM_S_WAY (0x2 << 17) +#define SSCOQM_S_ALL (0x1 << 17) +#define SSCOQM_S_ADDRESS (0x0 << 17) +#define SSCOQM_CE (0x1 << 15) +#define SSCOQM_CW (0x1 << 14) +#define SSCOQM_CM_MASK (0x7) +#define SSCOQM_CM_DIRT_TOUCH (0x7) +#define SSCOQM_CM_ZERO_TOUCH (0x6) +#define SSCOQM_CM_NORM_TOUCH (0x5) +#define SSCOQM_CM_PREF_FETCH (0x4) +#define SSCOQM_CM_SSC_FETCH (0x3) +#define SSCOQM_CM_WB_INV (0x2) +#define SSCOQM_CM_WB (0x1) +#define SSCOQM_CM_INV (0x0) + +#define SSCOQAD 0x506c024c +#define SSCOQSZ 0x506c0250 +#define SSCOQWN 0x506c0258 + +#define SSCOPPQSEF 0x506c025c +#define SSCOPPQSEF_FE (0x1 << 1) +#define SSCOPPQSEF_OE (0x1 << 0) + +#define SSCOLPQS 0x506c0260 +#define SSCOLPQS_EF (0x1 << 2) +#define SSCOLPQS_EST (0x1 << 1) +#define SSCOLPQS_QST (0x1 << 0) + +#define SSCOQCE0 0x506c0270 + +#define SSC_LINE_SIZE 128 +#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE)) + +#endif /* ARCH_SSC_REGS_H */ diff --git a/arch/arm/mach-uniphier/include/mach/umc-regs.h b/arch/arm/mach-uniphier/include/mach/umc-regs.h new file mode 100644 index 0000000..6159281 --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/umc-regs.h @@ -0,0 +1,119 @@ +/* + * UniPhier UMC (Universal Memory Controller) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_UMC_REGS_H +#define ARCH_UMC_REGS_H + +#define UMC_BASE 0x5b800000 + +/* SSIF registers */ +#define UMC_SSIF_BASE UMC_BASE + +#define UMC_CPURST 0x00000700 +#define UMC_IDSRST 0x0000070C +#define UMC_IXMRST 0x00000714 +#define UMC_HDMRST 0x00000718 +#define UMC_MDMRST 0x0000071C +#define UMC_HDDRST 0x00000720 +#define UMC_MDDRST 0x00000724 +#define UMC_SIORST 0x00000728 +#define UMC_GIORST 0x0000072C +#define UMC_HD2RST 0x00000734 +#define UMC_VIORST 0x0000073C +#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */ +#define UMC_DVCRST 0x00000748 /* Pro4 */ +#define UMC_RGLRST 0x00000750 +#define UMC_VPERST 0x00000758 +#define UMC_AIORST 0x00000764 +#define UMC_DMDRST 0x00000770 + +#define UMC_HDMCHSEL 0x00000898 +#define UMC_MDMCHSEL 0x0000089C +#define UMC_DVCCHSEL 0x000008C8 +#define UMC_DMDCHSEL 0x000008F0 + +#define UMC_CLKEN_SSIF_FETCH 0x0000C060 +#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064 +#define UMC_CLKEN_SSIF_COMWC0 0x0000C068 +#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C +#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070 +#define UMC_CLKEN_SSIF_COMWC1 0x0000C074 +#define UMC_CLKEN_SSIF_COMRC1 0x0000C078 +#define UMC_CLKEN_SSIF_WC 0x0000C07C +#define UMC_CLKEN_SSIF_RC 0x0000C080 +#define UMC_CLKEN_SSIF_DST 0x0000C084 + +/* CA registers */ +#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch)) + +/* DRAM controller registers */ +#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch)) + +#define UMC_CMDCTLA 0x00000000 +#define UMC_CMDCTLB 0x00000004 +#define UMC_INITCTLA 0x00000008 +#define UMC_INITCTLB 0x0000000C +#define UMC_INITCTLC 0x00000010 +#define UMC_INITSET 0x00000014 +#define UMC_INITSTAT 0x00000018 +#define UMC_DRMMR0 0x0000001C +#define UMC_DRMMR1 0x00000020 +#define UMC_DRMMR2 0x00000024 +#define UMC_DRMMR3 0x00000028 +#define UMC_SPCCTLA 0x00000030 +#define UMC_SPCCTLB 0x00000034 +#define UMC_SPCSETA 0x00000038 +#define UMC_SPCSETB 0x0000003C +#define UMC_SPCSETC 0x00000040 +#define UMC_SPCSETD 0x00000044 +#define UMC_SPCSTATA 0x00000050 +#define UMC_SPCSTATB 0x00000054 +#define UMC_SPCSTATC 0x00000058 +#define UMC_ACSSETA 0x00000060 +#define UMC_FLOWCTLA 0x00000400 +#define UMC_FLOWCTLB 0x00000404 +#define UMC_FLOWCTLC 0x00000408 +#define UMC_FLOWCTLG 0x00000508 +#define UMC_RDATACTL_D0 0x00000600 +#define UMC_WDATACTL_D0 0x00000604 +#define UMC_RDATACTL_D1 0x00000608 +#define UMC_WDATACTL_D1 0x0000060C +#define UMC_DATASET 0x00000610 +#define UMC_DCCGCTL 0x00000720 +#define UMC_DICGCTLA 0x00000724 +#define UMC_DICGCTLB 0x00000728 +#define UMC_DIOCTLA 0x00000C00 +#define UMC_DFICUPDCTLA 0x00000C20 + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> + +static inline void umc_polling(u32 address, u32 expval, u32 mask) +{ + u32 nmask = ~mask; + u32 data; + do { + data = readl(address) & nmask; + } while (data != expval); +} + +static inline void umc_dram_init_start(void __iomem *dramcont) +{ + writel(0x00000002, dramcont + UMC_INITSET); +} + +static inline void umc_dram_init_poll(void __iomem *dramcont) +{ + while ((readl(dramcont + UMC_INITSTAT) & 0x00000002)) + ; +} + +#endif + +#endif diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S new file mode 100644 index 0000000..2638bcd --- /dev/null +++ b/arch/arm/mach-uniphier/init_page_table.S @@ -0,0 +1,26 @@ +#include <config.h> +#include <linux/linkage.h> + +/* page table */ +#define NR_SECTIONS 4096 +#define SECTION_SHIFT 20 +#define DEVICE 0x00002002 /* Non-shareable Device */ +#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */ + +#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT)) +#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT)) + + .section ".rodata" + .align 14 +ENTRY(init_page_table) + section = 0 + .rept NR_SECTIONS + .if section == TEXT_SECTION || section == STACK_SECTION + attr = NORMAL + .else + attr = DEVICE + .endif + .word (section << SECTION_SHIFT) | attr + section = section + 1 + .endr +END(init_page_table) diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S new file mode 100644 index 0000000..92299fe --- /dev/null +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> +#include <linux/sizes.h> +#include <asm/system.h> +#include <mach/led.h> +#include <mach/arm-mpcore.h> +#include <mach/sbc-regs.h> +#include <mach/ssc-regs.h> + +ENTRY(lowlevel_init) + mov r8, lr @ persevere link reg across call + + /* + * The UniPhier Boot ROM loads SPL code to the L2 cache. + * But CPUs can only do instruction fetch now because start.S has + * cleared C and M bits. + * First we need to turn on MMU and Dcache again to get back + * data access to L2. + */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache + mcr p15, 0, r0, c1, c0, 0 + +#ifdef CONFIG_DEBUG_LL + bl setup_lowlevel_debug +#endif + + /* + * Now we are using the page table embedded in the Boot ROM. + * It is not handy since it is not a straight mapped table for sLD3. + * What we need to do next is to switch over to the page table in SPL. + */ + ldr r3, =init_page_table @ page table must be 16KB aligned + + /* Disable MMU and Dcache before switching Page Table */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache + mcr p15, 0, r0, c1, c0, 0 + + bl enable_mmu + +#ifdef CONFIG_UNIPHIER_SMP + /* + * ACTLR (Auxiliary Control Register) for Cortex-A9 + * bit[9] Parity on + * bit[8] Alloc in one way + * bit[7] EXCL (Exclusive cache bit) + * bit[6] SMP + * bit[3] Write full line of zeros mode + * bit[2] L1 Prefetch enable + * bit[1] L2 prefetch enable + * bit[0] FW (Cache and TLB maintenance broadcast) + */ + mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register) + orr r0, r0, #0x41 @ enable SMP, FW bit + mcr p15, 0, r0, c1, c0, 1 + + /* branch by CPU ID */ + mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register) + and r0, r0, #0x3 + cmp r0, #0x0 + beq primary_cpu + ldr r1, =ROM_BOOT_ROMRSV2 + mov r0, #0 + str r0, [r1] +0: wfe + ldr r0, [r1] + cmp r0, #0 + beq 0b + bx r0 @ r0: entry point of U-Boot main for the secondary CPU +primary_cpu: + ldr r1, =ROM_BOOT_ROMRSV2 + ldr r0, =_start @ entry for the secondary CPU + str r0, [r1] + ldr r0, [r1] @ make sure str is complete before sev + sev @ kick the sedoncary CPU + mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register + bfc r1, #0, #13 @ clear bit 12-0 + mov r0, #-1 + str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register + mov r0, #1 @ SCU enable + str r0, [r1, #SCU_CTRL] @ SCU Control Register +#endif + + bl setup_init_ram @ RAM area for temporary stack pointer + + mov lr, r8 @ restore link + mov pc, lr @ back to my caller +ENDPROC(lowlevel_init) + +ENTRY(enable_mmu) + mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register) + bic r0, r0, #0x37 + orr r0, r0, #0x20 @ disable TTBR1 + mcr p15, 0, r0, c2, c0, 2 + + orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA + mcr p15, 0, r0, c2, c0, 0 @ TTBR0 + + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + + mov r0, #-1 @ manager for all domains (No permission check) + mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register) + + dsb + isb + /* + * MMU on: + * TLBs was already invalidated in "../start.S" + * So, we don't need to invalidate it here. + */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable + mcr p15, 0, r0, c1, c0, 0 + + mov pc, lr +ENDPROC(enable_mmu) + +/* + * For PH1-Pro4 or older SoCs, the size of WAY is 32KB. + * It is large enough for tmp RAM. + */ +#define BOOT_RAM_SIZE (SZ_32K) +#define BOOT_WAY_BITS (0x00000100) /* way 8 */ + +ENTRY(setup_init_ram) + /* + * Touch to zero for the boot way + */ +0: + /* + * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order + */ + ldr r0, = 0x00408006 @ touch to zero with address range + ldr r1, = SSCOQM + str r0, [r1] + ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address + ldr r1, = SSCOQAD + str r0, [r1] + ldr r0, = BOOT_RAM_SIZE + ldr r1, = SSCOQSZ + str r0, [r1] + ldr r0, = BOOT_WAY_BITS + ldr r1, = SSCOQWN + str r0, [r1] + ldr r1, = SSCOPPQSEF + ldr r0, [r1] + cmp r0, #0 @ check if the command is successfully set + bne 0b @ try again if an error occurres + + ldr r1, = SSCOLPQS +1: + ldr r0, [r1] + cmp r0, #0x4 + bne 1b @ wait until the operation is completed + str r0, [r1] @ clear the complete notification flag + + mov pc, lr +ENDPROC(setup_init_ram) diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c new file mode 100644 index 0000000..bf3c177 --- /dev/null +++ b/arch/arm/mach-uniphier/memconf.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/sizes.h> +#include <asm/io.h> +#include <mach/sg-regs.h> + +static inline u32 sg_memconf_val_ch0(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH0_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH0_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH0_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH0_SZ_512M; + break; + case SZ_1G: + ret = SG_MEMCONF_CH0_SZ_1G; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH0_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH0_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +static inline u32 sg_memconf_val_ch1(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH1_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH1_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH1_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH1_SZ_512M; + break; + case SZ_1G: + ret = SG_MEMCONF_CH1_SZ_1G; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH1_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH1_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +void memconf_init(void) +{ + u32 tmp; + + /* Set DDR size */ + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); + tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE + tmp |= SG_MEMCONF_SPARSEMEM; +#endif + writel(tmp, SG_MEMCONF); +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile new file mode 100644 index 0000000..5ce3d8a --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile @@ -0,0 +1,16 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o +obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ + pll_spectrum.o umc_init.o ddrphy_init.o +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +else +obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o +obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o +endif + +obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c b/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c new file mode 100644 index 0000000..837e0d1 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/bcu-regs.h> + +#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) + +void bcu_init(void) +{ + int shift; + + writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */ + writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ + + /* Specify DDR channel */ + shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4; + writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c b/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c new file mode 100644 index 0000000..d359b56 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c @@ -0,0 +1 @@ +#include "../ph1-pro4/boot-mode.c" diff --git a/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c new file mode 100644 index 0000000..4ac5411 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sc-regs.h> + +void clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_RSTCTRL_NRST_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_RSTCTRL_NRST_NAND; +#endif + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_CLKCTRL_CEN_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_CLKCTRL_CEN_NAND; +#endif + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c new file mode 100644 index 0000000..a47e87a --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/types.h> +#include <asm/io.h> +#include <mach/ddrphy-regs.h> + +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8253c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a82dbc0, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + + writel(0x00000800, &phy->mr3); + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c new file mode 100644 index 0000000..d7ef16b --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c @@ -0,0 +1 @@ +#include "../ph1-pro4/early_clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S new file mode 100644 index 0000000..7928c5c --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S @@ -0,0 +1,29 @@ +/* + * On-chip UART initializaion for low-level debugging + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> +#include <mach/sg-regs.h> + +#define UART_CLK 36864000 +#include <mach/debug-uart.S> + +ENTRY(setup_lowlevel_debug) + init_debug_uart r0, r1, r2 + + /* UART Port 0 */ + set_pinsel 85, 1, r0, r1 + set_pinsel 88, 1, r0, r1 + + ldr r0, =SG_IECTRL + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] + + mov pc, lr +ENDPROC(setup_lowlevel_debug) diff --git a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c new file mode 100644 index 0000000..15d81eb --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sg-regs.h> + +void pin_init(void) +{ + u32 tmp; + + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ + sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ + + sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ + sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ + + sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ + sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */ + sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */ + sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */ + sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */ + sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */ + sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */ + sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */ + sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */ + sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */ + sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */ + sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */ + sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */ + sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */ + sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */ + sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */ + sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */ + sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */ + sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */ + /* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */ + /* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */ +#endif + + tmp = readl(SG_IECTRL); + tmp |= 0x41; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/platdevice.c b/arch/arm/mach-uniphier/ph1-ld4/platdevice.c new file mode 100644 index 0000000..c0e6294 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/platdevice.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/platdevice.h> + +#define UART_MASTER_CLK 36864000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) diff --git a/arch/arm/mach-uniphier/ph1-ld4/pll_init.c b/arch/arm/mach-uniphier/ph1-ld4/pll_init.c new file mode 100644 index 0000000..985e14f --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/pll_init.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sc-regs.h> +#include <mach/sg-regs.h> + +#undef DPLL_SSC_RATE_1PER + +static void dpll_init(void) +{ + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT (DPLLCTRL.bit[29:20]) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x000f0000; +#if CONFIG_DDR_FREQ == 1600 + tmp |= 0x000c0000; +#elif CONFIG_DDR_FREQ == 1333 + tmp |= 0x000d0000; +#else +# error "Unknown frequency" +#endif + +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~SC_DPLLCTRL_SSC_RATE; +#else + tmp |= SC_DPLLCTRL_SSC_RATE; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); +} + +static void upll_init(void) +{ + u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ + tmp = readl(SC_UPLLCTRL); + tmp &= ~0x18000000; + writel(tmp, SC_UPLLCTRL); + + if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x0228f5c0; + } else { + /* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x02328000; + } + } + + writel(tmp, SC_UPLLCTRL); + + /* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |= 0x08000000; + writel(tmp, SC_UPLLCTRL); + + /* wait 10 usec */ + udelay(10); + + /* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |= 0x10000000; + writel(tmp, SC_UPLLCTRL); +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 1 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* AXO: default 24.576MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* wait 10 usec */ + udelay(10); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* set 0 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +void pll_init(void) +{ + dpll_init(); + upll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 10 usec in upll_init() and vpll_init() + * so 20 usec can be saved here. + */ + udelay(480); +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c new file mode 100644 index 0000000..837b2a8 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c @@ -0,0 +1 @@ +#include "../ph1-pro4/pll_spectrum.c" diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c new file mode 100644 index 0000000..00f8461 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> + +void sbc_init(void) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); + + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * + * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank + * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x00000000-0x01ffffff: mask ROM + * 0x02000000-0x03efffff: memory bank (31MB) + * 0x03f00000-0x03ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c new file mode 100644 index 0000000..374a8c0 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> + +void sbc_init(void) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); + + /* XECS1: sub/boot memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + + /* XECS0: boot/sub memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); + + /* XECS3: peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); + + /* base address regsiters */ + writel(0x0000bc01, SBBASE0); + writel(0x0400bc01, SBBASE1); + writel(0x0800bf01, SBBASE3); + + /* enable access to sub memory when boot swap is on */ + if (boot_is_swapped()) + sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ + + sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/sg_init.c b/arch/arm/mach-uniphier/ph1-ld4/sg_init.c new file mode 100644 index 0000000..93e44af --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/sg_init.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sg-regs.h> + +void sg_init(void) +{ + u32 tmp; + + /* Input ports must be enabled before deasserting reset of cores */ + tmp = readl(SG_IECTRL); + tmp |= 0x1; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/umc_init.c b/arch/arm/mach-uniphier/ph1-ld4/umc_init.c new file mode 100644 index 0000000..081b028 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/umc_init.c @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/umc-regs.h> +#include <mach/ddrphy-regs.h> + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000000, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x000fffcf, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_FRCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ + if (freq == 1333) { + writel(0x45990b11, dramcont + UMC_CMDCTLA); + writel(0x16958924, dramcont + UMC_CMDCTLB); + writel(0x5101046A, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x27028B0A, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x38028B0A, dramcont + UMC_INITCTLB); + + writel(0x000FF0FF, dramcont + UMC_INITCTLC); + writel(0x00000b51, dramcont + UMC_DRMMR0); + } else if (freq == 1600) { + writel(0x36BB0F17, dramcont + UMC_CMDCTLA); + writel(0x18C6AA24, dramcont + UMC_CMDCTLB); + writel(0x5101387F, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x2F030D3F, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x43030D3F, dramcont + UMC_INITCTLB); + + writel(0x00FF00FF, dramcont + UMC_INITCTLC); + writel(0x00000d71, dramcont + UMC_DRMMR0); + } + + writel(0x00000006, dramcont + UMC_DRMMR1); + + if (freq == 1333) + writel(0x00000290, dramcont + UMC_DRMMR2); + else if (freq == 1600) + writel(0x00000298, dramcont + UMC_DRMMR2); + + writel(0x00000800, dramcont + UMC_DRMMR3); + + if (freq == 1333) { + if (size == 1) + writel(0x00240512, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x00350512, dramcont + UMC_SPCCTLA); + + writel(0x00ff0006, dramcont + UMC_SPCCTLB); + writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + } else if (freq == 1600) { + if (size == 1) + writel(0x002B0617, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x003F0617, dramcont + UMC_SPCCTLA); + + writel(0x00ff0008, dramcont + UMC_SPCCTLB); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + } + + writel(0x04060806, dramcont + UMC_WDATACTL_D0); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x00000003, dramcont + 0x7000); + writel(0x0000000f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000071, dramcont + 0x8008); + writel(0x0000003b, dramcont + UMC_DICGCTLA); + writel(0x020a0808, dramcont + UMC_DICGCTLB); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00000000, dramcont + UMC_SPCSETD); + writel(0x00000520, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 1); + ddrphy_training(phy1_0); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int umc_init(void) +{ + return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, + CONFIG_SDRAM1_SIZE / 0x08000000); +} + +#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ + (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ + CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 +/* OK */ +#else +#error Unsupported DDR configuration. +#endif diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile new file mode 100644 index 0000000..b88525c --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/Makefile @@ -0,0 +1,16 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o +obj-y += sg_init.o pll_init.o early_clkrst_init.o \ + pll_spectrum.o umc_init.o ddrphy_init.o +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +else +obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o +obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o +endif + +obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c b/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c new file mode 100644 index 0000000..9894c1a --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <mach/boot-device.h> +#include <mach/sg-regs.h> +#include <mach/sbc-regs.h> + +struct boot_device_info boot_device_table[] = { + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + { /* sentinel */ } +}; + +int get_boot_mode_sel(void) +{ + return (readl(SG_PINMON0) >> 1) & 0x1f; +} + +u32 spl_boot_device(void) +{ + int boot_mode; + + if (boot_is_swapped()) + return BOOT_DEVICE_NOR; + + boot_mode = get_boot_mode_sel(); + + return boot_device_table[boot_mode].type; +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c new file mode 100644 index 0000000..054efa6 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sc-regs.h> + +void clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | + SC_RSTCTRL_NRST_GIO; +#endif +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_RSTCTRL_NRST_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_RSTCTRL_NRST_NAND; +#endif + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp = readl(SC_RSTCTRL2); + tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; + writel(tmp, SC_RSTCTRL2); + readl(SC_RSTCTRL2); /* dummy read */ +#endif + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | + SC_CLKCTRL_CEN_GIO; +#endif +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_CLKCTRL_CEN_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_CLKCTRL_CEN_NAND; +#endif + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c new file mode 100644 index 0000000..7df5aea --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/types.h> +#include <asm/io.h> +#include <mach/ddrphy-regs.h> + +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8363c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a878400, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + + writel(0x00000000, &phy->mr3); + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c new file mode 100644 index 0000000..37bb79e --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <mach/sc-regs.h> + +void early_clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); + + tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; + if (spl_boot_device() != BOOT_DEVICE_NAND) + tmp &= ~SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S new file mode 100644 index 0000000..fcaf6d1 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S @@ -0,0 +1,39 @@ +/* + * On-chip UART initializaion for low-level debugging + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> +#include <mach/sc-regs.h> +#include <mach/sg-regs.h> + +#define UART_CLK 73728000 +#include <mach/debug-uart.S> + +ENTRY(setup_lowlevel_debug) + ldr r0, =SC_CLKCTRL + ldr r1, [r0] + orr r1, r1, #SC_CLKCTRL_CEN_PERI + str r1, [r0] + + init_debug_uart r0, r1, r2 + + /* UART Port 0 */ + set_pinsel 127, 0, r0, r1 + set_pinsel 128, 0, r0, r1 + + ldr r0, =SG_LOADPINCTRL + mov r1, #1 + str r1, [r0] + + ldr r0, =SG_IECTRL + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] + + mov pc, lr +ENDPROC(setup_lowlevel_debug) diff --git a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c new file mode 100644 index 0000000..f382ef4 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sg-regs.h> + +void pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ + sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ + sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ + sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ + sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ + sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ + sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */ + sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */ + sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */ + sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */ + sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */ + sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */ + sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */ + sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */ + sg_set_pinsel(48, 0); /* NFALE -> NFALE */ + sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */ + sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */ + sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */ + sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */ + sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */ + sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */ +#endif + +#ifdef CONFIG_USB_XHCI_UNIPHIER + sg_set_pinsel(180, 0); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(181, 0); /* USB0OD -> USB0OD */ + sg_set_pinsel(182, 0); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(183, 0); /* USB1OD -> USB1OD */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */ + sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */ + sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */ + sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */ +#endif + + writel(1, SG_LOADPINCTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/platdevice.c b/arch/arm/mach-uniphier/ph1-pro4/platdevice.c new file mode 100644 index 0000000..7440ced --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/platdevice.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/platdevice.h> + +#define UART_MASTER_CLK 73728000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c new file mode 100644 index 0000000..2a965a5 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sc-regs.h> +#include <mach/sg-regs.h> + +#undef DPLL_SSC_RATE_1PER + +static void dpll_init(void) +{ + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT ( DPLLCTRL.bit[29:20] ) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~(0x000f0000); +#if CONFIG_DDR_FREQ == 1600 + tmp |= 0x000c0000; +#elif CONFIG_DDR_FREQ == 1333 + tmp |= 0x000d0000; +#else +# error "Unsupported frequency" +#endif + + /* + * Set Moduration rate + * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) + */ +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~0x00008000; +#else + tmp |= 0x00008000; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + /* Set VPLL27A & VPLL27B */ + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + +#if defined(CONFIG_MACH_PH1_PRO4) + /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) + return; +#endif + + /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Unset VPLA_K_LD and VPLB_K_LD bit */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set VPLA_M and VPLB_M to 0x20 */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) { + /* Set VPLA_K and VPLB_K for AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066666; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066666; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* wait 1 usec */ + udelay(1); + + /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Unset VPLA_SNRST and VPLB_SNRST bit */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +void pll_init(void) +{ + dpll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 1 usec in vpll_init() so 1 usec can be saved here. + */ + udelay(499); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c new file mode 100644 index 0000000..ff9c73f --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sc-regs.h> + +void enable_dpll_ssc(void) +{ + u32 tmp; + + tmp = readl(SC_DPLLCTRL); + tmp |= SC_DPLLCTRL_SSC_EN; + writel(tmp, SC_DPLLCTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c new file mode 100644 index 0000000..5e75454 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> + +void sbc_init(void) +{ + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * + * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank + * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x00000000-0x01ffffff: mask ROM + * 0x02000000-0x03efffff: memory bank (31MB) + * 0x03f00000-0x03ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c new file mode 100644 index 0000000..67e6d82 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> + +void sbc_init(void) +{ + /* XECS0: boot/sub memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); + + /* XECS1: sub/boot memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + + /* XECS3: peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); + + writel(0x0000bc01, SBBASE0); /* boot memory */ + writel(0x0400bc01, SBBASE1); /* sub memory */ + writel(0x0800bf01, SBBASE3); /* peripherals */ + + /* enable access to sub memory when boot swap is on */ + if (boot_is_swapped()) + sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ + + sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ + writel(0x00000001, SG_LOADPINCTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/sg_init.c b/arch/arm/mach-uniphier/ph1-pro4/sg_init.c new file mode 100644 index 0000000..8677666 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/sg_init.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sg-regs.h> + +void sg_init(void) +{ + u32 tmp; + + /* Input ports must be enabled before deasserting reset of cores */ + tmp = readl(SG_IECTRL); + tmp |= 1 << 6; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/umc_init.c b/arch/arm/mach-uniphier/ph1-pro4/umc_init.c new file mode 100644 index 0000000..6cbb6b2 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/umc_init.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/umc-regs.h> +#include <mach/ddrphy-regs.h> + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000001, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x07ffffff, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + + writel(0x03010100, ssif_base + UMC_HDMCHSEL); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DVCCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */ + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_HDMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_HDDRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_GIORST); + writel(0x00000001, ssif_base + UMC_HD2RST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_DVCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_VPERST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ + writel(0x66bb0f17, dramcont + UMC_CMDCTLA); + writel(0x18c6aa44, dramcont + UMC_CMDCTLB); + writel(0x5101387f, dramcont + UMC_INITCTLA); + writel(0x43030d3f, dramcont + UMC_INITCTLB); + writel(0x00ff00ff, dramcont + UMC_INITCTLC); + writel(0x00000d71, dramcont + UMC_DRMMR0); + writel(0x00000006, dramcont + UMC_DRMMR1); + writel(0x00000298, dramcont + UMC_DRMMR2); + writel(0x00000000, dramcont + UMC_DRMMR3); + writel(0x003f0617, dramcont + UMC_SPCCTLA); + writel(0x00ff0008, dramcont + UMC_SPCCTLB); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); + writel(0x04060802, dramcont + UMC_WDATACTL_D0); + writel(0x04060802, dramcont + UMC_WDATACTL_D1); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x0000000f, dramcont + 0x7000); + writel(0x0000000f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000071, dramcont + 0x8008); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x00000000, dramcont + 0x0060); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00010000, dramcont + UMC_SPCSETD); + writel(0x80000020, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000103, dramcont0 + UMC_DIOCTLA); + + ddrphy_init(phy0_1, freq, size_ch0); + + ddrphy_prepare_training(phy0_1, 1); + ddrphy_training(phy0_1); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 0); + ddrphy_training(phy1_0); + + writel(0x00000103, dramcont1 + UMC_DIOCTLA); + + ddrphy_init(phy1_1, freq, size_ch1); + + ddrphy_prepare_training(phy1_1, 1); + ddrphy_training(phy1_1); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int umc_init(void) +{ + return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, + CONFIG_SDRAM1_SIZE / 0x08000000); +} + +#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ + (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ + ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ + (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1)) +/* OK */ +#else + #error Unsupported DDR configuration. +#endif diff --git a/arch/arm/mach-uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile new file mode 100644 index 0000000..5ce3d8a --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/Makefile @@ -0,0 +1,16 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o +obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ + pll_spectrum.o umc_init.o ddrphy_init.o +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +else +obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o +obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o +endif + +obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c b/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c new file mode 100644 index 0000000..69b172e --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/bcu_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c b/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c new file mode 100644 index 0000000..d359b56 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c @@ -0,0 +1 @@ +#include "../ph1-pro4/boot-mode.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c new file mode 100644 index 0000000..8d3435d --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c new file mode 100644 index 0000000..304edfb --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/types.h> +#include <asm/io.h> +#include <mach/ddrphy-regs.h> + +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8363c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a878400, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + +#ifdef CONFIG_DDR_STANDARD + writel(0x00000000, &phy->mr3); +#else + writel(0x00000800, &phy->mr3); +#endif + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); +} diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c new file mode 100644 index 0000000..dd236b7 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/early_clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S new file mode 100644 index 0000000..73f0f63 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S @@ -0,0 +1,29 @@ +/* + * On-chip UART initializaion for low-level debugging + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> +#include <mach/sg-regs.h> + +#define UART_CLK 80000000 +#include <mach/debug-uart.S> + +ENTRY(setup_lowlevel_debug) + init_debug_uart r0, r1, r2 + + /* UART Port 0 */ + set_pinsel 70, 3, r0, r1 + set_pinsel 71, 3, r0, r1 + + ldr r0, =SG_IECTRL + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] + + mov pc, lr +ENDPROC(setup_lowlevel_debug) diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c new file mode 100644 index 0000000..4c494ff --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sg-regs.h> + +void pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ + sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ + + sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ + + sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ + sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif + +#ifdef CONFIG_SYS_I2C_UNIPHIER + { + u32 tmp; + tmp = readl(SG_IECTRL); + tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */ + writel(tmp, SG_IECTRL); + } +#endif + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */ + sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */ + sg_set_pinsel(17, 0); /* XFALE_GB -> NFALE_GB */ + sg_set_pinsel(18, 0); /* XFCLE_GB -> NFCLE_GB */ + sg_set_pinsel(19, 0); /* XNFWP_GB -> XFNWP_GB */ + sg_set_pinsel(20, 0); /* XNFCE0_GB -> XNFCE0_GB */ + sg_set_pinsel(21, 0); /* NANDRYBY0_GB -> NANDRYBY0_GB */ + sg_set_pinsel(22, 0); /* XFNCE1_GB -> XFNCE1_GB */ + sg_set_pinsel(23, 0); /* NANDRYBY1_GB -> NANDRYBY1_GB */ + sg_set_pinsel(24, 0); /* NFD0_GB -> NFD0_GB */ + sg_set_pinsel(25, 0); /* NFD1_GB -> NFD1_GB */ + sg_set_pinsel(26, 0); /* NFD2_GB -> NFD2_GB */ + sg_set_pinsel(27, 0); /* NFD3_GB -> NFD3_GB */ + sg_set_pinsel(28, 0); /* NFD4_GB -> NFD4_GB */ + sg_set_pinsel(29, 0); /* NFD5_GB -> NFD5_GB */ + sg_set_pinsel(30, 0); /* NFD6_GB -> NFD6_GB */ + sg_set_pinsel(31, 0); /* NFD7_GB -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(41, 0); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(42, 0); /* USB0OD -> USB0OD */ + sg_set_pinsel(43, 0); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(44, 0); /* USB1OD -> USB1OD */ + /* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */ + /* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */ +#endif +} diff --git a/arch/arm/mach-uniphier/ph1-sld8/platdevice.c b/arch/arm/mach-uniphier/ph1-sld8/platdevice.c new file mode 100644 index 0000000..aa334a1 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/platdevice.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/platdevice.h> + +#define UART_MASTER_CLK 80000000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) diff --git a/arch/arm/mach-uniphier/ph1-sld8/pll_init.c b/arch/arm/mach-uniphier/ph1-sld8/pll_init.c new file mode 100644 index 0000000..8851007 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/pll_init.c @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sc-regs.h> +#include <mach/sg-regs.h> + +static void dpll_init(void) +{ + u32 tmp; + /* + * Set DPLL SSC parameters for DPLLCTRL3 + * [23] DIVN_TEST 0x1 + * [22:16] DIVN 0x50 + * [10] FREFSEL_TEST 0x1 + * [9:8] FREFSEL 0x2 + * [4] ICPD_TEST 0x1 + * [3:0] ICPD 0xb + */ + tmp = readl(SC_DPLLCTRL3); + tmp &= ~0x00ff0717; + tmp |= 0x00d0061b; + writel(tmp, SC_DPLLCTRL3); + + /* + * Set DPLL SSC parameters for DPLLCTRL + * <-1%> <-2%> + * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) + * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x3ff07fff; +#ifdef CONFIG_DPLL_SSC_RATE_1PER + tmp |= 0x084018bf; +#else + tmp |= 0x084031a6; +#endif + writel(tmp, SC_DPLLCTRL); + + /* + * Set DPLL SSC parameters for DPLLCTRL2 + * [31:29] SSC_STEP 0 + * [27] SSC_REG_REF 1 + * [26:20] SSC_M 79 (0x4f) + * [19:0] SSC_K 964689 (0xeb851) + */ + tmp = readl(SC_DPLLCTRL2); + tmp &= ~0xefffffff; + tmp |= 0x0cfeb851; + writel(tmp, SC_DPLLCTRL2); +} + +static void upll_init(void) +{ + u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ + tmp = readl(SC_UPLLCTRL); + tmp &= ~0x18000000; + writel(tmp, SC_UPLLCTRL); + + if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x0228f5c0; + } else { + /* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x02328000; + } + } + + writel(tmp, SC_UPLLCTRL); + + /* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |= 0x08000000; + writel(tmp, SC_UPLLCTRL); + + /* wait 10 usec */ + udelay(10); + + /* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |= 0x10000000; + writel(tmp, SC_UPLLCTRL); +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 1 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* AXO: default 24.576MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* wait 10 usec */ + udelay(10); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* set 0 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +void pll_init(void) +{ + dpll_init(); + upll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 10 usec in upll_init() and vpll_init() + * so 20 usec can be saved here. + */ + udelay(480); +} diff --git a/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c new file mode 100644 index 0000000..9b8c485 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c @@ -0,0 +1 @@ +#include "../ph1-ld4/pll_spectrum.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c new file mode 100644 index 0000000..225c0d2 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/sbc_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c new file mode 100644 index 0000000..fdef88e --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> + +void sbc_init(void) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); + + /* + * SBCTRL0* does not need settings because PH1-sLD8 has no support for + * XECS0. The boot swap must be enabled to boot from the support card. + */ + + if (boot_is_swapped()) { + /* XECS1 : boot memory if boot swap is on */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + } + + /* XECS4 : sub memory */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44); + + /* XECS5 : peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54); + + /* base address regsiters */ + writel(0x0000bc01, SBBASE0); /* boot memory */ + writel(0x0900bfff, SBBASE1); /* dummy */ + writel(0x0400bc01, SBBASE4); /* sub memory */ + writel(0x0800bf01, SBBASE5); /* peripherals */ + + sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */ + sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */ + + /* dummy read to assure write process */ + readl(SG_PINCTRL(0)); +} diff --git a/arch/arm/mach-uniphier/ph1-sld8/sg_init.c b/arch/arm/mach-uniphier/ph1-sld8/sg_init.c new file mode 100644 index 0000000..a808289 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/sg_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/sg_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/umc_init.c b/arch/arm/mach-uniphier/ph1-sld8/umc_init.c new file mode 100644 index 0000000..302611e --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/umc_init.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/umc-regs.h> +#include <mach/ddrphy-regs.h> + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000000, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x000fffcf, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_FRCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ +#ifdef CONFIG_DDR_STANDARD + writel(0x55990b11, dramcont + UMC_CMDCTLA); + writel(0x16958944, dramcont + UMC_CMDCTLB); +#else + writel(0x45990b11, dramcont + UMC_CMDCTLA); + writel(0x16958924, dramcont + UMC_CMDCTLB); +#endif + + writel(0x5101046A, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x27028B0A, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x38028B0A, dramcont + UMC_INITCTLB); + + writel(0x00FF00FF, dramcont + UMC_INITCTLC); + writel(0x00000b51, dramcont + UMC_DRMMR0); + writel(0x00000006, dramcont + UMC_DRMMR1); + writel(0x00000290, dramcont + UMC_DRMMR2); + +#ifdef CONFIG_DDR_STANDARD + writel(0x00000000, dramcont + UMC_DRMMR3); +#else + writel(0x00000800, dramcont + UMC_DRMMR3); +#endif + + if (size == 1) + writel(0x00240512, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x00350512, dramcont + UMC_SPCCTLA); + + writel(0x00ff0006, dramcont + UMC_SPCCTLB); + writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + writel(0x04060806, dramcont + UMC_WDATACTL_D0); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x00000003, dramcont + 0x7000); + writel(0x0000004f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000077, dramcont + 0x8008); + writel(0x0000003b, dramcont + UMC_DICGCTLA); + writel(0x020a0808, dramcont + UMC_DICGCTLB); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00000000, dramcont + UMC_SPCSETD); + writel(0x00000520, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 1); + ddrphy_training(phy1_0); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int umc_init(void) +{ + return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, + CONFIG_SDRAM1_SIZE / 0x08000000); +} + +#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ + (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ + CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 +/* OK */ +#else +#error Unsupported DDR configuration. +#endif diff --git a/arch/arm/mach-uniphier/print_misc_info.c b/arch/arm/mach-uniphier/print_misc_info.c new file mode 100644 index 0000000..22ea512 --- /dev/null +++ b/arch/arm/mach-uniphier/print_misc_info.c @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/board.h> + +int misc_init_f(void) +{ + return check_support_card(); +} diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c new file mode 100644 index 0000000..005fbcf --- /dev/null +++ b/arch/arm/mach-uniphier/reset.c @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sc-regs.h> + +void reset_cpu(unsigned long ignored) +{ + u32 tmp; + + writel(5, SC_IRQTIMSET); /* default value */ + + tmp = readl(SC_SLFRSTSEL); + tmp &= ~0x3; /* mask [1:0] */ + tmp |= 0x0; /* XRST reboot */ + writel(tmp, SC_SLFRSTSEL); + + tmp = readl(SC_SLFRSTCTL); + tmp |= 0x1; + writel(tmp, SC_SLFRSTCTL); +} diff --git a/arch/arm/mach-uniphier/smp.S b/arch/arm/mach-uniphier/smp.S new file mode 100644 index 0000000..18e3a9d --- /dev/null +++ b/arch/arm/mach-uniphier/smp.S @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2013 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/system.h> +#include <mach/led.h> +#include <mach/sbc-regs.h> + +/* Entry point of U-Boot main program for the secondary CPU */ +LENTRY(secondary_entry) + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable + mcr p15, 0, r0, c1, c0, 0 + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + dsb + led_write(C,0,,) + ldr r1, =ROM_BOOT_ROMRSV2 + mov r0, #0 + str r0, [r1] +0: wfe + ldr r4, [r1] @ r4: entry point for secondary CPUs + cmp r4, #0 + beq 0b + led_write(C, P, U, 1) + bx r4 @ secondary CPUs jump to linux +ENDPROC(secondary_entry) + +ENTRY(wakeup_secondary) + ldr r1, =ROM_BOOT_ROMRSV2 +0: ldr r0, [r1] + cmp r0, #0 + bne 0b + + /* set entry address and send event to the secondary CPU */ + ldr r0, =secondary_entry + str r0, [r1] + ldr r0, [r1] @ make sure store is complete + mov r0, #0x100 +0: subs r0, r0, #1 @ I don't know the reason, but without this wait + bne 0b @ fails to wake up the secondary CPU + sev + + /* wait until the secondary CPU reach to secondary_entry */ +0: ldr r0, [r1] + cmp r0, #0 + bne 0b + bx lr +ENDPROC(wakeup_secondary) diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c new file mode 100644 index 0000000..c3d90d0 --- /dev/null +++ b/arch/arm/mach-uniphier/spl.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2013-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <linux/compiler.h> +#include <mach/led.h> +#include <mach/board.h> + +void __weak bcu_init(void) +{ +}; +void sbc_init(void); +void sg_init(void); +void pll_init(void); +void pin_init(void); +void memconf_init(void); +void early_clkrst_init(void); +int umc_init(void); +void enable_dpll_ssc(void); + +void spl_board_init(void) +{ + bcu_init(); + + sbc_init(); + + sg_init(); + + uniphier_board_reset(); + + pll_init(); + + uniphier_board_init(); + + led_write(L, 0, , ); + + memconf_init(); + + led_write(L, 1, , ); + + early_clkrst_init(); + + led_write(L, 2, , ); + + { + int res; + + res = umc_init(); + if (res < 0) { + while (1) + ; + } + } + led_write(L, 3, , ); + + enable_dpll_ssc(); + + led_write(L, 4, , ); +} diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c new file mode 100644 index 0000000..e7b4158 --- /dev/null +++ b/arch/arm/mach-uniphier/support_card.c @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/board.h> + +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) + +#define PFC_MICRO_SUPPORT_CARD_RESET \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034) +#define PFC_MICRO_SUPPORT_CARD_REVISION \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0) +/* + * 0: reset deassert, 1: reset + * + * bit[0]: LAN, I2C, LED + * bit[1]: UART + */ +void support_card_reset_deassert(void) +{ + writel(0, PFC_MICRO_SUPPORT_CARD_RESET); +} + +void support_card_reset(void) +{ + writel(3, PFC_MICRO_SUPPORT_CARD_RESET); +} + +static int support_card_show_revision(void) +{ + u32 revision; + + revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION); + printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf); + return 0; +} +#endif + +#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) + +#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x00401300) +#define DCC_MICRO_SUPPORT_CARD_RESET_UART \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x00401304) +#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x00401308) +#define DCC_MICRO_SUPPORT_CARD_REVISION \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0) + +void support_card_reset_deassert(void) +{ + writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */ + writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */ + writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */ +} + +void support_card_reset(void) +{ + writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */ + writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */ + writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */ +} + +static int support_card_show_revision(void) +{ + u32 revision; + + revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION); + + if (revision >= 0x67) { + printf("(DCC CPLD version 3.%d.%d)\n", + revision >> 4, revision & 0xf); + return 0; + } else { + printf("(DCC CPLD unknown version)\n"); + return -1; + } +} +#endif + +int check_support_card(void) +{ + printf("SC: Micro Support Card "); + return support_card_show_revision(); +} + +void support_card_init(void) +{ + /* + * After power on, we need to keep the LAN controller in reset state + * for a while. (200 usec) + * Fortunatelly, enough wait time is already inserted in pll_init() + * function. So we do not have to wait here. + */ + support_card_reset_deassert(); +} + +#if defined(CONFIG_SMC911X) +#include <netdev.h> + +int board_eth_init(bd_t *bis) +{ + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +} +#endif + +#if !defined(CONFIG_SYS_NO_FLASH) + +#include <mtd/cfi_flash.h> +#include <mach/sbc-regs.h> + +struct memory_bank { + phys_addr_t base; + unsigned long size; +}; + +static int mem_is_flash(const struct memory_bank *mem) +{ + const int loop = 128; + u32 *scratch_addr; + u32 saved_value; + int ret = 1; + int i; + + /* just in case, use the tail of the memory bank */ + scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop, + sizeof(u32) * loop, MAP_NOCACHE); + + for (i = 0; i < loop; i++, scratch_addr++) { + saved_value = readl(scratch_addr); + writel(~saved_value, scratch_addr); + if (readl(scratch_addr) != saved_value) { + /* We assume no memory or SRAM here. */ + writel(saved_value, scratch_addr); + ret = 0; + break; + } + } + + unmap_physmem(scratch_addr, MAP_NOCACHE); + + return ret; +} + +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) + /* {address, size} */ +static const struct memory_bank memory_banks_boot_swap_off[] = { + {0x02000000, 0x01f00000}, +}; + +static const struct memory_bank memory_banks_boot_swap_on[] = { + {0x00000000, 0x01f00000}, +}; +#endif + +#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +static const struct memory_bank memory_banks_boot_swap_off[] = { + {0x04000000, 0x02000000}, +}; + +static const struct memory_bank memory_banks_boot_swap_on[] = { + {0x00000000, 0x02000000}, + {0x04000000, 0x02000000}, +}; +#endif + +static const struct memory_bank +*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; + +phys_addr_t cfi_flash_bank_addr(int i) +{ + return flash_banks_list[i]->base; +} + +unsigned long cfi_flash_bank_size(int i) +{ + return flash_banks_list[i]->size; +} + +static void detect_num_flash_banks(void) +{ + const struct memory_bank *memory_bank, *end; + + cfi_flash_num_flash_banks = 0; + + if (boot_is_swapped()) { + memory_bank = memory_banks_boot_swap_on; + end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on); + } else { + memory_bank = memory_banks_boot_swap_off; + end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off); + } + + for (; memory_bank < end; memory_bank++) { + if (cfi_flash_num_flash_banks >= + CONFIG_SYS_MAX_FLASH_BANKS_DETECT) + break; + + if (mem_is_flash(memory_bank)) { + flash_banks_list[cfi_flash_num_flash_banks] = + memory_bank; + + debug("flash bank found: base = 0x%lx, size = 0x%lx\n", + memory_bank->base, memory_bank->size); + cfi_flash_num_flash_banks++; + } + } + + debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); +} +#else /* ONFIG_SYS_NO_FLASH */ +void detect_num_flash_banks(void) +{ +}; +#endif /* ONFIG_SYS_NO_FLASH */ + +void support_card_late_init(void) +{ + detect_num_flash_banks(); +} diff --git a/arch/arm/mach-uniphier/timer.c b/arch/arm/mach-uniphier/timer.c new file mode 100644 index 0000000..adef08d --- /dev/null +++ b/arch/arm/mach-uniphier/timer.c @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/arm-mpcore.h> + +#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ +#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) + +static void *get_global_timer_base(void) +{ + void *val; + + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory"); + + return val + GLOBAL_TIMER_OFFSET; +} + +unsigned long timer_read_counter(void) +{ + /* + * ARM 64bit Global Timer is too much for our purpose. + * We use only lower 32 bit of the timer counter. + */ + return readl(get_global_timer_base() + GTIMER_CNT_L); +} + +int timer_init(void) +{ + /* enable timer */ + writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL); + + return 0; +} |