diff options
Diffstat (limited to 'arch/arm/mach-uniphier/dram/ddrphy-ld4.c')
-rw-r--r-- | arch/arm/mach-uniphier/dram/ddrphy-ld4.c | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ld4.c index c9e164f..620668e 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ld4.c @@ -1,14 +1,15 @@ /* - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <linux/err.h> -#include <linux/types.h> #include <linux/io.h> +#include "ddrphy-init.h" #include "ddrphy-regs.h" enum dram_freq { @@ -27,8 +28,7 @@ static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8}; static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71}; static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298}; -int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, - bool ddr3plus) +int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus) { enum dram_freq freq_e; u32 tmp; @@ -45,34 +45,34 @@ int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, return -EINVAL; } - writel(0x0300c473, &phy->pgcr[1]); - writel(ddrphy_ptr0[freq_e], &phy->ptr[0]); - writel(ddrphy_ptr1[freq_e], &phy->ptr[1]); - writel(0x00083DEF, &phy->ptr[2]); - writel(ddrphy_ptr3[freq_e], &phy->ptr[3]); - writel(ddrphy_ptr4[freq_e], &phy->ptr[4]); - writel(0xF004001A, &phy->dsgcr); + writel(0x0300c473, phy_base + PHY_PGCR1); + writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0); + writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1); + writel(0x00083DEF, phy_base + PHY_PTR2); + writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3); + writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4); + writel(0xF004001A, phy_base + PHY_DSGCR); /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); + tmp = readl(phy_base + PHY_DXCCR); tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); + tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM; + writel(tmp, phy_base + PHY_DXCCR); - writel(0x0000040B, &phy->dcr); - writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]); - writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]); - writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]); - writel(ddrphy_mr0[freq_e], &phy->mr0); - writel(0x00000006, &phy->mr1); - writel(ddrphy_mr2[freq_e], &phy->mr2); - writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3); + writel(0x0000040B, phy_base + PHY_DCR); + writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0); + writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1); + writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2); + writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0); + writel(0x00000006, phy_base + PHY_MR1); + writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2); + writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3); - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) ; - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); + writel(0x0300C473, phy_base + PHY_PGCR1); + writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1); return 0; } |