diff options
Diffstat (limited to 'arch/arm/mach-stm32/stm32f7/clock.c')
| -rw-r--r-- | arch/arm/mach-stm32/stm32f7/clock.c | 171 |
1 files changed, 81 insertions, 90 deletions
diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c index 78d22d4..e1ee173 100644 --- a/arch/arm/mach-stm32/stm32f7/clock.c +++ b/arch/arm/mach-stm32/stm32f7/clock.c @@ -11,76 +11,50 @@ #include <asm/arch/stm32.h> #include <asm/arch/stm32_periph.h> -#define RCC_CR_HSION (1 << 0) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_HSION BIT(0) +#define RCC_CR_HSEON BIT(16) +#define RCC_CR_HSERDY BIT(17) +#define RCC_CR_HSEBYP BIT(18) +#define RCC_CR_CSSON BIT(19) +#define RCC_CR_PLLON BIT(24) +#define RCC_CR_PLLRDY BIT(25) -#define RCC_PLLCFGR_PLLM_MASK 0x3F -#define RCC_PLLCFGR_PLLN_MASK 0x7FC0 -#define RCC_PLLCFGR_PLLP_MASK 0x30000 -#define RCC_PLLCFGR_PLLQ_MASK 0xF000000 -#define RCC_PLLCFGR_PLLSRC (1 << 22) -#define RCC_PLLCFGR_PLLM_SHIFT 0 -#define RCC_PLLCFGR_PLLN_SHIFT 6 -#define RCC_PLLCFGR_PLLP_SHIFT 16 -#define RCC_PLLCFGR_PLLQ_SHIFT 24 +#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0) +#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6) +#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16) +#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24) +#define RCC_PLLCFGR_PLLSRC BIT(22) +#define RCC_PLLCFGR_PLLM_SHIFT 0 +#define RCC_PLLCFGR_PLLN_SHIFT 6 +#define RCC_PLLCFGR_PLLP_SHIFT 16 +#define RCC_PLLCFGR_PLLQ_SHIFT 24 -#define RCC_CFGR_AHB_PSC_MASK 0xF0 -#define RCC_CFGR_APB1_PSC_MASK 0x1C00 -#define RCC_CFGR_APB2_PSC_MASK 0xE000 -#define RCC_CFGR_SW0 (1 << 0) -#define RCC_CFGR_SW1 (1 << 1) -#define RCC_CFGR_SW_MASK 0x3 -#define RCC_CFGR_SW_HSI 0 -#define RCC_CFGR_SW_HSE RCC_CFGR_SW0 -#define RCC_CFGR_SW_PLL RCC_CFGR_SW1 -#define RCC_CFGR_SWS0 (1 << 2) -#define RCC_CFGR_SWS1 (1 << 3) -#define RCC_CFGR_SWS_MASK 0xC -#define RCC_CFGR_SWS_HSI 0 -#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 -#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_PPRE1_SHIFT 10 -#define RCC_CFGR_PPRE2_SHIFT 13 - -#define RCC_APB1ENR_PWREN (1 << 28) - -/* - * RCC USART specific definitions - */ -#define RCC_ENR_USART1EN (1 << 4) -#define RCC_ENR_USART2EN (1 << 17) -#define RCC_ENR_USART3EN (1 << 18) -#define RCC_ENR_USART6EN (1 << 5) +#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) +#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10) +#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13) +#define RCC_CFGR_SW0 BIT(0) +#define RCC_CFGR_SW1 BIT(1) +#define RCC_CFGR_SW_MASK GENMASK(1, 0) +#define RCC_CFGR_SW_HSI 0 +#define RCC_CFGR_SW_HSE RCC_CFGR_SW0 +#define RCC_CFGR_SW_PLL RCC_CFGR_SW1 +#define RCC_CFGR_SWS0 BIT(2) +#define RCC_CFGR_SWS1 BIT(3) +#define RCC_CFGR_SWS_MASK GENMASK(3, 2) +#define RCC_CFGR_SWS_HSI 0 +#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 +#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_PPRE1_SHIFT 10 +#define RCC_CFGR_PPRE2_SHIFT 13 /* * Offsets of some PWR registers */ -#define PWR_CR1_ODEN (1 << 16) -#define PWR_CR1_ODSWEN (1 << 17) -#define PWR_CSR1_ODRDY (1 << 16) -#define PWR_CSR1_ODSWRDY (1 << 17) - - -/* - * RCC GPIO specific definitions - */ -#define RCC_ENR_GPIO_A_EN (1 << 0) -#define RCC_ENR_GPIO_B_EN (1 << 1) -#define RCC_ENR_GPIO_C_EN (1 << 2) -#define RCC_ENR_GPIO_D_EN (1 << 3) -#define RCC_ENR_GPIO_E_EN (1 << 4) -#define RCC_ENR_GPIO_F_EN (1 << 5) -#define RCC_ENR_GPIO_G_EN (1 << 6) -#define RCC_ENR_GPIO_H_EN (1 << 7) -#define RCC_ENR_GPIO_I_EN (1 << 8) -#define RCC_ENR_GPIO_J_EN (1 << 9) -#define RCC_ENR_GPIO_K_EN (1 << 10) +#define PWR_CR1_ODEN BIT(16) +#define PWR_CR1_ODSWEN BIT(17) +#define PWR_CSR1_ODRDY BIT(16) +#define PWR_CSR1_ODSWRDY BIT(17) struct pll_psc { u8 pll_m; @@ -92,21 +66,21 @@ struct pll_psc { u8 apb2_psc; }; -#define AHB_PSC_1 0 -#define AHB_PSC_2 0x8 -#define AHB_PSC_4 0x9 -#define AHB_PSC_8 0xA -#define AHB_PSC_16 0xB -#define AHB_PSC_64 0xC -#define AHB_PSC_128 0xD -#define AHB_PSC_256 0xE -#define AHB_PSC_512 0xF +#define AHB_PSC_1 0 +#define AHB_PSC_2 0x8 +#define AHB_PSC_4 0x9 +#define AHB_PSC_8 0xA +#define AHB_PSC_16 0xB +#define AHB_PSC_64 0xC +#define AHB_PSC_128 0xD +#define AHB_PSC_256 0xE +#define AHB_PSC_512 0xF -#define APB_PSC_1 0 -#define APB_PSC_2 0x4 -#define APB_PSC_4 0x5 -#define APB_PSC_8 0x6 -#define APB_PSC_16 0x7 +#define APB_PSC_1 0 +#define APB_PSC_2 0x4 +#define APB_PSC_4 0x5 +#define APB_PSC_8 0x6 +#define APB_PSC_16 0x7 #if !defined(CONFIG_STM32_HSE_HZ) #error "CONFIG_STM32_HSE_HZ not defined!" @@ -243,40 +217,57 @@ void clock_setup(int peripheral) { switch (peripheral) { case USART1_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN); + setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_USART1EN); break; case GPIO_A_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN); break; case GPIO_B_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN); break; case GPIO_C_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN); break; case GPIO_D_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN); break; case GPIO_E_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN); break; case GPIO_F_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN); break; case GPIO_G_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN); break; case GPIO_H_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN); break; case GPIO_I_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN); break; case GPIO_J_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN); break; case GPIO_K_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN); + break; + case SYSCFG_CLOCK_CFG: + setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); + break; + case TIMER2_CLOCK_CFG: + setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); + break; + case FMC_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN); + break; + case STMMAC_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN); + break; + case QSPI_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_QSPI_EN); break; default: break; |