diff options
Diffstat (limited to 'arch/arm/mach-keystone')
| -rw-r--r-- | arch/arm/mach-keystone/ddr3.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-keystone/include/mach/hardware.h | 4 |
2 files changed, 15 insertions, 1 deletions
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index dfb27b5..34606f4 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -52,7 +52,8 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); - __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); + if (!cpu_is_k2g()) + __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); @@ -64,6 +65,15 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) ; + /* Disable ECC for K2G */ + if (cpu_is_k2g()) { + clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1); + } + __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) ; diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index a99713a..2fd5b23 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -52,6 +52,10 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4 #define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4 +#define KS2_DDRPHY_DATX8_4_OFFSET 0x2C0 +#define KS2_DDRPHY_DATX8_5_OFFSET 0x300 +#define KS2_DDRPHY_DATX8_6_OFFSET 0x340 +#define KS2_DDRPHY_DATX8_7_OFFSET 0x380 #define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0 #define IODDRM_MASK 0x00000180 |