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-rw-r--r--arch/arm/mach-keystone/include/mach/clock-k2e.h1
-rw-r--r--arch/arm/mach-keystone/include/mach/clock.h2
-rw-r--r--arch/arm/mach-keystone/include/mach/clock_defs.h68
3 files changed, 64 insertions, 7 deletions
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index d013b83..68e15ac 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
@@ -55,6 +55,7 @@ enum pll_type_e {
CORE_PLL,
PASS_PLL,
DDR3_PLL,
+ TETRIS_PLL,
};
enum {
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index 9f6cfb2..8d4cad2 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -52,13 +52,13 @@ struct pll_init_data {
extern const struct keystone_pll_regs keystone_pll_regs[];
extern int dev_speeds[];
extern int arm_speeds[];
+extern s16 divn_val[];
void init_plls(int num_pll, struct pll_init_data *config);
void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
-void pass_pll_pa_clk_enable(void);
int get_max_dev_speed(void);
int get_max_arm_speed(void);
diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h
index 85a046b..1c9dc3e 100644
--- a/arch/arm/mach-keystone/include/mach/clock_defs.h
+++ b/arch/arm/mach-keystone/include/mach/clock_defs.h
@@ -69,7 +69,6 @@ static struct pllctl_regs *pllctl_regs[] = {
#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
-/* PLLCTL Bits */
#define PLLCTL_BYPASS BIT(23)
#define PLL_PLLRST BIT(14)
#define PLLCTL_PAPLL BIT(13)
@@ -102,10 +101,67 @@ static struct pllctl_regs *pllctl_regs[] = {
#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
#define PLL_BWADJ_HI_MASK 0xf
-#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1)
-#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4)
-#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17)
+/* PLLCTL Bits */
+#define PLLCTL_PLLENSRC_SHIF 5
+#define PLLCTL_PLLENSRC_MASK BIT(5)
+#define PLLCTL_PLLRST_SHIFT 3
+#define PLLCTL_PLLRST_MASK BIT(3)
+#define PLLCTL_PLLPWRDN_SHIFT 1
+#define PLLCTL_PLLPWRDN_MASK BIT(1)
+#define PLLCTL_PLLEN_SHIFT 0
+#define PLLCTL_PLLEN_MASK BIT(0)
+
+/* SECCTL Bits */
+#define SECCTL_BYPASS_SHIFT 23
+#define SECCTL_BYPASS_MASK BIT(23)
+#define SECCTL_OP_DIV_SHIFT 19
+#define SECCTL_OP_DIV_MASK (0xf << 19)
+
+/* PLLM Bits */
+#define PLLM_MULT_LO_SHIFT 0
+#define PLLM_MULT_LO_MASK 0x3f
+#define PLLM_MULT_LO_BITS 6
+
+/* PLLDIVn Bits */
+#define PLLDIV_ENABLE_SHIFT 15
+#define PLLDIV_ENABLE_MASK BIT(15)
+#define PLLDIV_RATIO_SHIFT 0x0
+#define PLLDIV_RATIO_MASK 0xff
+#define PLLDIV_MAX 16
+
+/* PLLCMD Bits */
+#define PLLCMD_GOSET_SHIFT 0
+#define PLLCMD_GOSET_MASK BIT(0)
+
+/* PLLSTAT Bits */
+#define PLLSTAT_GOSTAT_SHIFT 0
+#define PLLSTAT_GOSTAT_MASK BIT(0)
+
+/* Device Config PLLCTL0 */
+#define CFG_PLLCTL0_BWADJ_SHIFT 24
+#define CFG_PLLCTL0_BWADJ_MASK (0xff << 24)
+#define CFG_PLLCTL0_BWADJ_BITS 8
+#define CFG_PLLCTL0_BYPASS_SHIFT 23
+#define CFG_PLLCTL0_BYPASS_MASK BIT(23)
+#define CFG_PLLCTL0_CLKOD_SHIFT 19
+#define CFG_PLLCTL0_CLKOD_MASK (0xf << 19)
+#define CFG_PLLCTL0_PLLM_HI_SHIFT 12
+#define CFG_PLLCTL0_PLLM_HI_MASK (0x7f << 12)
+#define CFG_PLLCTL0_PLLM_SHIFT 6
+#define CFG_PLLCTL0_PLLM_MASK (0x1fff << 6)
+#define CFG_PLLCTL0_PLLD_SHIFT 0
+#define CFG_PLLCTL0_PLLD_MASK 0x3f
+
+/* Device Config PLLCTL1 */
+#define CFG_PLLCTL1_RST_SHIFT 14
+#define CFG_PLLCTL1_RST_MASK BIT(14)
+#define CFG_PLLCTL1_PAPLL_SHIFT 13
+#define CFG_PLLCTL1_PAPLL_MASK BIT(13)
+#define CFG_PLLCTL1_ENSAT_SHIFT 6
+#define CFG_PLLCTL1_ENSAT_MASK BIT(6)
+#define CFG_PLLCTL1_BWADJ_SHIFT 0
+#define CFG_PLLCTL1_BWADJ_MASK 0xf
+
+#define MISC_CTL1_ARM_PLL_EN BIT(13)
#endif /* _CLOCK_DEFS_H_ */