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Diffstat (limited to 'arch/arm/mach-exynos/dmc_init_ddr3.c')
-rw-r--r--arch/arm/mach-exynos/dmc_init_ddr3.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c
index 25a9df9..6a5d26c 100644
--- a/arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/arch/arm/mach-exynos/dmc_init_ddr3.c
@@ -618,7 +618,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
/*
* Send NOP, MRS and ZQINIT commands
* Sending MRS command will reset the DRAM. We should not be
- * reseting the DRAM after resume, this will lead to memory
+ * resetting the DRAM after resume, this will lead to memory
* corruption as DRAM content is lost after DRAM reset
*/
dmc_config_mrs(mem, &drex0->directcmd);