diff options
Diffstat (limited to 'arch/arm/mach-at91/include')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_pmc.h | 16 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_rtc.h | 71 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_sck.h | 21 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sama5_boot.h | 25 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sama5d2.h | 12 |
6 files changed, 126 insertions, 20 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 7684f09..680ceb0 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -67,18 +67,18 @@ typedef struct at91_pmc { #define AT91_PMC_MOR_MOSCEN 0x01 #define AT91_PMC_MOR_OSCBYPASS 0x02 #define AT91_PMC_MOR_MOSCRCEN 0x08 -#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) -#define AT91_PMC_MOR_KEY(x) ((x & 0xff) << 16) +#define AT91_PMC_MOR_OSCOUNT(x) (((x) & 0xff) << 8) +#define AT91_PMC_MOR_KEY(x) (((x) & 0xff) << 16) #define AT91_PMC_MOR_MOSCSEL (1 << 24) -#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) -#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) -#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) +#define AT91_PMC_PLLXR_DIV(x) ((x) & 0xFF) +#define AT91_PMC_PLLXR_PLLCOUNT(x) (((x) & 0x3F) << 8) +#define AT91_PMC_PLLXR_OUT(x) (((x) & 0x03) << 14) #if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \ defined(CONFIG_SAMA5D4) -#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18) +#define AT91_PMC_PLLXR_MUL(x) (((x) & 0x7F) << 18) #else -#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) +#define AT91_PMC_PLLXR_MUL(x) (((x) & 0x7FF) << 16) #endif #define AT91_PMC_PLLAR_29 0x20000000 #define AT91_PMC_PLLBR_USBDIV_1 0x00000000 @@ -158,7 +158,7 @@ typedef struct at91_pmc { #define AT91_PMC_PCR_CMD_WRITE (0x1 << 12) #define AT91_PMC_PCR_DIV (0x3 << 16) #define AT91_PMC_PCR_GCKDIV (0xff << 20) -#define AT91_PMC_PCR_GCKDIV_(x) ((x & 0xff) << 20) +#define AT91_PMC_PCR_GCKDIV_(x) (((x) & 0xff) << 20) #define AT91_PMC_PCR_GCKDIV_OFFSET 20 #define AT91_PMC_PCR_EN (0x1 << 28) #define AT91_PMC_PCR_GCKEN (0x1 << 29) diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h new file mode 100644 index 0000000..73070e3 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_rtc.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Real Time Clock (RTC) - System peripheral registers. + * Based on AT91RM9200 datasheet revision E. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef AT91_RTC_H +#define AT91_RTC_H + +/* Control Register */ +#define AT91_RTC_CR (ATMEL_BASE_RTC + 0x00) +#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time */ +#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar */ +#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ +#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) +#define AT91_RTC_TIMEVSEL_HOUR (1 << 8) +#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) +#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) +#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ +#define AT91_RTC_CALEVSEL_WEEK (0 << 16) +#define AT91_RTC_CALEVSEL_MONTH (1 << 16) +#define AT91_RTC_CALEVSEL_YEAR (2 << 16) + +#define AT91_RTC_MR (ATMEL_BASE_RTC + 0x04) /* Mode Register */ +#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ + +#define AT91_RTC_TIMR (ATMEL_BASE_RTC + 0x08) /* Time Register */ +#define AT91_RTC_SEC (0x7f << 0) /* Current Second */ +#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ +#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ +#define AT91_RTC_AMPM (1 << 22) /* AM/PM */ + +#define AT91_RTC_CALR (ATMEL_BASE_RTC + 0x0c) /* Calendar Register */ +#define AT91_RTC_CENT (0x7f << 0) /* Current Century */ +#define AT91_RTC_YEAR (0xff << 8) /* Current Year */ +#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ +#define AT91_RTC_DAY (7 << 21) /* Current Day */ +#define AT91_RTC_DATE (0x3f << 24) /* Current Date */ + +#define AT91_RTC_TIMALR (ATMEL_BASE_RTC + 0x10) /* Time Alarm */ +#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enab */ +#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enab */ +#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ + +#define AT91_RTC_CALALR (ATMEL_BASE_RTC + 0x14) /* Calendar Alarm */ +#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ +#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ + +#define AT91_RTC_SR (ATMEL_BASE_RTC + 0x18) /* Status Register */ +#define AT91_RTC_ACKUPD (1 << 0) /* Ack for Update */ +#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ +#define AT91_RTC_SECEV (1 << 2) /* Second Event */ +#define AT91_RTC_TIMEV (1 << 3) /* Time Event */ +#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ + +#define AT91_RTC_SCCR (ATMEL_BASE_RTC + 0x1c) /* Status Clear Cmd */ +#define AT91_RTC_IER (ATMEL_BASE_RTC + 0x20) /* Interrupt Enable */ +#define AT91_RTC_IDR (ATMEL_BASE_RTC + 0x24) /* Interrupt Disable */ +#define AT91_RTC_IMR (ATMEL_BASE_RTC + 0x28) /* Interrupt Mask */ + +#define AT91_RTC_VER (ATMEL_BASE_RTC + 0x2c) /* Valid Entry */ +#define AT91_RTC_NVTIM (1 << 0) /* Non-valid Time */ +#define AT91_RTC_NVCAL (1 << 1) /* Non-valid Calendar */ +#define AT91_RTC_NVTIMALR (1 << 2) /* .. Time Alarm */ +#define AT91_RTC_NVCALALR (1 << 3) /* .. Calendar Alarm */ + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91_sck.h b/arch/arm/mach-at91/include/mach/at91_sck.h new file mode 100644 index 0000000..ce8e577 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_sck.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef AT91_SCK_H +#define AT91_SCK_H + +/* + * SCKCR flags + */ +#define AT91SAM9G45_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */ +#define AT91SAM9G45_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */ +#define AT91SAM9G45_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */ +#define AT91SAM9G45_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */ +#define AT91SAM9G45_SCKCR_OSCSEL_RC (0 << 3) +#define AT91SAM9G45_SCKCR_OSCSEL_32 (1 << 3) + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index cf1c73f..5c32e24 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -109,6 +109,7 @@ #define ATMEL_BASE_RTT 0xfffffd20 #define ATMEL_BASE_PIT 0xfffffd30 #define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_SCKCR 0xfffffd50 #define ATMEL_BASE_GPBR 0xfffffd60 #define ATMEL_BASE_RTC 0xfffffdb0 /* Reserved: 0xfffffdc0 - 0xffffffff */ diff --git a/arch/arm/mach-at91/include/mach/sama5_boot.h b/arch/arm/mach-at91/include/mach/sama5_boot.h new file mode 100644 index 0000000..8911a44 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5_boot.h @@ -0,0 +1,25 @@ +/* + * Boot mode definitions for the SAMA5Dx SoC + * + * Copyright (C) 2016 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SAMA5_BOOT_H +#define __SAMA5_BOOT_H + +/* Boot modes stored by BootROM in r4 */ +#define ATMEL_SAMA5_BOOT_FROM_OFF 0 +#define ATMEL_SAMA5_BOOT_FROM_MASK 0xf +#define ATMEL_SAMA5_BOOT_FROM_SPI (0 << 0) +#define ATMEL_SAMA5_BOOT_FROM_MCI (1 << 0) +#define ATMEL_SAMA5_BOOT_FROM_SMC (2 << 0) +#define ATMEL_SAMA5_BOOT_FROM_TWI (3 << 0) +#define ATMEL_SAMA5_BOOT_FROM_QSPI (4 << 0) +#define ATMEL_SAMA5_BOOT_FROM_SAMBA (7 << 0) + +#define ATMEL_SAMA5_BOOT_DEV_ID_OFF 4 +#define ATMEL_SAMA5_BOOT_DEV_ID_MASK 0xf + +#endif /* __SAMA5_BOOT_H */ diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index ee841da..25c8541 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -230,18 +230,6 @@ /* No PMECC Galois table in ROM */ #define NO_GALOIS_TABLE_IN_ROM -/* Boot modes stored by BootROM in r4 */ -#define ATMEL_SAMA5D2_BOOT_FROM_OFF 0 -#define ATMEL_SAMA5D2_BOOT_FROM_MASK 0xf -#define ATMEL_SAMA5D2_BOOT_FROM_SPI (0 << 0) -#define ATMEL_SAMA5D2_BOOT_FROM_MCI (1 << 0) -#define ATMEL_SAMA5D2_BOOT_FROM_SMC (2 << 0) -#define ATMEL_SAMA5D2_BOOT_FROM_TWI (3 << 0) -#define ATMEL_SAMA5D2_BOOT_FROM_QSPI (4 << 0) - -#define ATMEL_SAMA5D2_BOOT_DEV_ID_OFF 4 -#define ATMEL_SAMA5D2_BOOT_DEV_ID_MASK 0xf - #ifndef __ASSEMBLY__ unsigned int get_chip_id(void); unsigned int get_extension_chip_id(void); |