4 files changed, 33 insertions, 16 deletions

diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 14a56f6..a7fb251 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -275,10 +275,6 @@ void board_init_f(ulong bootflag)
 
 	gd->mon_len = _bss_end_ofs;
 
-#ifdef CONFIG_MACH_TYPE
-	gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
-#endif
-
 	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
 		if ((*init_fnc_ptr)() != 0) {
 			hang ();
@@ -376,6 +372,11 @@ void board_init_f(ulong bootflag)
 	gd->bd = bd;
 	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
 			sizeof (bd_t), addr_sp);
+
+#ifdef CONFIG_MACH_TYPE
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
+#endif
+
 	addr_sp -= sizeof (gd_t);
 	id = (gd_t *) addr_sp;
 	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
@@ -451,11 +452,9 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
 	monitor_flash_len = _end_ofs;
-	/*
-	 * Enable D$:
-	 * I$, if needed, must be already enabled in start.S
-	 */
-	dcache_enable();
+
+	/* Enable caches */
+	enable_caches();
 
 	debug("monitor flash len: %08lX\n", monitor_flash_len);
 	board_init();	/* Setup chipselects */
@@ -626,7 +625,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
 		pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
 #endif
 #endif
-		sprintf((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
+		sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
 		setenv("mem", (char *)memsz);
 	}
 #endif
diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
index 36c629c..21d13f7 100644
--- a/arch/arm/lib/cache-pl310.c
+++ b/arch/arm/lib/cache-pl310.c
@@ -26,6 +26,7 @@
 #include <asm/armv7.h>
 #include <asm/pl310.h>
 #include <config.h>
+#include <common.h>
 
 struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
@@ -89,21 +90,23 @@ void v7_outer_cache_inval_range(u32 start, u32 stop)
 	u32 pa, line_size = 32;
 
 	/*
-	 * If start address is not aligned to cache-line flush the first
-	 * line to prevent affecting somebody else's buffer
+	 * If start address is not aligned to cache-line do not
+	 * invalidate the first cache-line
 	 */
 	if (start & (line_size - 1)) {
-		v7_outer_cache_flush_range(start, start + 1);
+		printf("ERROR: %s - start address is not aligned - 0x%08x\n",
+			__func__, start);
 		/* move to next cache line */
 		start = (start + line_size - 1) & ~(line_size - 1);
 	}
 
 	/*
-	 * If stop address is not aligned to cache-line flush the last
-	 * line to prevent affecting somebody else's buffer
+	 * If stop address is not aligned to cache-line do not
+	 * invalidate the last cache-line
 	 */
 	if (stop & (line_size - 1)) {
-		v7_outer_cache_flush_range(stop, stop + 1);
+		printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
+			__func__, stop);
 		/* align to the beginning of this cache line */
 		stop &= ~(line_size - 1);
 	}
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..b545fb7 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -53,3 +53,15 @@ void	__flush_dcache_all(void)
 }
 void	flush_dcache_all(void)
 	__attribute__((weak, alias("__flush_dcache_all")));
+
+
+/*
+ * Default implementation of enable_caches()
+ * Real implementation should be in platform code
+ */
+void __enable_caches(void)
+{
+	puts("WARNING: Caches not enabled\n");
+}
+void enable_caches(void)
+	__attribute__((weak, alias("__enable_caches")));
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index 3b5aeec..f655256 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -60,6 +60,9 @@
 .globl memcpy
 memcpy:
 
+		cmp	r0, r1
+		moveq	pc, lr
+
 		enter	r4, lr
 
 		subs	r2, r2, #4