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-rw-r--r--arch/arm/include/asm/arch-pxa/macro.h328
-rw-r--r--arch/arm/include/asm/arch-s3c24x0/s3c2440.h161
-rw-r--r--arch/arm/include/asm/arch-s3c24x0/s3c24x0.h672
-rw-r--r--arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h2
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/mmc.h2
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/uart.h14
-rw-r--r--arch/arm/include/asm/config.h3
-rw-r--r--arch/arm/include/asm/global_data.h2
-rw-r--r--arch/arm/include/asm/u-boot-arm.h6
9 files changed, 550 insertions, 640 deletions
diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h
deleted file mode 100644
index 85958dd..0000000
--- a/arch/arm/include/asm/arch-pxa/macro.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * arch/arm/include/asm/arch-pxa/macro.h
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_PXA_MACRO_H__
-#define __ASM_ARCH_PXA_MACRO_H__
-#ifdef __ASSEMBLY__
-
-#include <asm/macro.h>
-#include <asm/arch/pxa-regs.h>
-
-/*
- * This macro performs a 32bit write to a memory location and makes sure the
- * write operation really happened by performing a read back.
- *
- * Clobbered regs: r4, r5
- */
-.macro write32rb addr, data
- ldr r4, =\addr
- ldr r5, =\data
- str r5, [r4]
- ldr r5, [r4]
-.endm
-
-/*
- * This macro waits according to OSCR incrementation
- *
- * Clobbered regs: r4, r5, r6
- */
-.macro pxa_wait_ticks ticks
- ldr r4, =OSCR
- mov r5, #0
- str r5, [r4]
- ldr r5, =\ticks
-1:
- ldr r6, [r4]
- cmp r5, r6
- bgt 1b
-.endm
-
-/*
- * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
- *
- * Clobbered regs: r4, r5
- */
-.macro pxa_gpio_setup
- write32 GPSR0, CONFIG_SYS_GPSR0_VAL
- write32 GPSR1, CONFIG_SYS_GPSR1_VAL
- write32 GPSR2, CONFIG_SYS_GPSR2_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- write32 GPSR3, CONFIG_SYS_GPSR3_VAL
-#endif
-
- write32 GPCR0, CONFIG_SYS_GPCR0_VAL
- write32 GPCR1, CONFIG_SYS_GPCR1_VAL
- write32 GPCR2, CONFIG_SYS_GPCR2_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- write32 GPCR3, CONFIG_SYS_GPCR3_VAL
-#endif
-
- write32 GPDR0, CONFIG_SYS_GPDR0_VAL
- write32 GPDR1, CONFIG_SYS_GPDR1_VAL
- write32 GPDR2, CONFIG_SYS_GPDR2_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- write32 GPDR3, CONFIG_SYS_GPDR3_VAL
-#endif
-
- write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
- write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
- write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
- write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
- write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
- write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
- write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
-#endif
-
- write32 PSSR, CONFIG_SYS_PSSR_VAL
-.endm
-
-/*
- * This macro sets up the Memory controller of the PXA2xx CPU
- *
- * WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE
- * and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not
- * use this regs for other purpose inside this macro.
- *
- * Clobbered regs: r3, r4, r5, r6, r7
- */
-.macro pxa_mem_setup
- /* This comes handy when setting MDREFR */
- ldr r3, =MEMC_BASE
-
- /*
- * 1) Initialize Asynchronous static memory controller
- */
-
- /* MSC0: nCS(0,1) */
- write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
- /* MSC1: nCS(2,3) */
- write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
- /* MSC2: nCS(4,5) */
- write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
-
- /*
- * 2) Initialize Card Interface
- */
-
- /* MECR: Memory Expansion Card Register */
- write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
- /* MCMEM0: Card Interface slot 0 timing */
- write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
- /* MCMEM1: Card Interface slot 1 timing */
- write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
-
- /*
- * 3) Configure Fly-By DMA register
- */
-
- write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
-
- /*
- * 4) Initialize Timing for Sync Memory (SDCLK0)
- */
-
- /*
- * Before accessing MDREFR we need a valid DRI field, so we set
- * this to power on defaults + DRI field.
- */
- ldr r5, [r3, #MDREFR_OFFSET]
- bic r5, r5, #0x0ff
- bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- mov r7, r4
- lsl r4, #20
- lsr r4, #20 /* Get a valid DRI field */
-
- orr r5, r5, r4 /* MDREFR user config with correct DRI */
-
- orr r5, #MDREFR_K0RUN
- orr r5, #MDREFR_SLFRSH
- bic r5, #MDREFR_APD
- bic r5, #MDREFR_E1PIN
-
- str r5, [r3, #MDREFR_OFFSET]
- ldr r4, [r3, #MDREFR_OFFSET]
-
- /*
- * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
- */
-
- /* Initialize SXCNFG register. Assert the enable bits.
- *
- * Write SXMRS to cause an MRS command to all enabled banks of
- * synchronous static memory. Note that SXLCR need not be written
- * at this time.
- */
- write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
-
- /*
- * 6) Initialize SDRAM
- */
-
- bic r7, #MDREFR_SLFRSH
- str r7, [r3, #MDREFR_OFFSET]
- ldr r4, [r3, #MDREFR_OFFSET]
-
- orr r7, #MDREFR_E1PIN
- str r7, [r3, #MDREFR_OFFSET]
- ldr r4, [r3, #MDREFR_OFFSET]
-
- /*
- * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
- * but not enable each SDRAM partition pair.
- */
-
- /* Fetch platform value of MDCNFG */
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- /* Disable all sdram banks */
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
- /* Write initial value of MDCNFG, w/o enabling sdram banks */
- str r4, [r3, #MDCNFG_OFFSET]
- ldr r4, [r3, #MDCNFG_OFFSET]
-
- /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
- pxa_wait_ticks 0x300
-
- /*
- * 8) Trigger a number (usually 8) refresh cycles by attempting
- * non-burst read or write accesses to disabled SDRAM, as commonly
- * specified in the power up sequence documented in SDRAM data
- * sheets. The address(es) used for this purpose must not be
- * cacheable.
- */
-
- ldr r4, =CONFIG_SYS_DRAM_BASE
-.rept 9
- str r5, [r4]
-.endr
-
- /*
- * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
- */
-
- ldr r5, =CONFIG_SYS_MDCNFG_VAL
- ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
- and r5, r5, r4
- ldr r4, [r3, #MDCNFG_OFFSET]
- orr r4, r4, r5
- str r4, [r3, #MDCNFG_OFFSET]
- ldr r4, [r3, #MDCNFG_OFFSET]
-
- /*
- * 10) Write MDMRS.
- */
-
- ldr r4, =CONFIG_SYS_MDMRS_VAL
- str r4, [r3, #MDMRS_OFFSET]
- ldr r4, [r3, #MDMRS_OFFSET]
-
- /*
- * 11) Enable APD
- */
-
- ldr r4, [r3, #MDREFR_OFFSET]
- and r7, r7, #MDREFR_APD
- orr r4, r4, r7
- str r4, [r3, #MDREFR_OFFSET]
- ldr r4, [r3, #MDREFR_OFFSET]
-.endm
-
-/*
- * This macro tests if the CPU woke up from sleep and eventually resumes
- *
- * Clobbered regs: r4, r5
- */
-.macro pxa_wakeup
- ldr r4, =RCSR
- ldr r5, [r4]
- and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
- str r5, [r4]
- teq r5, #RCSR_SMR
-
- bne pxa_wakeup_exit
-
- ldr r4, =PSSR
- mov r5, #PSSR_PH
- str r5, [r4]
-
- ldr r4, =PSPR
- ldr pc, [r4]
-pxa_wakeup_exit:
-.endm
-
-/*
- * This macro disables all interupts on PXA2xx/PXA3xx CPU
- *
- * Clobbered regs: r4, r5
- */
-.macro pxa_intr_setup
- write32 ICLR, 0
- write32 ICMR, 0
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- write32 ICLR2, 0
- write32 ICMR2, 0
-#endif
-.endm
-
-/*
- * This macro configures clock on PXA2xx/PXA3xx CPU
- *
- * Clobbered regs: r4, r5
- */
-.macro pxa_clock_setup
- /* Disable the peripheral clocks, and set the core clock frequency */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- write32 CKEN, CONFIG_SYS_CKEN
-
- /* Write CCCR */
- write32 CCCR, CONFIG_SYS_CCCR
-
-#ifdef CONFIG_RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
- write32 OSCC, #OSCC_OON
- ldr r4, =OSCC
-
- /* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
-2:
- ldr r5, [r4]
- ands r5, r5, #1
- beq 2b
-#endif
-.endm
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_PXA_MACRO_H__ */
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
new file mode 100644
index 0000000..8c606e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2003
+ * David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c2440.h
+ * Version : 31.3.2003
+ *
+ * Based on S3C2440 User's manual Rev x.x
+ ************************************************/
+
+#ifndef __S3C2440_H__
+#define __S3C2440_H__
+
+#define S3C24X0_UART_CHANNELS 3
+#define S3C24X0_SPI_CHANNELS 2
+
+/* S3C2440 only supports 512 Byte HW ECC */
+#define S3C2440_ECCSIZE 512
+#define S3C2440_ECCBYTES 3
+
+enum s3c24x0_uarts_nr {
+ S3C24X0_UART0,
+ S3C24X0_UART1,
+ S3C24X0_UART2
+};
+
+/* S3C2440 device base addresses */
+#define S3C24X0_MEMCTL_BASE 0x48000000
+#define S3C24X0_USB_HOST_BASE 0x49000000
+#define S3C24X0_INTERRUPT_BASE 0x4A000000
+#define S3C24X0_DMA_BASE 0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
+#define S3C24X0_LCD_BASE 0x4D000000
+#define S3C2440_NAND_BASE 0x4E000000
+#define S3C24X0_UART_BASE 0x50000000
+#define S3C24X0_TIMER_BASE 0x51000000
+#define S3C24X0_USB_DEVICE_BASE 0x52000140
+#define S3C24X0_WATCHDOG_BASE 0x53000000
+#define S3C24X0_I2C_BASE 0x54000000
+#define S3C24X0_I2S_BASE 0x55000000
+#define S3C24X0_GPIO_BASE 0x56000000
+#define S3C24X0_RTC_BASE 0x57000000
+#define S3C2440_ADC_BASE 0x58000000
+#define S3C24X0_SPI_BASE 0x59000000
+#define S3C2440_SDI_BASE 0x5A000000
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+ return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+ return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+ return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+ return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
+{
+ return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+ return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+
+static inline struct s3c2440_nand *s3c2440_get_base_nand(void)
+{
+ return (struct s3c2440_nand *)S3C2440_NAND_BASE;
+}
+
+static inline struct s3c24x0_uart
+ *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+ return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+ return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+ return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+ return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+ return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+ return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+ return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+ return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+
+static inline struct s3c2440_adc *s3c2440_get_base_adc(void)
+{
+ return (struct s3c2440_adc *)S3C2440_ADC_BASE;
+}
+
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+ return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+
+static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void)
+{
+ return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
+}
+
+#endif /*__S3C2440_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index 15f53dd..f634d11 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -33,12 +33,12 @@
/* Memory controller (see manual chapter 5) */
struct s3c24x0_memctl {
- u32 BWSCON;
- u32 BANKCON[8];
- u32 REFRESH;
- u32 BANKSIZE;
- u32 MRSRB6;
- u32 MRSRB7;
+ u32 bwscon;
+ u32 bankcon[8];
+ u32 refresh;
+ u32 banksize;
+ u32 mrsrb6;
+ u32 mrsrb7;
};
@@ -72,40 +72,38 @@ struct s3c24x0_usb_host {
/* INTERRUPT (see manual chapter 14) */
struct s3c24x0_interrupt {
- u32 SRCPND;
- u32 INTMOD;
- u32 INTMSK;
- u32 PRIORITY;
- u32 INTPND;
- u32 INTOFFSET;
-#ifdef CONFIG_S3C2410
- u32 SUBSRCPND;
- u32 INTSUBMSK;
+ u32 srcpnd;
+ u32 intmod;
+ u32 intmsk;
+ u32 priority;
+ u32 intpnd;
+ u32 intoffset;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ u32 subsrcpnd;
+ u32 intsubmsk;
#endif
};
/* DMAS (see manual chapter 8) */
struct s3c24x0_dma {
- u32 DISRC;
-#ifdef CONFIG_S3C2410
- u32 DISRCC;
+ u32 disrc;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ u32 disrcc;
#endif
- u32 DIDST;
-#ifdef CONFIG_S3C2410
- u32 DIDSTC;
+ u32 didst;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ u32 didstc;
#endif
- u32 DCON;
- u32 DSTAT;
- u32 DCSRC;
- u32 DCDST;
- u32 DMASKTRIG;
-#ifdef CONFIG_S3C2400
+ u32 dcon;
+ u32 dstat;
+ u32 dcsrc;
+ u32 dcdst;
+ u32 dmasktrig;
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \
+ || defined(CONFIG_S3C2440)
u32 res[1];
#endif
-#ifdef CONFIG_S3C2410
- u32 res[7];
-#endif
};
struct s3c24x0_dmas {
@@ -116,90 +114,111 @@ struct s3c24x0_dmas {
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/* (see S3C2410 manual chapter 7) */
struct s3c24x0_clock_power {
- u32 LOCKTIME;
- u32 MPLLCON;
- u32 UPLLCON;
- u32 CLKCON;
- u32 CLKSLOW;
- u32 CLKDIVN;
+ u32 locktime;
+ u32 mpllcon;
+ u32 upllcon;
+ u32 clkcon;
+ u32 clkslow;
+ u32 clkdivn;
+#if defined(CONFIG_S3C2440)
+ u32 camdivn;
+#endif
};
/* LCD CONTROLLER (see manual chapter 15) */
struct s3c24x0_lcd {
- u32 LCDCON1;
- u32 LCDCON2;
- u32 LCDCON3;
- u32 LCDCON4;
- u32 LCDCON5;
- u32 LCDSADDR1;
- u32 LCDSADDR2;
- u32 LCDSADDR3;
- u32 REDLUT;
- u32 GREENLUT;
- u32 BLUELUT;
+ u32 lcdcon1;
+ u32 lcdcon2;
+ u32 lcdcon3;
+ u32 lcdcon4;
+ u32 lcdcon5;
+ u32 lcdsaddr1;
+ u32 lcdsaddr2;
+ u32 lcdsaddr3;
+ u32 redlut;
+ u32 greenlut;
+ u32 bluelut;
u32 res[8];
- u32 DITHMODE;
- u32 TPAL;
-#ifdef CONFIG_S3C2410
- u32 LCDINTPND;
- u32 LCDSRCPND;
- u32 LCDINTMSK;
- u32 LPCSEL;
+ u32 dithmode;
+ u32 tpal;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ u32 lcdintpnd;
+ u32 lcdsrcpnd;
+ u32 lcdintmsk;
+ u32 lpcsel;
#endif
};
+#ifdef CONFIG_S3C2410
/* NAND FLASH (see S3C2410 manual chapter 6) */
struct s3c2410_nand {
- u32 NFCONF;
- u32 NFCMD;
- u32 NFADDR;
- u32 NFDATA;
- u32 NFSTAT;
- u32 NFECC;
+ u32 nfconf;
+ u32 nfcmd;
+ u32 nfaddr;
+ u32 nfdata;
+ u32 nfstat;
+ u32 nfecc;
+};
+#endif
+#ifdef CONFIG_S3C2440
+/* NAND FLASH (see S3C2440 manual chapter 6) */
+struct s3c2440_nand {
+ u32 nfconf;
+ u32 nfcont;
+ u32 nfcmd;
+ u32 nfaddr;
+ u32 nfdata;
+ u32 nfeccd0;
+ u32 nfeccd1;
+ u32 nfeccd;
+ u32 nfstat;
+ u32 nfstat0;
+ u32 nfstat1;
};
+#endif
/* UART (see manual chapter 11) */
struct s3c24x0_uart {
- u32 ULCON;
- u32 UCON;
- u32 UFCON;
- u32 UMCON;
- u32 UTRSTAT;
- u32 UERSTAT;
- u32 UFSTAT;
- u32 UMSTAT;
+ u32 ulcon;
+ u32 ucon;
+ u32 ufcon;
+ u32 umcon;
+ u32 utrstat;
+ u32 uerstat;
+ u32 ufstat;
+ u32 umstat;
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 UTXH;
+ u8 utxh;
u8 res2[3];
- u8 URXH;
+ u8 urxh;
#else /* Little Endian */
- u8 UTXH;
+ u8 utxh;
u8 res1[3];
- u8 URXH;
+ u8 urxh;
u8 res2[3];
#endif
- u32 UBRDIV;
+ u32 ubrdiv;
};
/* PWM TIMER (see manual chapter 10) */
struct s3c24x0_timer {
- u32 TCNTB;
- u32 TCMPB;
- u32 TCNTO;
+ u32 tcntb;
+ u32 tcmpb;
+ u32 tcnto;
};
struct s3c24x0_timers {
- u32 TCFG0;
- u32 TCFG1;
- u32 TCON;
+ u32 tcfg0;
+ u32 tcfg1;
+ u32 tcon;
struct s3c24x0_timer ch[4];
- u32 TCNTB4;
- u32 TCNTO4;
+ u32 tcntb4;
+ u32 tcnto4;
};
@@ -207,9 +226,9 @@ struct s3c24x0_timers {
struct s3c24x0_usb_dev_fifos {
#ifdef __BIG_ENDIAN
u8 res[3];
- u8 EP_FIFO_REG;
+ u8 ep_fifo_reg;
#else /* little endian */
- u8 EP_FIFO_REG;
+ u8 ep_fifo_reg;
u8 res[3];
#endif
};
@@ -217,29 +236,29 @@ struct s3c24x0_usb_dev_fifos {
struct s3c24x0_usb_dev_dmas {
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 EP_DMA_CON;
+ u8 ep_dma_con;
u8 res2[3];
- u8 EP_DMA_UNIT;
+ u8 ep_dma_unit;
u8 res3[3];
- u8 EP_DMA_FIFO;
+ u8 ep_dma_fifo;
u8 res4[3];
- u8 EP_DMA_TTC_L;
+ u8 ep_dma_ttc_l;
u8 res5[3];
- u8 EP_DMA_TTC_M;
+ u8 ep_dma_ttc_m;
u8 res6[3];
- u8 EP_DMA_TTC_H;
+ u8 ep_dma_ttc_h;
#else /* little endian */
- u8 EP_DMA_CON;
+ u8 ep_dma_con;
u8 res1[3];
- u8 EP_DMA_UNIT;
+ u8 ep_dma_unit;
u8 res2[3];
- u8 EP_DMA_FIFO;
+ u8 ep_dma_fifo;
u8 res3[3];
- u8 EP_DMA_TTC_L;
+ u8 ep_dma_ttc_l;
u8 res4[3];
- u8 EP_DMA_TTC_M;
+ u8 ep_dma_ttc_m;
u8 res5[3];
- u8 EP_DMA_TTC_H;
+ u8 ep_dma_ttc_h;
u8 res6[3];
#endif
};
@@ -247,69 +266,69 @@ struct s3c24x0_usb_dev_dmas {
struct s3c24x0_usb_device {
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 FUNC_ADDR_REG;
+ u8 func_addr_reg;
u8 res2[3];
- u8 PWR_REG;
+ u8 pwr_reg;
u8 res3[3];
- u8 EP_INT_REG;
+ u8 ep_int_reg;
u8 res4[15];
- u8 USB_INT_REG;
+ u8 usb_int_reg;
u8 res5[3];
- u8 EP_INT_EN_REG;
+ u8 ep_int_en_reg;
u8 res6[15];
- u8 USB_INT_EN_REG;
+ u8 usb_int_en_reg;
u8 res7[3];
- u8 FRAME_NUM1_REG;
+ u8 frame_num1_reg;
u8 res8[3];
- u8 FRAME_NUM2_REG;
+ u8 frame_num2_reg;
u8 res9[3];
- u8 INDEX_REG;
+ u8 index_reg;
u8 res10[7];
- u8 MAXP_REG;
+ u8 maxp_reg;
u8 res11[3];
- u8 EP0_CSR_IN_CSR1_REG;
+ u8 ep0_csr_in_csr1_reg;
u8 res12[3];
- u8 IN_CSR2_REG;
+ u8 in_csr2_reg;
u8 res13[7];
- u8 OUT_CSR1_REG;
+ u8 out_csr1_reg;
u8 res14[3];
- u8 OUT_CSR2_REG;
+ u8 out_csr2_reg;
u8 res15[3];
- u8 OUT_FIFO_CNT1_REG;
+ u8 out_fifo_cnt1_reg;
u8 res16[3];
- u8 OUT_FIFO_CNT2_REG;
+ u8 out_fifo_cnt2_reg;
#else /* little endian */
- u8 FUNC_ADDR_REG;
+ u8 func_addr_reg;
u8 res1[3];
- u8 PWR_REG;
+ u8 pwr_reg;
u8 res2[3];
- u8 EP_INT_REG;
+ u8 ep_int_reg;
u8 res3[15];
- u8 USB_INT_REG;
+ u8 usb_int_reg;
u8 res4[3];
- u8 EP_INT_EN_REG;
+ u8 ep_int_en_reg;
u8 res5[15];
- u8 USB_INT_EN_REG;
+ u8 usb_int_en_reg;
u8 res6[3];
- u8 FRAME_NUM1_REG;
+ u8 frame_num1_reg;
u8 res7[3];
- u8 FRAME_NUM2_REG;
+ u8 frame_num2_reg;
u8 res8[3];
- u8 INDEX_REG;
+ u8 index_reg;
u8 res9[7];
- u8 MAXP_REG;
+ u8 maxp_reg;
u8 res10[7];
- u8 EP0_CSR_IN_CSR1_REG;
+ u8 ep0_csr_in_csr1_reg;
u8 res11[3];
- u8 IN_CSR2_REG;
+ u8 in_csr2_reg;
u8 res12[3];
- u8 OUT_CSR1_REG;
+ u8 out_csr1_reg;
u8 res13[7];
- u8 OUT_CSR2_REG;
+ u8 out_csr2_reg;
u8 res14[3];
- u8 OUT_FIFO_CNT1_REG;
+ u8 out_fifo_cnt1_reg;
u8 res15[3];
- u8 OUT_FIFO_CNT2_REG;
+ u8 out_fifo_cnt2_reg;
u8 res16[3];
#endif /* __BIG_ENDIAN */
struct s3c24x0_usb_dev_fifos fifo[5];
@@ -319,18 +338,18 @@ struct s3c24x0_usb_device {
/* WATCH DOG TIMER (see manual chapter 18) */
struct s3c24x0_watchdog {
- u32 WTCON;
- u32 WTDAT;
- u32 WTCNT;
+ u32 wtcon;
+ u32 wtdat;
+ u32 wtcnt;
};
/* IIC (see manual chapter 20) */
struct s3c24x0_i2c {
- u32 IICCON;
- u32 IICSTAT;
- u32 IICADD;
- u32 IICDS;
+ u32 iiccon;
+ u32 iicstat;
+ u32 iicadd;
+ u32 iicds;
};
@@ -338,25 +357,25 @@ struct s3c24x0_i2c {
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
u16 res1;
- u16 IISCON;
+ u16 iiscon;
u16 res2;
- u16 IISMOD;
+ u16 iismod;
u16 res3;
- u16 IISPSR;
+ u16 iispsr;
u16 res4;
- u16 IISFCON;
+ u16 iisfcon;
u16 res5;
- u16 IISFIFO;
+ u16 iisfifo;
#else /* little endian */
- u16 IISCON;
+ u16 iiscon;
u16 res1;
- u16 IISMOD;
+ u16 iismod;
u16 res2;
- u16 IISPSR;
+ u16 iispsr;
u16 res3;
- u16 IISFCON;
+ u16 iisfcon;
u16 res4;
- u16 IISFIFO;
+ u16 iisfifo;
u16 res5;
#endif
};
@@ -365,87 +384,146 @@ struct s3c24x0_i2s {
/* I/O PORT (see manual chapter 9) */
struct s3c24x0_gpio {
#ifdef CONFIG_S3C2400
- u32 PACON;
- u32 PADAT;
+ u32 pacon;
+ u32 padat;
- u32 PBCON;
- u32 PBDAT;
- u32 PBUP;
+ u32 pbcon;
+ u32 pbdat;
+ u32 pbup;
- u32 PCCON;
- u32 PCDAT;
- u32 PCUP;
+ u32 pccon;
+ u32 pcdat;
+ u32 pcup;
- u32 PDCON;
- u32 PDDAT;
- u32 PDUP;
+ u32 pdcon;
+ u32 pddat;
+ u32 pdup;
- u32 PECON;
- u32 PEDAT;
- u32 PEUP;
+ u32 pecon;
+ u32 pedat;
+ u32 peup;
- u32 PFCON;
- u32 PFDAT;
- u32 PFUP;
+ u32 pfcon;
+ u32 pfdat;
+ u32 pfup;
- u32 PGCON;
- u32 PGDAT;
- u32 PGUP;
+ u32 pgcon;
+ u32 pgdat;
+ u32 pgup;
- u32 OPENCR;
+ u32 opencr;
- u32 MISCCR;
- u32 EXTINT;
+ u32 misccr;
+ u32 extint;
#endif
#ifdef CONFIG_S3C2410
- u32 GPACON;
- u32 GPADAT;
+ u32 gpacon;
+ u32 gpadat;
+ u32 res1[2];
+ u32 gpbcon;
+ u32 gpbdat;
+ u32 gpbup;
+ u32 res2;
+ u32 gpccon;
+ u32 gpcdat;
+ u32 gpcup;
+ u32 res3;
+ u32 gpdcon;
+ u32 gpddat;
+ u32 gpdup;
+ u32 res4;
+ u32 gpecon;
+ u32 gpedat;
+ u32 gpeup;
+ u32 res5;
+ u32 gpfcon;
+ u32 gpfdat;
+ u32 gpfup;
+ u32 res6;
+ u32 gpgcon;
+ u32 gpgdat;
+ u32 gpgup;
+ u32 res7;
+ u32 gphcon;
+ u32 gphdat;
+ u32 gphup;
+ u32 res8;
+
+ u32 misccr;
+ u32 dclkcon;
+ u32 extint0;
+ u32 extint1;
+ u32 extint2;
+ u32 eintflt0;
+ u32 eintflt1;
+ u32 eintflt2;
+ u32 eintflt3;
+ u32 eintmask;
+ u32 eintpend;
+ u32 gstatus0;
+ u32 gstatus1;
+ u32 gstatus2;
+ u32 gstatus3;
+ u32 gstatus4;
+#endif
+#if defined(CONFIG_S3C2440)
+ u32 gpacon;
+ u32 gpadat;
u32 res1[2];
- u32 GPBCON;
- u32 GPBDAT;
- u32 GPBUP;
+ u32 gpbcon;
+ u32 gpbdat;
+ u32 gpbup;
u32 res2;
- u32 GPCCON;
- u32 GPCDAT;
- u32 GPCUP;
+ u32 gpccon;
+ u32 gpcdat;
+ u32 gpcup;
u32 res3;
- u32 GPDCON;
- u32 GPDDAT;
- u32 GPDUP;
+ u32 gpdcon;
+ u32 gpddat;
+ u32 gpdup;
u32 res4;
- u32 GPECON;
- u32 GPEDAT;
- u32 GPEUP;
+ u32 gpecon;
+ u32 gpedat;
+ u32 gpeup;
u32 res5;
- u32 GPFCON;
- u32 GPFDAT;
- u32 GPFUP;
+ u32 gpfcon;
+ u32 gpfdat;
+ u32 gpfup;
u32 res6;
- u32 GPGCON;
- u32 GPGDAT;
- u32 GPGUP;
+ u32 gpgcon;
+ u32 gpgdat;
+ u32 gpgup;
u32 res7;
- u32 GPHCON;
- u32 GPHDAT;
- u32 GPHUP;
+ u32 gphcon;
+ u32 gphdat;
+ u32 gphup;
u32 res8;
- u32 MISCCR;
- u32 DCLKCON;
- u32 EXTINT0;
- u32 EXTINT1;
- u32 EXTINT2;
- u32 EINTFLT0;
- u32 EINTFLT1;
- u32 EINTFLT2;
- u32 EINTFLT3;
- u32 EINTMASK;
- u32 EINTPEND;
- u32 GSTATUS0;
- u32 GSTATUS1;
- u32 GSTATUS2;
- u32 GSTATUS3;
- u32 GSTATUS4;
+ u32 misccr;
+ u32 dclkcon;
+ u32 extint0;
+ u32 extint1;
+ u32 extint2;
+ u32 eintflt0;
+ u32 eintflt1;
+ u32 eintflt2;
+ u32 eintflt3;
+ u32 eintmask;
+ u32 eintpend;
+ u32 gstatus0;
+ u32 gstatus1;
+ u32 gstatus2;
+ u32 gstatus3;
+ u32 gstatus4;
+
+ u32 res9;
+ u32 dsc0;
+ u32 dsc1;
+ u32 mslcon;
+ u32 gpjcon;
+ u32 gpjdat;
+ u32 gpjup;
+ u32 res10;
#endif
};
@@ -454,74 +532,74 @@ struct s3c24x0_gpio {
struct s3c24x0_rtc {
#ifdef __BIG_ENDIAN
u8 res1[67];
- u8 RTCCON;
+ u8 rtccon;
u8 res2[3];
- u8 TICNT;
+ u8 ticnt;
u8 res3[11];
- u8 RTCALM;
+ u8 rtcalm;
u8 res4[3];
- u8 ALMSEC;
+ u8 almsec;
u8 res5[3];
- u8 ALMMIN;
+ u8 almmin;
u8 res6[3];
- u8 ALMHOUR;
+ u8 almhour;
u8 res7[3];
- u8 ALMDATE;
+ u8 almdate;
u8 res8[3];
- u8 ALMMON;
+ u8 almmon;
u8 res9[3];
- u8 ALMYEAR;
+ u8 almyear;
u8 res10[3];
- u8 RTCRST;
+ u8 rtcrst;
u8 res11[3];
- u8 BCDSEC;
+ u8 bcdsec;
u8 res12[3];
- u8 BCDMIN;
+ u8 bcdmin;
u8 res13[3];
- u8 BCDHOUR;
+ u8 bcdhour;
u8 res14[3];
- u8 BCDDATE;
+ u8 bcddate;
u8 res15[3];
- u8 BCDDAY;
+ u8 bcdday;
u8 res16[3];
- u8 BCDMON;
+ u8 bcdmon;
u8 res17[3];
- u8 BCDYEAR;
+ u8 bcdyear;
#else /* little endian */
u8 res0[64];
- u8 RTCCON;
+ u8 rtccon;
u8 res1[3];
- u8 TICNT;
+ u8 ticnt;
u8 res2[11];
- u8 RTCALM;
+ u8 rtcalm;
u8 res3[3];
- u8 ALMSEC;
+ u8 almsec;
u8 res4[3];
- u8 ALMMIN;
+ u8 almmin;
u8 res5[3];
- u8 ALMHOUR;
+ u8 almhour;
u8 res6[3];
- u8 ALMDATE;
+ u8 almdate;
u8 res7[3];
- u8 ALMMON;
+ u8 almmon;
u8 res8[3];
- u8 ALMYEAR;
+ u8 almyear;
u8 res9[3];
- u8 RTCRST;
+ u8 rtcrst;
u8 res10[3];
- u8 BCDSEC;
+ u8 bcdsec;
u8 res11[3];
- u8 BCDMIN;
+ u8 bcdmin;
u8 res12[3];
- u8 BCDHOUR;
+ u8 bcdhour;
u8 res13[3];
- u8 BCDDATE;
+ u8 bcddate;
u8 res14[3];
- u8 BCDDAY;
+ u8 bcdday;
u8 res15[3];
- u8 BCDMON;
+ u8 bcdmon;
u8 res16[3];
- u8 BCDYEAR;
+ u8 bcdyear;
u8 res17[3];
#endif
};
@@ -529,34 +607,34 @@ struct s3c24x0_rtc {
/* ADC (see manual chapter 16) */
struct s3c2400_adc {
- u32 ADCCON;
- u32 ADCDAT;
+ u32 adccon;
+ u32 adcdat;
};
/* ADC (see manual chapter 16) */
struct s3c2410_adc {
- u32 ADCCON;
- u32 ADCTSC;
- u32 ADCDLY;
- u32 ADCDAT0;
- u32 ADCDAT1;
+ u32 adccon;
+ u32 adctsc;
+ u32 adcdly;
+ u32 adcdat0;
+ u32 adcdat1;
};
/* SPI (see manual chapter 22) */
struct s3c24x0_spi_channel {
- u8 SPCON;
+ u8 spcon;
u8 res1[3];
- u8 SPSTA;
+ u8 spsta;
u8 res2[3];
- u8 SPPIN;
+ u8 sppin;
u8 res3[3];
- u8 SPPRE;
+ u8 sppre;
u8 res4[3];
- u8 SPTDAT;
+ u8 sptdat;
u8 res5[3];
- u8 SPRDAT;
+ u8 sprdat;
u8 res6[3];
u8 res7[16];
};
@@ -570,53 +648,53 @@ struct s3c24x0_spi {
struct s3c2400_mmc {
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 MMCON;
+ u8 mmcon;
u8 res2[3];
- u8 MMCRR;
+ u8 mmcrr;
u8 res3[3];
- u8 MMFCON;
+ u8 mmfcon;
u8 res4[3];
- u8 MMSTA;
+ u8 mmsta;
u16 res5;
- u16 MMFSTA;
+ u16 mmfsta;
u8 res6[3];
- u8 MMPRE;
+ u8 mmpre;
u16 res7;
- u16 MMLEN;
+ u16 mmlen;
u8 res8[3];
- u8 MMCR7;
- u32 MMRSP[4];
+ u8 mmcr7;
+ u32 mmrsp[4];
u8 res9[3];
- u8 MMCMD0;
- u32 MMCMD1;
+ u8 mmcmd0;
+ u32 mmcmd1;
u16 res10;
- u16 MMCR16;
+ u16 mmcr16;
u8 res11[3];
- u8 MMDAT;
+ u8 mmdat;
#else
- u8 MMCON;
+ u8 mmcon;
u8 res1[3];
- u8 MMCRR;
+ u8 mmcrr;
u8 res2[3];
- u8 MMFCON;
+ u8 mmfcon;
u8 res3[3];
- u8 MMSTA;
+ u8 mmsta;
u8 res4[3];
- u16 MMFSTA;
+ u16 mmfsta;
u16 res5;
- u8 MMPRE;
+ u8 mmpre;
u8 res6[3];
- u16 MMLEN;
+ u16 mmlen;
u16 res7;
- u8 MMCR7;
+ u8 mmcr7;
u8 res8[3];
- u32 MMRSP[4];
- u8 MMCMD0;
+ u32 mmrsp[4];
+ u8 mmcmd0;
u8 res9[3];
- u32 MMCMD1;
- u16 MMCR16;
+ u32 mmcmd1;
+ u16 mmcr16;
u16 res10;
- u8 MMDAT;
+ u8 mmdat;
u8 res11[3];
#endif
};
@@ -624,29 +702,29 @@ struct s3c2400_mmc {
/* SD INTERFACE (see S3C2410 manual chapter 19) */
struct s3c2410_sdi {
- u32 SDICON;
- u32 SDIPRE;
- u32 SDICARG;
- u32 SDICCON;
- u32 SDICSTA;
- u32 SDIRSP0;
- u32 SDIRSP1;
- u32 SDIRSP2;
- u32 SDIRSP3;
- u32 SDIDTIMER;
- u32 SDIBSIZE;
- u32 SDIDCON;
- u32 SDIDCNT;
- u32 SDIDSTA;
- u32 SDIFSTA;
+ u32 sdicon;
+ u32 sdipre;
+ u32 sdicarg;
+ u32 sdiccon;
+ u32 sdicsta;
+ u32 sdirsp0;
+ u32 sdirsp1;
+ u32 sdirsp2;
+ u32 sdirsp3;
+ u32 sdidtimer;
+ u32 sdibsize;
+ u32 sdidcon;
+ u32 sdidcnt;
+ u32 sdidsta;
+ u32 sdifsta;
#ifdef __BIG_ENDIAN
u8 res[3];
- u8 SDIDAT;
+ u8 sdidat;
#else
- u8 SDIDAT;
+ u8 sdidat;
u8 res[3];
#endif
- u32 SDIIMSK;
+ u32 sdiimsk;
};
#endif /*__S3C24X0_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
index c37d4a1..54184c4 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
@@ -22,6 +22,8 @@
#include <asm/arch/s3c2400.h>
#elif defined CONFIG_S3C2410
#include <asm/arch/s3c2410.h>
+#elif defined CONFIG_S3C2440
+ #include <asm/arch/s3c2440.h>
#else
#error Please define the s3c24x0 cpu type
#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index 68c59d1..48de64d 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -65,7 +65,7 @@ struct mmc_host {
unsigned int clock; /* Current clock (MHz) */
};
-int s5p_mmc_init(int dev_index);
+int s5p_mmc_init(int dev_index, int bus_width);
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/uart.h b/arch/arm/include/asm/arch-s5pc1xx/uart.h
index 2d7ad7e..f6eeab4 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/uart.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/uart.h
@@ -24,6 +24,12 @@
#define __ASM_ARCH_UART_H_
#ifndef __ASSEMBLY__
+/* baudrate rest value */
+union br_rest {
+ unsigned short slot; /* udivslot */
+ unsigned char value; /* ufracval */
+};
+
struct s5p_uart {
unsigned int ulcon;
unsigned int ucon;
@@ -38,10 +44,12 @@ struct s5p_uart {
unsigned char urxh;
unsigned char res2[3];
unsigned int ubrdiv;
- unsigned short udivslot;
- unsigned char res3[2];
- unsigned char res4[0x3d0];
+ union br_rest rest;
+ unsigned char res3[0x3d0];
};
+
+static int use_divslot = 1;
+
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 4124f0a..c60dba2 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -21,9 +21,6 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-/* Relocation to SDRAM works on all ARM boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 5438ebc..ada3fbb 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -61,7 +61,6 @@ typedef struct global_data {
unsigned long tbu;
unsigned long long timer_reset_value;
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */
unsigned long mon_len; /* monitor len */
@@ -71,7 +70,6 @@ typedef struct global_data {
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
unsigned long tlb_addr;
#endif
-#endif
void **jt; /* jump table */
char env_buf[32]; /* buffer for getenv() before reloc. */
} gd_t;
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index 4ac4f61..33973a3 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -34,16 +34,12 @@ extern ulong _bss_start_ofs; /* BSS start relative to _start */
extern ulong _bss_end_ofs; /* BSS end relative to _start */
extern ulong IRQ_STACK_START; /* top of IRQ stack */
extern ulong FIQ_STACK_START; /* top of FIQ stack */
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-extern ulong _armboot_start_ofs; /* code start */
-#else
extern ulong _TEXT_BASE; /* code start */
extern ulong _datarel_start_ofs;
extern ulong _datarelrolocal_start_ofs;
extern ulong _datarellocal_start_ofs;
extern ulong _datarelro_start_ofs;
extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */
-#endif
/* cpu/.../cpu.c */
int cpu_init(void);
@@ -56,9 +52,7 @@ int arch_misc_init(void);
/* board/.../... */
int board_init(void);
int dram_init (void);
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
void dram_init_banksize (void);
-#endif
void setup_serial_tag (struct tag **params);
void setup_revision_tag (struct tag **params);
generated by cgit v1.1 at 2024-11-08 08:04:42 +0000