diff options
Diffstat (limited to 'arch/arm/include')
24 files changed, 754 insertions, 142 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index 98fc2b5..2f4a3d1 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -137,14 +137,62 @@ struct pad_signals { int mcasp0_fsr; int mcasp0_axr1; int mcasp0_ahclkx; - int xdma_event_intr0; - int xdma_event_intr1; + int cam0_hd; + int cam0_vd; + int cam0_field; + int cam0_wen; + int cam0_pclk; + int cam0_data8; + int cam0_data9; + int cam1_data9; + int cam1_data8; + int cam1_hd; + int cam1_vd; + int cam1_pclk; + int cam1_field; + int cam1_wen; + int cam1_data0; + int cam1_data1; + int cam1_data2; + int cam1_data3; + int cam1_data4; + int cam1_data5; + int cam1_data6; + int cam1_data7; + int cam0_data0; + int cam0_data1; + int cam0_data2; + int cam0_data3; + int cam0_data4; + int cam0_data5; + int cam0_data6; + int cam0_data7; + int uart3_rxd; + int uart3_txd; + int uart3_ctsn; + int uart3_rtsn; + int gpio5_8; + int gpio5_9; + int gpio5_10; + int gpio5_11; + int gpio5_12; + int gpio5_13; + int spi4_sclk; + int spi4_d0; + int spi4_d1; + int spi4_cs0; + int spi2_sclk; + int spi2_d0; + int spi2_d1; + int spi2_cs0; + int xdma_evt_intr0; + int xdma_evt_intr1; + int clkreq; int nresetin_out; - int porz; - int nnmi; - int osc0_in; - int osc0_out; int rsvd1; + int nnmi; + int rsvd2; + int rsvd3; int tms; int tdi; int tdo; @@ -154,34 +202,11 @@ struct pad_signals { int emu1; int osc1_in; int osc1_out; - int pmic_power_en; int rtc_porz; - int rsvd2; - int ext_wakeup; - int enz_kaldo_1p8v; - int usb0_dm; - int usb0_dp; - int usb0_ce; - int usb0_id; - int usb0_vbus; + int ext_wakeup0; + int pmic_power_en0; int usb0_drvvbus; - int usb1_dm; - int usb1_dp; - int usb1_ce; - int usb1_id; - int usb1_vbus; int usb1_drvvbus; - int ddr_resetn; - int ddr_csn0; - int ddr_cke; - int ddr_ck; - int ddr_nck; - int ddr_casn; - int ddr_rasn; - int ddr_wen; - int ddr_ba0; - int ddr_ba1; - int ddr_ba2; }; #endif /* _MUX_AM43XX_H_ */ diff --git a/arch/arm/include/asm/arch-arm720t/hardware.h b/arch/arm/include/asm/arch-arm720t/hardware.h deleted file mode 100644 index 8ca42d9..0000000 --- a/arch/arm/include/asm/arch-arm720t/hardware.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __ARM7_HW_H -#define __ARM7_HW_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune <curt@cucy.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) -/* include IntegratorCP/CM720T specific hardware file if there was one */ -#else -#error No hardware file defined for this configuration -#endif - -#endif /* __ARM7_HW_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index b140c1f..ca8d38c 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -8,6 +8,14 @@ #define _ASM_ARMV8_FSL_LSCH3_CONFIG_ #include <fsl_ddrc_version.h> + +#define CONFIG_SYS_PAGE_SIZE 0x10000 + +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#endif + #define CONFIG_MP #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ /* Link Definitions */ @@ -23,6 +31,7 @@ #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) @@ -30,6 +39,20 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) +#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) + +/* SP (Cortex-A5) related */ +#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) +#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ + (CONFIG_SYS_FSL_SP_ADDR + 0x0008) +#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ + (CONFIG_SYS_FSL_SP_ADDR + 0x1000) + #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL @@ -88,22 +111,57 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 - +#define CONFIG_SYS_FSL_ESDHC_LE /* IFC */ #define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* PCIe */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) +#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL + +/* Cache Coherent Interconnect */ +#define CCI_MN_BASE 0x04000000 +#define CCI_MN_RNF_NODEID_LIST 0x180 +#define CCI_MN_DVM_DOMAIN_CTL 0x200 +#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 + +/* Device Configuration */ +#define DCFG_BASE 0x01e00000 +#define DCFG_PORSR1 0x000 +#define DCFG_PORSR1_RCW_SRC 0xff800000 +#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 + +#define DCFG_DCSR_BASE 0X700100000ULL +#define DCFG_DCSR_PORCR1 0x000 + +/* Supplemental Configuration */ +#define SCFG_BASE 0x01fc0000 +#define SCFG_USB3PRM1CR 0x000 #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SRDS_2 #else #error SoC not defined #endif #ifdef CONFIG_LS2085A #define CONFIG_SYS_FSL_ERRATUM_A008336 +#define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 +#define CONFIG_SYS_FSL_ERRATUM_A008585 +#define CONFIG_SYS_FSL_ERRATUM_A008751 #endif #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h new file mode 100644 index 0000000..2810f3f --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h @@ -0,0 +1,67 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SERDES_H +#define __FSL_SERDES_H + +#include <config.h> + +#define SRDS_MAX_LANES 8 + +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + XAUI1, + XAUI2, + XFI1, + XFI2, + XFI3, + XFI4, + XFI5, + XFI6, + XFI7, + XFI8, + SGMII1, + SGMII2, + SGMII3, + SGMII4, + SGMII5, + SGMII6, + SGMII7, + SGMII8, + SGMII9, + SGMII10, + SGMII11, + SGMII12, + SGMII13, + SGMII14, + SGMII15, + SGMII16, + QSGMII_A, /* A indicates MACs 1-4 */ + QSGMII_B, /* B indicates MACs 5-8 */ + QSGMII_C, /* C indicates MACs 9-12 */ + QSGMII_D, /* D indicates MACs 12-16 */ + SERDES_PRCTL_COUNT +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, +}; + +int is_serdes_configured(enum srds_prtcl device); +void fsl_serdes_init(void); + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); +int is_serdes_prtcl_valid(int serdes, u32 prtcl); + +#endif /* __FSL_SERDES_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h index dd11ef7..d6bee60 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -47,6 +47,30 @@ struct ccsr_gur { u32 devdisr5; /* Device disable control 5 */ u32 devdisr6; /* Device disable control 6 */ u32 devdisr7; /* Device disable control 7 */ +#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 +#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 +#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 +#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 +#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 +#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 +#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 +#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 +#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 +#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 +#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 +#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 +#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 u8 res_08c[0x90-0x8c]; u32 coredisru; /* uppper portion for support of 64 cores */ u32 coredisrl; /* lower portion for support of 64 cores */ @@ -63,6 +87,11 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 + u8 res_180[0x200-0x180]; u32 scratchrw[32]; /* Scratch Read/Write */ u8 res_280[0x300-0x280]; diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h new file mode 100644 index 0000000..16b723d --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h @@ -0,0 +1,8 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void fsl_lsch3_early_init_f(void); + diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 6561ce6..4dc528b 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -119,10 +119,6 @@ #define DCU_LAYER_MAX_NUM 16 -#define QE_MURAM_SIZE 0x6000UL -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 - #define CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_LS102XA diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 3a64afc..a8122c1 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -17,6 +17,9 @@ #define SOC_VER_LS1021 0x11 #define SOC_VER_LS1022 0x12 +#define SOC_MAJOR_VER_1_0 0x1 +#define SOC_MAJOR_VER_2_0 0x2 + #define CCSR_BRR_OFFSET 0xe4 #define CCSR_SCRATCHRW1_OFFSET 0x200 diff --git a/arch/arm/include/asm/arch-stm32f4/fmc.h b/arch/arm/include/asm/arch-stm32f4/fmc.h new file mode 100644 index 0000000..4ab3031 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/fmc.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2013 + * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, <rev13@wp.pl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MACH_FMC_H_ +#define _MACH_FMC_H_ + +struct stm32_fmc_regs { + u32 sdcr1; /* Control register 1 */ + u32 sdcr2; /* Control register 2 */ + u32 sdtr1; /* Timing register 1 */ + u32 sdtr2; /* Timing register 2 */ + u32 sdcmr; /* Mode register */ + u32 sdrtr; /* Refresh timing register */ + u32 sdsr; /* Status register */ +}; + +/* + * FMC registers base + */ +#define STM32_SDRAM_FMC_BASE 0xA0000140 +#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE) + +/* Control register SDCR */ +#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ +#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ +#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ +#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ +#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ +#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ +#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ +#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ +#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ + +/* Timings register SDTR */ +#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ +#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ +#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ +#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ +#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ +#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ +#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ + + +#define FMC_SDCMR_NRFS_SHIFT 5 + +#define FMC_SDCMR_MODE_NORMAL 0 +#define FMC_SDCMR_MODE_START_CLOCK 1 +#define FMC_SDCMR_MODE_PRECHARGE 2 +#define FMC_SDCMR_MODE_AUTOREFRESH 3 +#define FMC_SDCMR_MODE_WRITE_MODE 4 +#define FMC_SDCMR_MODE_SELFREFRESH 5 +#define FMC_SDCMR_MODE_POWERDOWN 6 + +#define FMC_SDCMR_BANK_1 (1 << 4) +#define FMC_SDCMR_BANK_2 (1 << 3) + +#define FMC_SDCMR_MODE_REGISTER_SHIFT 9 + +#define FMC_SDSR_BUSY (1 << 5) + +#define FMC_BUSY_WAIT() do { \ + __asm__ __volatile__ ("dsb" : : : "memory"); \ + while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \ + ; \ + } while (0) + + +#endif /* _MACH_FMC_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h new file mode 100644 index 0000000..7cd866e --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/gpio.h @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2011 + * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, <rev13@wp.pl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STM32_GPIO_H_ +#define _STM32_GPIO_H_ + +enum stm32_gpio_port { + STM32_GPIO_PORT_A = 0, + STM32_GPIO_PORT_B, + STM32_GPIO_PORT_C, + STM32_GPIO_PORT_D, + STM32_GPIO_PORT_E, + STM32_GPIO_PORT_F, + STM32_GPIO_PORT_G, + STM32_GPIO_PORT_H, + STM32_GPIO_PORT_I +}; + +enum stm32_gpio_pin { + STM32_GPIO_PIN_0 = 0, + STM32_GPIO_PIN_1, + STM32_GPIO_PIN_2, + STM32_GPIO_PIN_3, + STM32_GPIO_PIN_4, + STM32_GPIO_PIN_5, + STM32_GPIO_PIN_6, + STM32_GPIO_PIN_7, + STM32_GPIO_PIN_8, + STM32_GPIO_PIN_9, + STM32_GPIO_PIN_10, + STM32_GPIO_PIN_11, + STM32_GPIO_PIN_12, + STM32_GPIO_PIN_13, + STM32_GPIO_PIN_14, + STM32_GPIO_PIN_15 +}; + +enum stm32_gpio_mode { + STM32_GPIO_MODE_IN = 0, + STM32_GPIO_MODE_OUT, + STM32_GPIO_MODE_AF, + STM32_GPIO_MODE_AN +}; + +enum stm32_gpio_otype { + STM32_GPIO_OTYPE_PP = 0, + STM32_GPIO_OTYPE_OD +}; + +enum stm32_gpio_speed { + STM32_GPIO_SPEED_2M = 0, + STM32_GPIO_SPEED_25M, + STM32_GPIO_SPEED_50M, + STM32_GPIO_SPEED_100M +}; + +enum stm32_gpio_pupd { + STM32_GPIO_PUPD_NO = 0, + STM32_GPIO_PUPD_UP, + STM32_GPIO_PUPD_DOWN +}; + +enum stm32_gpio_af { + STM32_GPIO_AF0 = 0, + STM32_GPIO_AF1, + STM32_GPIO_AF2, + STM32_GPIO_AF3, + STM32_GPIO_AF4, + STM32_GPIO_AF5, + STM32_GPIO_AF6, + STM32_GPIO_AF7, + STM32_GPIO_AF8, + STM32_GPIO_AF9, + STM32_GPIO_AF10, + STM32_GPIO_AF11, + STM32_GPIO_AF12, + STM32_GPIO_AF13, + STM32_GPIO_AF14, + STM32_GPIO_AF15 +}; + +struct stm32_gpio_dsc { + enum stm32_gpio_port port; + enum stm32_gpio_pin pin; +}; + +struct stm32_gpio_ctl { + enum stm32_gpio_mode mode; + enum stm32_gpio_otype otype; + enum stm32_gpio_speed speed; + enum stm32_gpio_pupd pupd; + enum stm32_gpio_af af; +}; + +static inline unsigned stm32_gpio_to_port(unsigned gpio) +{ + return gpio / 16; +} + +static inline unsigned stm32_gpio_to_pin(unsigned gpio) +{ + return gpio % 16; +} + +int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc, + const struct stm32_gpio_ctl *gpio_ctl); +int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state); + +#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h new file mode 100644 index 0000000..a9f88db --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2011 + * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, <rev13@wp.pl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MACH_STM32_H_ +#define _MACH_STM32_H_ + +/* + * Peripheral memory map + */ +#define STM32_PERIPH_BASE 0x40000000 +#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) +#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) +#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) +#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000) + +#define STM32_BUS_MASK 0xFFFF0000 + +/* + * Register maps + */ +struct stm32_rcc_regs { + u32 cr; /* RCC clock control */ + u32 pllcfgr; /* RCC PLL configuration */ + u32 cfgr; /* RCC clock configuration */ + u32 cir; /* RCC clock interrupt */ + u32 ahb1rstr; /* RCC AHB1 peripheral reset */ + u32 ahb2rstr; /* RCC AHB2 peripheral reset */ + u32 ahb3rstr; /* RCC AHB3 peripheral reset */ + u32 rsv0; + u32 apb1rstr; /* RCC APB1 peripheral reset */ + u32 apb2rstr; /* RCC APB2 peripheral reset */ + u32 rsv1[2]; + u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ + u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ + u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ + u32 rsv2; + u32 apb1enr; /* RCC APB1 peripheral clock enable */ + u32 apb2enr; /* RCC APB2 peripheral clock enable */ + u32 rsv3[2]; + u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ + u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ + u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ + u32 rsv4; + u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ + u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ + u32 rsv5[2]; + u32 bdcr; /* RCC Backup domain control */ + u32 csr; /* RCC clock control & status */ + u32 rsv6[2]; + u32 sscgr; /* RCC spread spectrum clock generation */ + u32 plli2scfgr; /* RCC PLLI2S configuration */ + u32 pllsaicfgr; + u32 dckcfgr; +}; + +struct stm32_pwr_regs { + u32 cr; + u32 csr; +}; + +struct stm32_flash_regs { + u32 acr; + u32 key; + u32 optkeyr; + u32 sr; + u32 cr; + u32 optcr; + u32 optcr1; +}; + +/* + * Registers access macros + */ +#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800) +#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) + +#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000) +#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE) + +#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0x3C00) +#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE) + +#define STM32_FLASH_SR_BSY (1 << 16) + +#define STM32_FLASH_CR_PG (1 << 0) +#define STM32_FLASH_CR_SER (1 << 1) +#define STM32_FLASH_CR_STRT (1 << 16) +#define STM32_FLASH_CR_LOCK (1 << 31) +#define STM32_FLASH_CR_SNB_OFFSET 3 + +enum clock { + CLOCK_CORE, + CLOCK_AHB, + CLOCK_APB1, + CLOCK_APB2 +}; + +int configure_clocks(void); +unsigned long clock_get(enum clock clck); + +#endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/hardware.h b/arch/arm/include/asm/arch-tegra114/hardware.h deleted file mode 100644 index c21fbb6..0000000 --- a/arch/arm/include/asm/arch-tegra114/hardware.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA114_HARDWARE_H_ -#define _TEGRA114_HARDWARE_H_ - -/* include tegra specific hardware definitions */ - -#endif /* _TEGRA114_HARDWARE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/hardware.h b/arch/arm/include/asm/arch-tegra124/hardware.h deleted file mode 100644 index 114fce8..0000000 --- a/arch/arm/include/asm/arch-tegra124/hardware.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_HARDWARE_H_ -#define _TEGRA124_HARDWARE_H_ - -/* - * Include Tegra-specific hardware definitions - * Nothing needed currently for Tegra124 - */ - -#endif /* _TEGRA124_HARDWARE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/hardware.h b/arch/arm/include/asm/arch-tegra20/hardware.h deleted file mode 100644 index a295894..0000000 --- a/arch/arm/include/asm/arch-tegra20/hardware.h +++ /dev/null @@ -1,13 +0,0 @@ -/* -* (C) Copyright 2010-2011 -* NVIDIA Corporation <www.nvidia.com> -* - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef __TEGRA2_HW_H -#define __TEGRA2_HW_H - -/* include tegra specific hardware definitions */ - -#endif /* __TEGRA2_HW_H */ diff --git a/arch/arm/include/asm/arch-tegra30/hardware.h b/arch/arm/include/asm/arch-tegra30/hardware.h deleted file mode 100644 index b1a5aa9..0000000 --- a/arch/arm/include/asm/arch-tegra30/hardware.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA30_HARDWARE_H_ -#define _TEGRA30_HARDWARE_H_ - -/* include tegra specific hardware definitions */ - -#endif /* _TEGRA30-HARDWARE_H_ */ diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 724682c..bc6db2a 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -189,6 +189,7 @@ struct anadig_reg { #define CCM_REG_CTRL_MASK 0xffffffff #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) #define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8) @@ -199,6 +200,7 @@ struct anadig_reg { #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 +#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4) #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) @@ -206,14 +208,23 @@ struct anadig_reg { #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) +#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8) #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) #define CCM_CCGR10_NFC_CTRL_MASK 0x3 +#define ANADIG_PLL7_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL7_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) #define ANADIG_PLL5_CTRL_BYPASS (1 << 16) #define ANADIG_PLL5_CTRL_ENABLE (1 << 13) #define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL5_CTRL_DIV_SELECT 1 +#define ANADIG_PLL3_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL3_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL2_CTRL_DIV_SELECT 1 diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h new file mode 100644 index 0000000..6730cde --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015 + * Toradex, Inc. + * + * Authors: Stefan Agner + * Sanchayan Maity + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_VF610_DDRMC_H +#define __ASM_ARCH_VF610_DDRMC_H + +struct ddrmc_lvl_info { + u16 wrlvl_reg_en; + u16 wrlvl_dl_0; + u16 wrlvl_dl_1; + u16 rdlvl_gt_reg_en; + u16 rdlvl_gt_dl_0; + u16 rdlvl_gt_dl_1; + u16 rdlvl_reg_en; + u16 rdlvl_dl_0; + u16 rdlvl_dl_1; +}; + +struct ddr3_jedec_timings { + u8 tinit; + u32 trst_pwron; + u32 cke_inactive; + u8 wrlat; + u8 caslat_lin; + u8 trc; + u8 trrd; + u8 tccd; + u8 tfaw; + u8 trp; + u8 twtr; + u8 tras_min; + u8 tmrd; + u8 trtp; + u32 tras_max; + u8 tmod; + u8 tckesr; + u8 tcke; + u8 trcd_int; + u8 tdal; + u16 tdll; + u8 trp_ab; + u16 tref; + u8 trfc; + u8 tpdex; + u8 txpdll; + u8 txsnr; + u16 txsr; + u8 cksrx; + u8 cksre; + u16 zqcl; + u16 zqinit; + u8 zqcs; + u8 ref_per_zq; + u8 aprebit; + u8 wlmrd; + u8 wldqsen; +}; + +void ddrmc_setup_iomux(void); +void ddrmc_phy_init(void); +void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, + struct ddrmc_lvl_info *lvl, + int col_diff, int row_diff); + +#endif diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 6b10bdf..a7d765a 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -52,6 +52,7 @@ #define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) #define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) #define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000) +#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000) #define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) #define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) #define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) @@ -65,7 +66,9 @@ #define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) #define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) #define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) -#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) +#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800) +#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00) +#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) #define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) #define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) #define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) @@ -84,6 +87,7 @@ #define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000) #define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) +#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000) #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) #define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) #define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000) @@ -196,8 +200,8 @@ #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) #define DDRMC_CR97_WRLVL_EN (1 << 24) -#define DDRMC_CR98_WRLVL_DL_0 (0) -#define DDRMC_CR99_WRLVL_DL_1 (0) +#define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff) +#define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff) #define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) #define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) @@ -263,6 +267,14 @@ #define SRC_SRSR_WDOG_M4 (0x1 << 4) #define SRC_SRSR_WDOG_A5 (0x1 << 3) #define SRC_SRSR_POR_RST (0x1 << 0) +#define SRC_SBMR2_BMOD_MASK (0x3 << 24) +#define SRC_SBMR2_BMOD_SHIFT 24 +#define SRC_SBMR2_BMOD_FUSES 0x0 +#define SRC_SBMR2_BMOD_SERIAL 0x1 +#define SRC_SBMR2_BMOD_RCON 0x2 + +/* Slow Clock Source Controller Module (SCSC) */ +#define SCSC_SOSC_CTR_SOSC_EN 0x1 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> @@ -448,6 +460,24 @@ struct mscm_ir { u16 rsvd3[848]; }; +/* SCSC */ +struct scsc_reg { + u32 sirc_ctr; + u32 sosc_ctr; +}; + +/* MSCM */ +struct mscm { + u32 cpxtype; + u32 cpxnum; + u32 cpxmaster; + u32 cpxcount; + u32 cpxcfg0; + u32 cpxcfg1; + u32 cpxcfg2; + u32 cpxcfg3; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h new file mode 100644 index 0000000..d2aa1c4 --- /dev/null +++ b/arch/arm/include/asm/armv7m.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2010,2011 + * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, <rev13@wp.pl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARMV7M_H +#define ARMV7M_H + +#if defined(__ASSEMBLY__) +.syntax unified +.thumb +#endif + +#define V7M_SCB_BASE 0xE000ED00 +#define V7M_MPU_BASE 0xE000ED90 + +#define V7M_SCB_VTOR 0x08 + +#if !defined(__ASSEMBLY__) +struct v7m_scb { + uint32_t cpuid; /* CPUID Base Register */ + uint32_t icsr; /* Interrupt Control and State Register */ + uint32_t vtor; /* Vector Table Offset Register */ + uint32_t aircr; /* App Interrupt and Reset Control Register */ +}; +#define V7M_SCB ((struct v7m_scb *)V7M_SCB_BASE) + +#define V7M_AIRCR_VECTKEY 0x5fa +#define V7M_AIRCR_VECTKEY_SHIFT 16 +#define V7M_AIRCR_ENDIAN (1 << 15) +#define V7M_AIRCR_PRIGROUP_SHIFT 8 +#define V7M_AIRCR_PRIGROUP_MSK (0x7 << V7M_AIRCR_PRIGROUP_SHIFT) +#define V7M_AIRCR_SYSRESET (1 << 2) + +#define V7M_ICSR_VECTACT_MSK 0xFF + +struct v7m_mpu { + uint32_t type; /* Type Register */ + uint32_t ctrl; /* Control Register */ + uint32_t rnr; /* Region Number Register */ + uint32_t rbar; /* Region Base Address Register */ + uint32_t rasr; /* Region Attribute and Size Register */ +}; +#define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE) + +#define V7M_MPU_CTRL_ENABLE (1 << 0) +#define V7M_MPU_CTRL_HFNMIENA (1 << 1) + +#define V7M_MPU_RASR_EN (1 << 0) +#define V7M_MPU_RASR_SIZE_BITS 1 +#define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS) +#define V7M_MPU_RASR_AP_RW_RW (3 << 24) + +#endif /* !defined(__ASSEMBLY__) */ +#endif /* ARMV7M_H */ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h new file mode 100644 index 0000000..f097c81 --- /dev/null +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -0,0 +1,25 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SECURE_BOOT_H +#define __FSL_SECURE_BOOT_H + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_FIT_SIGNATURE + +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xcfffffff;" \ + "setenv initrd_high 0xcfffffff;" \ + "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" + +/* The address needs to be modified according to NOR memory map */ +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000 + +#include <config_fsl_secboot.h> +#endif +#endif + +#endif diff --git a/arch/arm/include/asm/imx-common/regs-usbphy.h b/arch/arm/include/asm/imx-common/regs-usbphy.h new file mode 100644 index 0000000..220e45f --- /dev/null +++ b/arch/arm/include/asm/imx-common/regs-usbphy.h @@ -0,0 +1,26 @@ +/* + * Freescale USB PHY Register Definitions + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __REGS_USBPHY_H__ +#define __REGS_USBPHY_H__ + +#define USBPHY_CTRL 0x00000030 +#define USBPHY_CTRL_SET 0x00000034 +#define USBPHY_CTRL_CLR 0x00000038 +#define USBPHY_CTRL_TOG 0x0000003C +#define USBPHY_PWD 0x00000000 +#define USBPHY_TX 0x00000010 +#define USBPHY_RX 0x00000020 +#define USBPHY_DEBUG 0x00000050 + +#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) +#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) +#define USBPHY_CTRL_OTG_ID (1 << 27) +#define USBPHY_CTRL_CLKGATE (1 << 30) +#define USBPHY_CTRL_SFTRST (1 << 31) + +#endif /* __REGS_USBPHY_H__ */ diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index c424a22..5afe791 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1108,6 +1108,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_KZM9G 4140 #define MACH_TYPE_COLIBRI_T30 4493 #define MACH_TYPE_APALIS_T30 4513 +#define MACH_TYPE_OMAPL138_LCDK 2495 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index c8c3e71..b0296fb 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -362,6 +362,10 @@ struct omap_sys_ctrl_regs { u32 control_core_control_io1; u32 control_core_control_io2; u32 control_id_code; + u32 control_std_fuse_die_id_0; + u32 control_std_fuse_die_id_1; + u32 control_std_fuse_die_id_2; + u32 control_std_fuse_die_id_3; u32 control_std_fuse_opp_bgap; u32 control_ldosram_iva_voltage_ctrl; u32 control_ldosram_mpu_voltage_ctrl; @@ -578,6 +582,7 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); void usb_fake_mac_from_die_id(u32 *id); +void usb_set_serial_num_from_die_id(u32 *id); void omap_smc1(u32 service, u32 val); diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h deleted file mode 100644 index fb08578..0000000 --- a/arch/arm/include/asm/pcie_layerscape.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PCIE_LAYERSCAPE_H_ -#define __PCIE_LAYERSCAPE_H_ - -void pci_init_board(void); -void ft_pcie_setup(void *blob, bd_t *bd); - -#endif |