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-rw-r--r--arch/arm/include/asm/arch-sunxi/clock.h29
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun4i.h256
-rw-r--r--arch/arm/include/asm/arch-sunxi/sys_proto.h16
-rw-r--r--arch/arm/include/asm/arch-sunxi/timer.h88
4 files changed, 389 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
new file mode 100644
index 0000000..5669f39
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_H
+#define _SUNXI_CLOCK_H
+
+#include <linux/types.h>
+
+#define CLK_GATE_OPEN 0x1
+#define CLK_GATE_CLOSE 0x0
+
+/* clock control module regs definition */
+#include <asm/arch/clock_sun4i.h>
+
+#ifndef __ASSEMBLY__
+int clock_init(void);
+int clock_twi_onoff(int port, int state);
+void clock_set_pll1(unsigned int hz);
+unsigned int clock_get_pll6(void);
+void clock_init_safe(void);
+void clock_init_uart(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
new file mode 100644
index 0000000..928f3f2
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -0,0 +1,256 @@
+/*
+ * sun4i, sun5i and sun7i clock register definitions
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN4I_H
+#define _SUNXI_CLOCK_SUN4I_H
+
+struct sunxi_ccm_reg {
+ u32 pll1_cfg; /* 0x00 pll1 control */
+ u32 pll1_tun; /* 0x04 pll1 tuning */
+ u32 pll2_cfg; /* 0x08 pll2 control */
+ u32 pll2_tun; /* 0x0c pll2 tuning */
+ u32 pll3_cfg; /* 0x10 pll3 control */
+ u8 res0[0x4];
+ u32 pll4_cfg; /* 0x18 pll4 control */
+ u8 res1[0x4];
+ u32 pll5_cfg; /* 0x20 pll5 control */
+ u32 pll5_tun; /* 0x24 pll5 tuning */
+ u32 pll6_cfg; /* 0x28 pll6 control */
+ u32 pll6_tun; /* 0x2c pll6 tuning */
+ u32 pll7_cfg; /* 0x30 pll7 control */
+ u32 pll1_tun2; /* 0x34 pll5 tuning2 */
+ u8 res2[0x4];
+ u32 pll5_tun2; /* 0x3c pll5 tuning2 */
+ u8 res3[0xc];
+ u32 pll_lock_dbg; /* 0x4c pll lock time debug */
+ u32 osc24m_cfg; /* 0x50 osc24m control */
+ u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */
+ u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */
+ u32 axi_gate; /* 0x5c axi module clock gating */
+ u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
+ u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
+ u32 apb0_gate; /* 0x68 apb0 module clock gating */
+ u32 apb1_gate; /* 0x6c apb1 module clock gating */
+ u8 res4[0x10];
+ u32 nand_sclk_cfg; /* 0x80 nand sub clock control */
+ u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */
+ u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
+ u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
+ u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
+ u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
+ u32 ts_clk_cfg; /* 0x98 transport stream clock control */
+ u32 ss_clk_cfg; /* 0x9c */
+ u32 spi0_clk_cfg; /* 0xa0 */
+ u32 spi1_clk_cfg; /* 0xa4 */
+ u32 spi2_clk_cfg; /* 0xa8 */
+ u32 pata_clk_cfg; /* 0xac */
+ u32 ir0_clk_cfg; /* 0xb0 */
+ u32 ir1_clk_cfg; /* 0xb4 */
+ u32 iis_clk_cfg; /* 0xb8 */
+ u32 ac97_clk_cfg; /* 0xbc */
+ u32 spdif_clk_cfg; /* 0xc0 */
+ u32 keypad_clk_cfg; /* 0xc4 */
+ u32 sata_clk_cfg; /* 0xc8 */
+ u32 usb_clk_cfg; /* 0xcc */
+ u32 gps_clk_cfg; /* 0xd0 */
+ u32 spi3_clk_cfg; /* 0xd4 */
+ u8 res5[0x28];
+ u32 dram_clk_cfg; /* 0x100 */
+ u32 be0_clk_cfg; /* 0x104 */
+ u32 be1_clk_cfg; /* 0x108 */
+ u32 fe0_clk_cfg; /* 0x10c */
+ u32 fe1_clk_cfg; /* 0x110 */
+ u32 mp_clk_cfg; /* 0x114 */
+ u32 lcd0_ch0_clk_cfg; /* 0x118 */
+ u32 lcd1_ch0_clk_cfg; /* 0x11c */
+ u32 csi_isp_clk_cfg; /* 0x120 */
+ u8 res6[0x4];
+ u32 tvd_clk_reg; /* 0x128 */
+ u32 lcd0_ch1_clk_cfg; /* 0x12c */
+ u32 lcd1_ch1_clk_cfg; /* 0x130 */
+ u32 csi0_clk_cfg; /* 0x134 */
+ u32 csi1_clk_cfg; /* 0x138 */
+ u32 ve_clk_cfg; /* 0x13c */
+ u32 audio_codec_clk_cfg; /* 0x140 */
+ u32 avs_clk_cfg; /* 0x144 */
+ u32 ace_clk_cfg; /* 0x148 */
+ u32 lvds_clk_cfg; /* 0x14c */
+ u32 hdmi_clk_cfg; /* 0x150 */
+ u32 mali_clk_cfg; /* 0x154 */
+ u8 res7[0x4];
+ u32 mbus_clk_cfg; /* 0x15c */
+ u8 res8[0x4];
+ u32 gmac_clk_cfg; /* 0x164 */
+};
+
+/* apb1 bit field */
+#define APB1_CLK_SRC_OSC24M (0x0 << 24)
+#define APB1_CLK_SRC_PLL6 (0x1 << 24)
+#define APB1_CLK_SRC_LOSC (0x2 << 24)
+#define APB1_CLK_SRC_MASK (0x3 << 24)
+#define APB1_CLK_RATE_N_1 (0x0 << 16)
+#define APB1_CLK_RATE_N_2 (0x1 << 16)
+#define APB1_CLK_RATE_N_4 (0x2 << 16)
+#define APB1_CLK_RATE_N_8 (0x3 << 16)
+#define APB1_CLK_RATE_N_MASK (3 << 16)
+#define APB1_CLK_RATE_M(m) (((m)-1) << 0)
+#define APB1_CLK_RATE_M_MASK (0x1f << 0)
+
+/* apb1 gate field */
+#define APB1_GATE_UART_SHIFT (16)
+#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)
+#define APB1_GATE_TWI_SHIFT (0)
+#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT)
+
+/* clock divide */
+#define AXI_DIV_SHIFT (0)
+#define AXI_DIV_1 0
+#define AXI_DIV_2 1
+#define AXI_DIV_3 2
+#define AXI_DIV_4 3
+#define AHB_DIV_SHIFT (4)
+#define AHB_DIV_1 0
+#define AHB_DIV_2 1
+#define AHB_DIV_4 2
+#define AHB_DIV_8 3
+#define APB0_DIV_SHIFT (8)
+#define APB0_DIV_1 0
+#define APB0_DIV_2 1
+#define APB0_DIV_4 2
+#define APB0_DIV_8 3
+#define CPU_CLK_SRC_SHIFT (16)
+#define CPU_CLK_SRC_OSC24M 1
+#define CPU_CLK_SRC_PLL1 2
+
+#define CCM_PLL1_CFG_ENABLE_SHIFT 31
+#define CCM_PLL1_CFG_VCO_RST_SHIFT 30
+#define CCM_PLL1_CFG_VCO_BIAS_SHIFT 26
+#define CCM_PLL1_CFG_PLL4_EXCH_SHIFT 25
+#define CCM_PLL1_CFG_BIAS_CUR_SHIFT 20
+#define CCM_PLL1_CFG_DIVP_SHIFT 16
+#define CCM_PLL1_CFG_LCK_TMR_SHIFT 13
+#define CCM_PLL1_CFG_FACTOR_N_SHIFT 8
+#define CCM_PLL1_CFG_FACTOR_K_SHIFT 4
+#define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT 3
+#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2
+#define CCM_PLL1_CFG_FACTOR_M_SHIFT 0
+
+#define PLL1_CFG_DEFAULT 0xa1005000
+
+#define PLL6_CFG_DEFAULT 0xa1009911
+
+/* nand clock */
+#define NAND_CLK_SRC_OSC24 0
+#define NAND_CLK_DIV_N 0
+#define NAND_CLK_DIV_M 0
+
+/* gps clock */
+#define GPS_SCLK_GATING_OFF 0
+#define GPS_RESET 0
+
+/* ahb clock gate bit offset */
+#define AHB_GATE_OFFSET_GPS 26
+#define AHB_GATE_OFFSET_SATA 25
+#define AHB_GATE_OFFSET_PATA 24
+#define AHB_GATE_OFFSET_SPI3 23
+#define AHB_GATE_OFFSET_SPI2 22
+#define AHB_GATE_OFFSET_SPI1 21
+#define AHB_GATE_OFFSET_SPI0 20
+#define AHB_GATE_OFFSET_TS0 18
+#define AHB_GATE_OFFSET_EMAC 17
+#define AHB_GATE_OFFSET_ACE 16
+#define AHB_GATE_OFFSET_DLL 15
+#define AHB_GATE_OFFSET_SDRAM 14
+#define AHB_GATE_OFFSET_NAND 13
+#define AHB_GATE_OFFSET_MS 12
+#define AHB_GATE_OFFSET_MMC3 11
+#define AHB_GATE_OFFSET_MMC2 10
+#define AHB_GATE_OFFSET_MMC1 9
+#define AHB_GATE_OFFSET_MMC0 8
+#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_BIST 7
+#define AHB_GATE_OFFSET_DMA 6
+#define AHB_GATE_OFFSET_SS 5
+#define AHB_GATE_OFFSET_USB_OHCI1 4
+#define AHB_GATE_OFFSET_USB_EHCI1 3
+#define AHB_GATE_OFFSET_USB_OHCI0 2
+#define AHB_GATE_OFFSET_USB_EHCI0 1
+#define AHB_GATE_OFFSET_USB 0
+
+/* ahb clock gate bit offset (second register) */
+#define AHB_GATE_OFFSET_GMAC 17
+
+#define CCM_AHB_GATE_GPS (0x1 << 26)
+#define CCM_AHB_GATE_SDRAM (0x1 << 14)
+#define CCM_AHB_GATE_DLL (0x1 << 15)
+#define CCM_AHB_GATE_ACE (0x1 << 16)
+
+#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
+#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
+#define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2)
+#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
+#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
+#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
+#define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_LDO (0x1 << 7)
+#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
+#define CCM_PLL5_CTRL_N_X(n) (n)
+#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
+#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
+#define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_BW (0x1 << 18)
+#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19)
+#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20)
+#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f)
+#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25)
+#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29)
+#define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
+#define CCM_PLL5_CTRL_EN (0x1 << 31)
+
+#define CCM_PLL6_CTRL_N_SHIFT 8
+#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT 4
+#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+
+#define CCM_GPS_CTRL_RESET (0x1 << 0)
+#define CCM_GPS_CTRL_GATE (0x1 << 1)
+
+#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15)
+
+#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0)
+#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf)
+#define CCM_MBUS_CTRL_M_X(n) ((n) - 1)
+#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16)
+#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf)
+#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0)))
+#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24)
+#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3)
+#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0
+#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1
+#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
+#define CCM_MBUS_CTRL_GATE (0x1 << 31)
+
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
+#define CCM_MMC_CTRL_PLL5 (0x2 << 24)
+
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+
+#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
+#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
+#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
+#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
+#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+
+#endif /* _SUNXI_CLOCK_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
new file mode 100644
index 0000000..c3e636e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <linux/types.h>
+
+void sdelay(unsigned long);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
new file mode 100644
index 0000000..6aacfd7
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Configuration settings for the Allwinner A10-evb board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_TIMER_H_
+#define _SUNXI_TIMER_H_
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+/* General purpose timer */
+struct sunxi_timer {
+ u32 ctl;
+ u32 inter;
+ u32 val;
+ u8 res[4];
+};
+
+/* Audio video sync*/
+struct sunxi_avs {
+ u32 ctl; /* 0x80 */
+ u32 cnt0; /* 0x84 */
+ u32 cnt1; /* 0x88 */
+ u32 div; /* 0x8c */
+};
+
+/* 64 bit counter */
+struct sunxi_64cnt {
+ u32 ctl; /* 0xa0 */
+ u32 lo; /* 0xa4 */
+ u32 hi; /* 0xa8 */
+};
+
+/* Watchdog */
+struct sunxi_wdog {
+ u32 ctl; /* 0x90 */
+ u32 mode; /* 0x94 */
+};
+
+/* Rtc */
+struct sunxi_rtc {
+ u32 ctl; /* 0x100 */
+ u32 yymmdd; /* 0x104 */
+ u32 hhmmss; /* 0x108 */
+};
+
+/* Alarm */
+struct sunxi_alarm {
+ u32 ddhhmmss; /* 0x10c */
+ u32 hhmmss; /* 0x110 */
+ u32 en; /* 0x114 */
+ u32 irqen; /* 0x118 */
+ u32 irqsta; /* 0x11c */
+};
+
+/* Timer general purpose register */
+struct sunxi_tgp {
+ u32 tgpd;
+};
+
+struct sunxi_timer_reg {
+ u32 tirqen; /* 0x00 */
+ u32 tirqsta; /* 0x04 */
+ u8 res1[8];
+ struct sunxi_timer timer[6]; /* We have 6 timers */
+ u8 res2[16];
+ struct sunxi_avs avs;
+ struct sunxi_wdog wdog;
+ u8 res3[8];
+ struct sunxi_64cnt cnt64;
+ u8 res4[0x58];
+ struct sunxi_rtc rtc;
+ struct sunxi_alarm alarm;
+ struct sunxi_tgp tgp[4];
+ u8 res5[8];
+ u32 cpu_cfg;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif