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-rw-r--r--arch/arm/include/asm/arch-at91/spl.h24
-rw-r--r--arch/arm/include/asm/arch-davinci/emif_defs.h72
-rw-r--r--arch/arm/include/asm/arch-davinci/hardware.h1
-rw-r--r--arch/arm/include/asm/arch-davinci/nand_defs.h38
-rw-r--r--arch/arm/include/asm/arch-davinci/spl.h16
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware-k2hk.h7
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware.h30
-rw-r--r--arch/arm/include/asm/arch-keystone/nand_defs.h23
-rw-r--r--arch/arm/include/asm/arch-mx35/spl.h22
-rw-r--r--arch/arm/include/asm/arch-mx5/spl.h13
-rw-r--r--arch/arm/include/asm/arch-mx6/hab.h17
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/iomux.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6-ddr.h231
-rw-r--r--arch/arm/include/asm/arch-mx6/sys_proto.h4
-rw-r--r--arch/arm/include/asm/arch-tegra114/spl.h22
-rw-r--r--arch/arm/include/asm/arch-tegra124/spl.h13
-rw-r--r--arch/arm/include/asm/arch-tegra20/spl.h12
-rw-r--r--arch/arm/include/asm/arch-tegra30/spl.h12
-rw-r--r--arch/arm/include/asm/arch-tnetv107x/emif_defs.h1
-rw-r--r--arch/arm/include/asm/arch-tnetv107x/hardware.h2
-rw-r--r--arch/arm/include/asm/arch-tnetv107x/nand_defs.h23
-rw-r--r--arch/arm/include/asm/atomic.h2
-rw-r--r--arch/arm/include/asm/bitops.h2
-rw-r--r--arch/arm/include/asm/imx-common/iomux-v3.h25
-rw-r--r--arch/arm/include/asm/io.h3
-rw-r--r--arch/arm/include/asm/proc-armv/processor.h2
-rw-r--r--arch/arm/include/asm/processor.h2
-rw-r--r--arch/arm/include/asm/ptrace.h2
-rw-r--r--arch/arm/include/asm/spl.h20
-rw-r--r--arch/arm/include/asm/ti-common/davinci_nand.h (renamed from arch/arm/include/asm/arch-keystone/emif_defs.h)55
-rw-r--r--arch/arm/include/asm/ti-common/ti-aemif.h39
32 files changed, 386 insertions, 353 deletions
diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h
deleted file mode 100644
index d8a87da..0000000
--- a/arch/arm/include/asm/arch-at91/spl.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-enum {
- BOOT_DEVICE_NONE,
-#ifdef CONFIG_SYS_USE_MMC
- BOOT_DEVICE_MMC1,
- BOOT_DEVICE_MMC2,
- BOOT_DEVICE_MMC2_2,
-#elif CONFIG_SYS_USE_NANDFLASH
- BOOT_DEVICE_NAND,
-#elif CONFIG_SYS_USE_SERIALFLASH
- BOOT_DEVICE_SPI,
-#endif
-};
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h
deleted file mode 100644
index 7e19cfe..0000000
--- a/arch/arm/include/asm/arch-davinci/emif_defs.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _EMIF_DEFS_H_
-#define _EMIF_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-struct davinci_emif_regs {
- u_int32_t ercsr;
- u_int32_t awccr;
- u_int32_t sdbcr;
- u_int32_t sdrcr;
- u_int32_t ab1cr;
- u_int32_t ab2cr;
- u_int32_t ab3cr;
- u_int32_t ab4cr;
- u_int32_t sdtimr;
- u_int32_t ddrsr;
- u_int32_t ddrphycr;
- u_int32_t ddrphysr;
- u_int32_t totar;
- u_int32_t totactr;
- u_int32_t ddrphyid_rev;
- u_int32_t sdsretr;
- u_int32_t eirr;
- u_int32_t eimr;
- u_int32_t eimsr;
- u_int32_t eimcr;
- u_int32_t ioctrlr;
- u_int32_t iostatr;
- u_int8_t rsvd0[8];
- u_int32_t nandfcr;
- u_int32_t nandfsr;
- u_int8_t rsvd1[8];
- u_int32_t nandfecc[4];
- u_int8_t rsvd2[60];
- u_int32_t nand4biteccload;
- u_int32_t nand4bitecc[4];
- u_int32_t nanderradd1;
- u_int32_t nanderradd2;
- u_int32_t nanderrval1;
- u_int32_t nanderrval2;
-};
-
-#define davinci_emif_regs \
- ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
-
-#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2))
-#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
-#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4)
-#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
-#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
-#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
-#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
-
-/* Chip Select setup */
-#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
-#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
-#define DAVINCI_ABCR_WSETUP(n) (n << 26)
-#define DAVINCI_ABCR_WSTROBE(n) (n << 20)
-#define DAVINCI_ABCR_WHOLD(n) (n << 17)
-#define DAVINCI_ABCR_RSETUP(n) (n << 13)
-#define DAVINCI_ABCR_RSTROBE(n) (n << 7)
-#define DAVINCI_ABCR_RHOLD(n) (n << 4)
-#define DAVINCI_ABCR_TA(n) (n << 2)
-#define DAVINCI_ABCR_ASIZE_16BIT 1
-#define DAVINCI_ABCR_ASIZE_8BIT 0
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 98fe56e..a4eb0bd 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -597,7 +597,6 @@ static inline enum davinci_clk_ids get_async3_src(void)
#if defined(CONFIG_SOC_DM365)
#include <asm/arch/aintc_defs.h>
#include <asm/arch/ddr2_defs.h>
-#include <asm/arch/emif_defs.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pll_defs.h>
#include <asm/arch/psc_defs.h>
diff --git a/arch/arm/include/asm/arch-davinci/nand_defs.h b/arch/arm/include/asm/arch-davinci/nand_defs.h
deleted file mode 100644
index dee1c6f..0000000
--- a/arch/arm/include/asm/arch-davinci/nand_defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts shamelesly stolen from Linux Kernel source tree.
- *
- * ------------------------------------------------------------
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _NAND_DEFS_H_
-#define _NAND_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_SOC_DM646X
-#define MASK_CLE 0x80000
-#define MASK_ALE 0x40000
-#else
-#define MASK_CLE 0x10
-#define MASK_ALE 0x08
-#endif
-
-#ifdef CONFIG_SYS_NAND_MASK_CLE
-#undef MASK_CLE
-#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
-#endif
-#ifdef CONFIG_SYS_NAND_MASK_ALE
-#undef MASK_ALE
-#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
-#endif
-
-#define NAND_READ_START 0x00
-#define NAND_READ_END 0x30
-#define NAND_STATUS 0x70
-
-extern void davinci_nand_init(struct nand_chip *nand);
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/spl.h b/arch/arm/include/asm/arch-davinci/spl.h
deleted file mode 100644
index 5afe0d4..0000000
--- a/arch/arm/include/asm/arch-davinci/spl.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_NAND 1
-#define BOOT_DEVICE_SPI 2
-#define BOOT_DEVICE_MMC1 3
-#define BOOT_DEVICE_MMC2 4 /* dummy */
-#define BOOT_DEVICE_MMC2_2 5 /* dummy */
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 7ac2662..50ce649 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -9,13 +9,6 @@
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE
-#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
-#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000
-#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000
-#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000
-
#define K2HK_PLL_CNTRL_BASE 0x02310000
#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 6c532ca..ffdecbf 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -22,32 +22,6 @@
typedef volatile unsigned int dv_reg;
typedef volatile unsigned int *dv_reg_p;
-#define ASYNC_EMIF_NUM_CS 4
-#define ASYNC_EMIF_MODE_NOR 0
-#define ASYNC_EMIF_MODE_NAND 1
-#define ASYNC_EMIF_MODE_ONENAND 2
-#define ASYNC_EMIF_PRESERVE -1
-
-struct async_emif_config {
- unsigned mode;
- unsigned select_strobe;
- unsigned extend_wait;
- unsigned wr_setup;
- unsigned wr_strobe;
- unsigned wr_hold;
- unsigned rd_setup;
- unsigned rd_strobe;
- unsigned rd_hold;
- unsigned turn_around;
- enum {
- ASYNC_EMIF_8 = 0,
- ASYNC_EMIF_16 = 1,
- ASYNC_EMIF_32 = 2,
- } width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
struct ddr3_phy_config {
unsigned int pllcr;
unsigned int pgcr1_mask;
@@ -145,6 +119,10 @@ struct ddr3_emif_config {
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
+/* AEMIF */
+#define KS2_AEMIF_CNTRL_BASE 0x21000a00
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
+
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif
diff --git a/arch/arm/include/asm/arch-keystone/nand_defs.h b/arch/arm/include/asm/arch-keystone/nand_defs.h
deleted file mode 100644
index 58417db..0000000
--- a/arch/arm/include/asm/arch-keystone/nand_defs.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * nand driver definitions to re-use davinci nand driver on Keystone2
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _NAND_DEFS_H_
-#define _NAND_DEFS_H_
-
-#include <asm/arch/hardware.h>
-#include <linux/mtd/nand.h>
-
-#define MASK_CLE 0x4000
-#define MASK_ALE 0x2000
-
-#define NAND_READ_START 0x00
-#define NAND_READ_END 0x30
-#define NAND_STATUS 0x70
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h
deleted file mode 100644
index d0efec2..0000000
--- a/arch/arm/include/asm/arch-mx35/spl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_NONE 0
-#define BOOT_DEVICE_XIP 1
-#define BOOT_DEVICE_XIPWAIT 2
-#define BOOT_DEVICE_NAND 3
-#define BOOT_DEVICE_ONENAND 4
-#define BOOT_DEVICE_MMC1 5
-#define BOOT_DEVICE_MMC2 6
-#define BOOT_DEVICE_MMC2_2 7
-#define BOOT_DEVICE_NOR 8
-#define BOOT_DEVICE_I2C 9
-#define BOOT_DEVICE_SPI 10
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx5/spl.h b/arch/arm/include/asm/arch-mx5/spl.h
deleted file mode 100644
index 20c6cae..0000000
--- a/arch/arm/include/asm/arch-mx5/spl.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2013 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_SPL_H__
-#define __ASM_ARCH_SPL_H__
-
-#define BOOT_DEVICE_NONE 0
-#define BOOT_DEVICE_NAND 1
-
-#endif /* __ASM_ARCH_SPL_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/arch-mx6/hab.h
index d724f20..1f12695 100644
--- a/arch/arm/include/asm/arch-mx6/hab.h
+++ b/arch/arm/include/asm/arch-mx6/hab.h
@@ -53,12 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
typedef void hapi_clock_init_t(void);
-#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
-#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
-#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
-#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
-#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
-#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D)
+#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
+#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
+#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
+#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
+
+#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
+#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)
+#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8)
+#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C)
+#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0)
#define HAB_CID_ROM 0 /**< ROM Caller ID */
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 1f19727..a69a753 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -217,6 +217,8 @@
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_2 0x12
+#define CHIP_REV_1_5 0x15
#define IRAM_SIZE 0x00040000
#define FEC_QUIRK_ENET_MAC
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index f9ee0d9..6a4a632 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -39,7 +39,7 @@
#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4)
#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10)
#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12)
-#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12)
#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12)
/*
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 43d377a..d544d2e 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -6,6 +6,7 @@
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_MX6Q
#include "mx6q-ddr.h"
#else
@@ -15,6 +16,236 @@
#error "Please select cpu"
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
+#else
+
+/* MMDC P0/P1 Registers */
+struct mmdc_p_regs {
+ u32 mdctl;
+ u32 mdpdc;
+ u32 mdotc;
+ u32 mdcfg0;
+ u32 mdcfg1;
+ u32 mdcfg2;
+ u32 mdmisc;
+ u32 mdscr;
+ u32 mdref;
+ u32 res1[2];
+ u32 mdrwd;
+ u32 mdor;
+ u32 res2[3];
+ u32 mdasp;
+ u32 res3[240];
+ u32 mapsr;
+ u32 res4[254];
+ u32 mpzqhwctrl;
+ u32 res5[2];
+ u32 mpwldectrl0;
+ u32 mpwldectrl1;
+ u32 res6;
+ u32 mpodtctrl;
+ u32 mprddqby0dl;
+ u32 mprddqby1dl;
+ u32 mprddqby2dl;
+ u32 mprddqby3dl;
+ u32 res7[4];
+ u32 mpdgctrl0;
+ u32 mpdgctrl1;
+ u32 res8;
+ u32 mprddlctl;
+ u32 res9;
+ u32 mpwrdlctl;
+ u32 res10[25];
+ u32 mpmur0;
+};
+
+/*
+ * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
+ */
+#define MX6DQ_IOM_DDR_BASE 0x020e0500
+struct mx6dq_iomux_ddr_regs {
+ u32 res1[3];
+ u32 dram_sdqs5;
+ u32 dram_dqm5;
+ u32 dram_dqm4;
+ u32 dram_sdqs4;
+ u32 dram_sdqs3;
+ u32 dram_dqm3;
+ u32 dram_sdqs2;
+ u32 dram_dqm2;
+ u32 res2[16];
+ u32 dram_cas;
+ u32 res3[2];
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 res4[2];
+ u32 dram_sdclk_0;
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdclk_1;
+ u32 dram_sdcke1;
+ u32 dram_sdodt0;
+ u32 dram_sdodt1;
+ u32 res5;
+ u32 dram_sdqs0;
+ u32 dram_dqm0;
+ u32 dram_sdqs1;
+ u32 dram_dqm1;
+ u32 dram_sdqs6;
+ u32 dram_dqm6;
+ u32 dram_sdqs7;
+ u32 dram_dqm7;
+};
+
+#define MX6DQ_IOM_GRP_BASE 0x020e0700
+struct mx6dq_iomux_grp_regs {
+ u32 res1[18];
+ u32 grp_b7ds;
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 res2;
+ u32 grp_ddrpke;
+ u32 res3[6];
+ u32 grp_ddrmode;
+ u32 res4[3];
+ u32 grp_b0ds;
+ u32 grp_b1ds;
+ u32 grp_ctlds;
+ u32 res5;
+ u32 grp_b2ds;
+ u32 grp_ddr_type;
+ u32 grp_b3ds;
+ u32 grp_b4ds;
+ u32 grp_b5ds;
+ u32 grp_b6ds;
+};
+
+#define MX6SDL_IOM_DDR_BASE 0x020e0400
+struct mx6sdl_iomux_ddr_regs {
+ u32 res1[25];
+ u32 dram_cas;
+ u32 res2[2];
+ u32 dram_dqm0;
+ u32 dram_dqm1;
+ u32 dram_dqm2;
+ u32 dram_dqm3;
+ u32 dram_dqm4;
+ u32 dram_dqm5;
+ u32 dram_dqm6;
+ u32 dram_dqm7;
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 res3[2];
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdcke1;
+ u32 dram_sdclk_0;
+ u32 dram_sdclk_1;
+ u32 dram_sdodt0;
+ u32 dram_sdodt1;
+ u32 dram_sdqs0;
+ u32 dram_sdqs1;
+ u32 dram_sdqs2;
+ u32 dram_sdqs3;
+ u32 dram_sdqs4;
+ u32 dram_sdqs5;
+ u32 dram_sdqs6;
+ u32 dram_sdqs7;
+};
+
+#define MX6SDL_IOM_GRP_BASE 0x020e0700
+struct mx6sdl_iomux_grp_regs {
+ u32 res1[18];
+ u32 grp_b7ds;
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 grp_ddrpke;
+ u32 res2[2];
+ u32 grp_ddrmode;
+ u32 grp_b0ds;
+ u32 res3;
+ u32 grp_ctlds;
+ u32 grp_b1ds;
+ u32 grp_ddr_type;
+ u32 grp_b2ds;
+ u32 grp_b3ds;
+ u32 grp_b4ds;
+ u32 grp_b5ds;
+ u32 res4;
+ u32 grp_b6ds;
+};
+
+/* Device Information: Varies per DDR3 part number and speed grade */
+struct mx6_ddr3_cfg {
+ u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
+ u8 density; /* chip density (Gb) (1,2,4,8) */
+ u8 width; /* bus width (bits) (4,8,16) */
+ u8 banks; /* number of banks */
+ u8 rowaddr; /* row address bits (11-16)*/
+ u8 coladdr; /* col address bits (9-12) */
+ u8 pagesz; /* page size (K) (1-2) */
+ u16 trcd; /* tRCD=tRP=CL (ns*100) */
+ u16 trcmin; /* tRC min (ns*100) */
+ u16 trasmin; /* tRAS min (ns*100) */
+ u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
+};
+
+/* System Information: Varies per board design, layout, and term choices */
+struct mx6_ddr_sysinfo {
+ u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
+ u8 cs_density; /* density per chip select (Gb) */
+ u8 ncs; /* number chip selects used (1|2) */
+ char cs1_mirror;/* enable address mirror (0|1) */
+ char bi_on; /* Bank interleaving enable */
+ u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
+ u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
+ u8 ralat; /* Read Additional Latency (0-7) */
+ u8 walat; /* Write Additional Latency (0-3) */
+ u8 mif3_mode; /* Command prediction working mode */
+ u8 rst_to_cke; /* Time from SDE enable to CKE rise */
+ u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
+};
+
+/*
+ * Board specific calibration:
+ * This includes write leveling calibration values as well as DQS gating
+ * and read/write delays. These values are board/layout/device specific.
+ * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
+ * (DOC-96412) to determine these values over a range of boards and
+ * temperatures.
+ */
+struct mx6_mmdc_calibration {
+ /* write leveling calibration */
+ u32 p0_mpwldectrl0;
+ u32 p0_mpwldectrl1;
+ u32 p1_mpwldectrl0;
+ u32 p1_mpwldectrl1;
+ /* read DQS gating */
+ u32 p0_mpdgctrl0;
+ u32 p0_mpdgctrl1;
+ u32 p1_mpdgctrl0;
+ u32 p1_mpdgctrl1;
+ /* read delay */
+ u32 p0_mprddlctl;
+ u32 p1_mprddlctl;
+ /* write delay */
+ u32 p0_mpwrdlctl;
+ u32 p1_mpwrdlctl;
+};
+
+/* configure iomux (pinctl/padctl) */
+void mx6dq_dram_iocfg(unsigned width,
+ const struct mx6dq_iomux_ddr_regs *,
+ const struct mx6dq_iomux_grp_regs *);
+void mx6sdl_dram_iocfg(unsigned width,
+ const struct mx6sdl_iomux_ddr_regs *,
+ const struct mx6sdl_iomux_grp_regs *);
+
+/* configure mx6 mmdc registers */
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
+ const struct mx6_mmdc_calibration *,
+ const struct mx6_ddr3_cfg *);
+
+#endif /* CONFIG_SPL_BUILD */
#define MX6_MMDC_P0_MDCTL 0x021b0000
#define MX6_MMDC_P0_MDPDC 0x021b0004
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 38851a1..42d30f5 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -11,7 +11,9 @@
#include <asm/imx-common/regs-common.h>
#include "../arch-imx/cpu.h"
-#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+#define soc_rev() (get_cpu_rev() & 0xFF)
+#define is_soc_rev(rev) (soc_rev() - rev)
+
u32 get_cpu_rev(void);
/* returns MXC_CPU_ value */
diff --git a/arch/arm/include/asm/arch-tegra114/spl.h b/arch/arm/include/asm/arch-tegra114/spl.h
deleted file mode 100644
index ebb16fe..0000000
--- a/arch/arm/include/asm/arch-tegra114/spl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM 1
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra124/spl.h b/arch/arm/include/asm/arch-tegra124/spl.h
deleted file mode 100644
index e266395..0000000
--- a/arch/arm/include/asm/arch-tegra124/spl.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * (C) Copyright 2010-2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM 1
-
-#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/spl.h b/arch/arm/include/asm/arch-tegra20/spl.h
deleted file mode 100644
index 8953b00..0000000
--- a/arch/arm/include/asm/arch-tegra20/spl.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM 1
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra30/spl.h b/arch/arm/include/asm/arch-tegra30/spl.h
deleted file mode 100644
index 8953b00..0000000
--- a/arch/arm/include/asm/arch-tegra30/spl.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM 1
-
-#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
deleted file mode 100644
index 9969a01..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm/arch-davinci/emif_defs.h>
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
index 2a7ca4e..d458e0b 100644
--- a/arch/arm/include/asm/arch-tnetv107x/hardware.h
+++ b/arch/arm/include/asm/arch-tnetv107x/hardware.h
@@ -155,4 +155,6 @@ int wdt_kick(void);
#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
+
#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h b/arch/arm/include/asm/arch-tnetv107x/nand_defs.h
deleted file mode 100644
index b298fba..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * TNETV107X: NAND definitions
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _NAND_DEFS_H_
-#define _NAND_DEFS_H_
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/emif_defs.h>
-
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
-
-#define MASK_CLE 0x4000
-#define MASK_ALE 0x2000
-
-#define NAND_READ_START 0x00
-#define NAND_READ_END 0x30
-#define NAND_STATUS 0x70
-
-extern void davinci_nand_init(struct nand_chip *nand);
-
-#endif
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 1b22eeb..34c07fe 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -25,7 +25,7 @@ typedef struct { volatile int counter; } atomic_t;
#define ATOMIC_INIT(i) { (i) }
#ifdef __KERNEL__
-#include <asm/proc/system.h>
+#include <asm/proc-armv/system.h>
#define atomic_read(v) ((v)->counter)
#define atomic_set(v,i) (((v)->counter) = (i))
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index 879e20e..597dafb 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -17,7 +17,7 @@
#ifdef __KERNEL__
-#include <asm/proc/system.h>
+#include <asm/proc-armv/system.h>
#define smp_mb__before_clear_bit() do { } while (0)
#define smp_mb__after_clear_bit() do { } while (0)
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index ff45618..e91d4ac 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -177,4 +177,29 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def); \
+}
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
+
#endif /* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 6a1f05a..9f35fd6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -437,4 +437,7 @@ out:
#endif /* __mem_isa */
#endif /* __KERNEL__ */
+
+#include <iotrace.h>
+
#endif /* __ASM_ARM_IO_H */
diff --git a/arch/arm/include/asm/proc-armv/processor.h b/arch/arm/include/asm/proc-armv/processor.h
index 5bfab7f..532f207 100644
--- a/arch/arm/include/asm/proc-armv/processor.h
+++ b/arch/arm/include/asm/proc-armv/processor.h
@@ -18,7 +18,7 @@
#ifndef __ASM_PROC_PROCESSOR_H
#define __ASM_PROC_PROCESSOR_H
-#include <asm/proc/domain.h>
+#include <asm/proc-armv/domain.h>
#define KERNEL_STACK_SIZE PAGE_SIZE
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 445d449..83481c6 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -45,7 +45,7 @@ typedef unsigned long mm_segment_t; /* domain register */
#if 0 /* XXX###XXX */
#include <asm/arch/memory.h>
#endif /* XXX###XXX */
-#include <asm/proc/processor.h>
+#include <asm/proc-armv/processor.h>
#include <asm/types.h>
union debug_insn {
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 73c9087..a836f6c 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -11,7 +11,7 @@
/* options set using PTRACE_SETOPTIONS */
#define PTRACE_O_TRACESYSGOOD 0x00000001
-#include <asm/proc/ptrace.h>
+#include <asm/proc-armv/ptrace.h>
#ifndef __ASSEMBLY__
#define pc_pointer(v) \
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 90e5a9d..18a319d 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -7,9 +7,29 @@
#ifndef _ASM_SPL_H_
#define _ASM_SPL_H_
+#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) || defined(CONFIG_ZYNQ) \
+ || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
+ || defined(CONFIG_EXYNOS4210)
/* Platform-specific defines */
#include <asm/arch/spl.h>
+#else
+enum {
+ BOOT_DEVICE_RAM,
+ BOOT_DEVICE_MMC1,
+ BOOT_DEVICE_MMC2,
+ BOOT_DEVICE_MMC2_2,
+ BOOT_DEVICE_NAND,
+ BOOT_DEVICE_ONENAND,
+ BOOT_DEVICE_NOR,
+ BOOT_DEVICE_UART,
+ BOOT_DEVICE_SPI,
+ BOOT_DEVICE_SATA,
+ BOOT_DEVICE_I2C,
+ BOOT_DEVICE_NONE
+};
+#endif
+
/* Linker symbols. */
extern char __bss_start[], __bss_end[];
diff --git a/arch/arm/include/asm/arch-keystone/emif_defs.h b/arch/arm/include/asm/ti-common/davinci_nand.h
index a3378aa..11407be 100644
--- a/arch/arm/include/asm/arch-keystone/emif_defs.h
+++ b/arch/arm/include/asm/ti-common/davinci_nand.h
@@ -1,23 +1,45 @@
/*
- * emif definitions to re-use davinci emif driver on Keystone2
+ * NAND Flash Driver
*
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2006-2014 Texas Instruments.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * Based on Linux DaVinci NAND driver by TI.
*/
-#ifndef _EMIF_DEFS_H_
-#define _EMIF_DEFS_H_
+#ifndef _DAVINCI_NAND_H_
+#define _DAVINCI_NAND_H_
+
+#include <linux/mtd/nand.h>
#include <asm/arch/hardware.h>
+#define NAND_READ_START 0x00
+#define NAND_READ_END 0x30
+#define NAND_STATUS 0x70
+
+#define MASK_CLE 0x10
+#define MASK_ALE 0x08
+
+#ifdef CONFIG_SYS_NAND_MASK_CLE
+#undef MASK_CLE
+#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#endif
+#ifdef CONFIG_SYS_NAND_MASK_ALE
+#undef MASK_ALE
+#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#endif
+
struct davinci_emif_regs {
uint32_t ercsr;
uint32_t awccr;
uint32_t sdbcr;
uint32_t sdrcr;
- uint32_t abncr[4];
+ union {
+ uint32_t abncr[4];
+ uint32_t ab1cr;
+ uint32_t ab2cr;
+ uint32_t ab3cr;
+ uint32_t ab4cr;
+ };
uint32_t sdtimr;
uint32_t ddrsr;
uint32_t ddrphycr;
@@ -56,18 +78,21 @@ struct davinci_emif_regs {
#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
+#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
/* Chip Select setup */
#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
-#define DAVINCI_ABCR_WSETUP(n) ((n) << 26)
-#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20)
-#define DAVINCI_ABCR_WHOLD(n) ((n) << 17)
-#define DAVINCI_ABCR_RSETUP(n) ((n) << 13)
-#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7)
-#define DAVINCI_ABCR_RHOLD(n) ((n) << 4)
-#define DAVINCI_ABCR_TA(n) ((n) << 2)
+#define DAVINCI_ABCR_WSETUP(n) (n << 26)
+#define DAVINCI_ABCR_WSTROBE(n) (n << 20)
+#define DAVINCI_ABCR_WHOLD(n) (n << 17)
+#define DAVINCI_ABCR_RSETUP(n) (n << 13)
+#define DAVINCI_ABCR_RSTROBE(n) (n << 7)
+#define DAVINCI_ABCR_RHOLD(n) (n << 4)
+#define DAVINCI_ABCR_TA(n) (n << 2)
#define DAVINCI_ABCR_ASIZE_16BIT 1
#define DAVINCI_ABCR_ASIZE_8BIT 0
+void davinci_nand_init(struct nand_chip *nand);
+
#endif
diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h
new file mode 100644
index 0000000..4a311d4
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/ti-aemif.h
@@ -0,0 +1,39 @@
+/*
+ * AEMIF definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _AEMIF_H_
+#define _AEMIF_H_
+
+#define AEMIF_NUM_CS 4
+#define AEMIF_MODE_NOR 0
+#define AEMIF_MODE_NAND 1
+#define AEMIF_MODE_ONENAND 2
+#define AEMIF_PRESERVE -1
+
+struct aemif_config {
+ unsigned mode;
+ unsigned select_strobe;
+ unsigned extend_wait;
+ unsigned wr_setup;
+ unsigned wr_strobe;
+ unsigned wr_hold;
+ unsigned rd_setup;
+ unsigned rd_strobe;
+ unsigned rd_hold;
+ unsigned turn_around;
+ enum {
+ AEMIF_WIDTH_8 = 0,
+ AEMIF_WIDTH_16 = 1,
+ AEMIF_WIDTH_32 = 2,
+ } width;
+};
+
+void aemif_init(int num_cs, struct aemif_config *config);
+
+#endif