diff options
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/arch-omap4/clocks.h | 45 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-omap4/omap.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-omap5/clocks.h | 50 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/omap_common.h | 63 |
5 files changed, 67 insertions, 97 deletions
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 4710d88..ceb3367 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -242,55 +242,10 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 -#define NUM_SYS_CLKS 7 - -struct dpll_regs { - u32 cm_clkmode_dpll; - u32 cm_idlest_dpll; - u32 cm_autoidle_dpll; - u32 cm_clksel_dpll; - u32 cm_div_m2_dpll; - u32 cm_div_m3_dpll; - u32 cm_div_m4_dpll; - u32 cm_div_m5_dpll; - u32 cm_div_m6_dpll; - u32 cm_div_m7_dpll; -}; - -/* DPLL parameter table */ -struct dpll_params { - u32 m; - u32 n; - s8 m2; - s8 m3; - s8 m4; - s8 m5; - s8 m6; - s8 m7; -}; - -extern const u32 sys_clk_array[8]; - void scale_vcores(void); void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); u32 get_offset_code(u32 offset); -u32 omap_ddr_clk(void); void do_scale_vcore(u32 vcore_reg, u32 volt_mv); -void setup_post_dividers(u32 const base, const struct dpll_params *params); -u32 get_sys_clk_index(void); -void enable_basic_clocks(void); -void enable_basic_uboot_clocks(void); -void enable_non_essential_clocks(void); -void do_enable_clocks(u32 const *clk_domains, - u32 const *clk_modules_hw_auto, - u32 const *clk_modules_explicit_en, - u8 wait_for_enable); -const struct dpll_params *get_mpu_dpll_params(void); -const struct dpll_params *get_core_dpll_params(void); -const struct dpll_params *get_per_dpll_params(void); -const struct dpll_params *get_iva_dpll_params(void); -const struct dpll_params *get_usb_dpll_params(void); -const struct dpll_params *get_abe_dpll_params(void); struct omap4_scrm_regs { u32 revision; /* 0x0000 */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 86ba335..1c0ce9b 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -179,7 +179,8 @@ struct control_lpddr2io_regs { #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) -#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C) /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 67e74ca..063347f 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -234,58 +234,8 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 -#define NUM_SYS_CLKS 7 - -struct dpll_regs { - u32 cm_clkmode_dpll; - u32 cm_idlest_dpll; - u32 cm_autoidle_dpll; - u32 cm_clksel_dpll; - u32 cm_div_m2_dpll; - u32 cm_div_m3_dpll; - u32 cm_div_h11_dpll; - u32 cm_div_h12_dpll; - u32 cm_div_h13_dpll; - u32 cm_div_h14_dpll; - u32 reserved[3]; - u32 cm_div_h22_dpll; - u32 cm_div_h23_dpll; -}; - -/* DPLL parameter table */ -struct dpll_params { - u32 m; - u32 n; - s8 m2; - s8 m3; - s8 h11; - s8 h12; - s8 h13; - s8 h14; - s8 h22; - s8 h23; -}; - -extern const u32 sys_clk_array[8]; - void scale_vcores(void); void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); u32 get_offset_code(u32 offset); -u32 omap_ddr_clk(void); void do_scale_vcore(u32 vcore_reg, u32 volt_mv); -void setup_post_dividers(u32 const base, const struct dpll_params *params); -u32 get_sys_clk_index(void); -void enable_basic_clocks(void); -void enable_non_essential_clocks(void); -void enable_basic_uboot_clocks(void); -void do_enable_clocks(u32 const *clk_domains, - u32 const *clk_modules_hw_auto, - u32 const *clk_modules_explicit_en, - u8 wait_for_enable); -const struct dpll_params *get_mpu_dpll_params(void); -const struct dpll_params *get_core_dpll_params(void); -const struct dpll_params *get_per_dpll_params(void); -const struct dpll_params *get_iva_dpll_params(void); -const struct dpll_params *get_usb_dpll_params(void); -const struct dpll_params *get_abe_dpll_params(void); #endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 50e055e..7123694 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -272,7 +272,8 @@ struct omap_sys_ctrl_regs { #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C) /* Silicon revisions */ #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index fcf9ce5..c2d8388 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -27,6 +27,8 @@ #include <common.h> +#define NUM_SYS_CLKS 7 + struct prcm_regs { /* cm1.ckgen */ u32 cm_clksel_core; @@ -324,11 +326,72 @@ struct prcm_regs { u32 prm_vc_cfg_channel; }; +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 m4_h11; + s8 m5_h12; + s8 m6_h13; + s8 m7_h14; + s8 h22; + s8 h23; +}; + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_h11_dpll; + u32 cm_div_m5_h12_dpll; + u32 cm_div_m6_h13_dpll; + u32 cm_div_m7_h14_dpll; + u32 reserved[3]; + u32 cm_div_h22_dpll; + u32 cm_div_h23_dpll; +}; + +struct dplls { + const struct dpll_params *mpu; + const struct dpll_params *core; + const struct dpll_params *per; + const struct dpll_params *abe; + const struct dpll_params *iva; + const struct dpll_params *usb; +}; + extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; extern struct prcm_regs const omap4_prcm; +extern struct dplls const **dplls_data; +extern const u32 sys_clk_array[8]; void hw_data_init(void); + +const struct dpll_params *get_mpu_dpll_params(struct dplls const *); +const struct dpll_params *get_core_dpll_params(struct dplls const *); +const struct dpll_params *get_per_dpll_params(struct dplls const *); +const struct dpll_params *get_iva_dpll_params(struct dplls const *); +const struct dpll_params *get_usb_dpll_params(struct dplls const *); +const struct dpll_params *get_abe_dpll_params(struct dplls const *); + +void do_enable_clocks(u32 const *clk_domains, + u32 const *clk_modules_hw_auto, + u32 const *clk_modules_explicit_en, + u8 wait_for_enable); + +void setup_post_dividers(u32 const base, + const struct dpll_params *params); +u32 omap_ddr_clk(void); +u32 get_sys_clk_index(void); +void enable_basic_clocks(void); +void enable_basic_uboot_clocks(void); +void enable_non_essential_clocks(void); + /* Max value for DPLL multiplier M */ #define OMAP_DPLL_MAX_N 127 |