diff options
Diffstat (limited to 'arch/arm/include/asm')
47 files changed, 1988 insertions, 1517 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 87bb937..49b113d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -17,10 +17,22 @@ #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -#if defined(CONFIG_LS2085A) +/* + * Reserve secure memory + * To be aligned with MMU block size + */ +#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ + +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#ifdef CONFIG_LS2080A +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#endif +#ifdef CONFIG_LS2085A #define CONFIG_NUM_DDR_CONTROLLERS 3 +#define CONFIG_SYS_FSL_HAS_DP_DDR +#endif #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 @@ -44,6 +56,7 @@ #define CONFIG_SYS_FSL_CCSR_SCFG_LE #define CONFIG_SYS_FSL_ESDHC_LE #define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN @@ -60,6 +73,13 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) +#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) +#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ +#define CCN_HN_F_SAM_NODEID_MASK 0x7f +#define CCN_HN_F_SAM_NODEID_DDR0 0x4 +#define CCN_HN_F_SAM_NODEID_DDR1 0xe + #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) @@ -84,11 +104,20 @@ #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) +#define DCSR_CGACRE5 0x700070914ULL +#define EPU_EPCMPR5 0x700060914ULL +#define EPU_EPCCR5 0x700060814ULL +#define EPU_EPSMCR5 0x700060228ULL +#define EPU_EPECR5 0x700060314ULL +#define EPU_EPCTR5 0x700060a14ULL +#define EPU_EPGCR 0x700060000ULL + #define CONFIG_SYS_FSL_ERRATUM_A008336 #define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 +#define CONFIG_SYS_FSL_ERRATUM_A009635 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -103,8 +132,8 @@ #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ #define CONFIG_SYS_FSL_DDR_BE -#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_CCSR_GUR_BE #define CONFIG_SYS_FSL_CCSR_SCFG_BE @@ -113,6 +142,7 @@ #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_PEX_LUT_BE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -123,8 +153,8 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SNVS_LE -#define CONFIG_SYS_FSL_SEC_LE +#define CONFIG_SYS_FSL_SEC_MON_BE +#define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE #define CONFIG_KEY_REVOCATION @@ -136,6 +166,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A009929 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 2903996..e030430 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -8,8 +8,8 @@ #define _FSL_LAYERSCAPE_CPU_H static struct cpu_type cpu_type_list[] = { - CPU_TYPE_ENTRY(LS2085, LS2085, 8), CPU_TYPE_ENTRY(LS2080, LS2080, 8), + CPU_TYPE_ENTRY(LS2085, LS2085, 8), CPU_TYPE_ENTRY(LS2045, LS2045, 4), CPU_TYPE_ENTRY(LS1043, LS1043, 4), }; @@ -103,7 +103,7 @@ struct sys_mmu_table { u64 phys_addr; u64 size; u64 memory_type; - u64 share; + u64 attribute; }; struct table_info { @@ -115,7 +115,8 @@ struct table_info { static const struct sys_mmu_table early_mmu_table[] = { #ifdef CONFIG_FSL_LSCH3 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, /* For IFC Region #1, only the first 4MB is cache-enabled */ @@ -128,18 +129,27 @@ static const struct sys_mmu_table early_mmu_table[] = { { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, + /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, @@ -152,72 +162,95 @@ static const struct sys_mmu_table early_mmu_table[] = { static const struct sys_mmu_table final_mmu_table[] = { #ifdef CONFIG_FSL_LSCH3 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, /* For QBMAN portal, only the first 64MB is cache-enabled */ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN | PMD_SECT_NS }, { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#ifdef CONFIG_LS2085A + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, #endif { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, - CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE }, #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h index 4da73ab..099563e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h @@ -11,4 +11,5 @@ void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); void append_mmu_masters(void *blob, const char *smmu_path, const char *master_name, u32 *stream_ids, int count); void fdt_fixup_smmu_pcie(void *blob); +void fdt_fixup_board_enet(void *fdt); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index e1043b5..d1fbde7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -9,7 +9,7 @@ #include <config.h> -#if defined(CONFIG_LS2085A) +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) enum srds_prtcl { NONE = 0, PCIE1, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d941437..21b803f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -11,7 +11,8 @@ #define CONFIG_SYS_IMMR 0x01000000 #define CONFIG_SYS_DCSRBAR 0x20000000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) +#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) @@ -30,15 +31,15 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) -#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe90000) +#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 @@ -60,6 +61,10 @@ #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x10000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 6a70d44..91f3ce8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -51,8 +51,8 @@ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) -#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) +#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ @@ -69,6 +69,10 @@ #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) +/* SATA */ +#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) +#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) + /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) @@ -78,6 +82,10 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x80000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC /* Device Configuration */ #define DCFG_BASE 0x01e00000 @@ -115,7 +123,9 @@ struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; unsigned long freq_ddrbus; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR unsigned long freq_ddrbus2; +#endif unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h index 5c94530..954104b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h @@ -7,7 +7,7 @@ #ifndef __FSL_STREAM_ID_H #define __FSL_STREAM_ID_H -/* Stream IDs on ls2085a devices are not hardwired and are +/* Stream IDs on ls2080a devices are not hardwired and are * programmed by sw. There are a limited number of stream IDs * available, and the partitioning of them is scenario dependent. * This header defines the partitioning between legacy, PCI, @@ -17,7 +17,7 @@ * on the specific hardware config-- e.g. perhaps not all * PEX controllers are in use. * - * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for + * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bit streamID bit diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 5ed456e..1565592 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -23,6 +23,14 @@ #define scfg_out32(a, v) out_be32(a, v) #endif +#ifdef CONFIG_SYS_FSL_PEX_LUT_LE +#define pex_lut_in32(a) in_le32(a) +#define pex_lut_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) +#define pex_lut_in32(a) in_be32(a) +#define pex_lut_out32(a, v) out_be32(a, v) +#endif + struct cpu_type { char name[15]; u32 soc_ver; @@ -43,6 +51,37 @@ struct cpu_type { #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +/* ahci port register default value */ +#define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY_2_CFG 0x28184d1f +#define AHCI_PORT_PHY_3_CFG 0x0e081509 +#define AHCI_PORT_TRANS_CFG 0x08000029 + +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 axicc; /* AXI cache control */ + u32 paxic; /* port AXI config */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; + #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); #elif defined(CONFIG_FSL_LSCH2) @@ -50,4 +89,7 @@ void fsl_lsch2_early_init_f(void); #endif void cpu_name(char *name); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +void erratum_a009635(void); +#endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 845ba4f..d76514e 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -27,7 +27,6 @@ #endif #if defined(CONFIG_SYS_NS16550_SERIAL) -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 09ed980..89339fe 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -11,6 +11,8 @@ #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) #define IS_E_PROCESSOR(svr) (svr & 0x80000) +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) #define SOC_VER_SLS1020 0x00 #define SOC_VER_LS1020 0x10 @@ -31,7 +33,7 @@ #define RCWSR4_SRDS1_PRTCL_SHIFT 24 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 -#define TIMER_COMP_VAL 0xffffffff +#define TIMER_COMP_VAL 0xffffffffffffffffull #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define SYS_COUNTER_CTRL_ENABLE (1 << 24) @@ -150,6 +152,12 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 +#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 +#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 +#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 +#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 +#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 #define SCFG_ENDIANCR_LE 0x80000000 /* Supplemental Configuration Unit */ @@ -222,7 +230,7 @@ struct ccsr_scfg { u32 scfgrevcr; u32 coresrencr; u32 pex2pmrdsr; - u32 ddrc1cr; + u32 eddrtqcfg; u32 ddrc2cr; u32 ddrc3cr; u32 ddrc4cr; @@ -422,4 +430,7 @@ struct ccsr_ahci { u32 pberr; /* port 0/1 BIST error */ u32 cmds; /* port 0/1 CMD status error */ }; + +uint get_svr(void); + #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file mode 100644 index 0000000..f10cb91 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -0,0 +1,12 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_SOC_H +#define __FSL_LS102XA_SOC_H + +unsigned int get_soc_major_rev(void); +int arch_soc_init(void); +#endif /* __FSL_LS102XA_SOC_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h new file mode 100644 index 0000000..7ecc8ee --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3036_H +#define _ASM_ARCH_CRU_RK3036_H + +#include <common.h> + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define CPU_ACLK_HZ 150000000 +#define CPU_HCLK_HZ 300000000 +#define CPU_PCLK_HZ 300000000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +struct rk3036_cru { + struct rk3036_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + } pll[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[11]; + unsigned int reserved; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int reserved1[2]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved2[2]; + unsigned int cru_glb_cnt_th; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved3; + unsigned int cru_rst_st; + unsigned int reserved4[0x23]; + unsigned int cru_pll_mask_con; +}; +check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_POSTDIV1_MASK = 7, + PLL_POSTDIV1_SHIFT = 12, + PLL_FBDIV_MASK = 0xfff, + PLL_FBDIV_SHIFT = 0, + + /* PLLCON1 */ + PLL_DSMPD_MASK = 1, + PLL_DSMPD_SHIFT = 12, + PLL_LOCK_STATUS_MASK = 1, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_POSTDIV2_MASK = 7, + PLL_POSTDIV2_SHIFT = 6, + PLL_REFDIV_MASK = 0x3f, + PLL_REFDIV_SHIFT = 0, + PLL_RST_SHIFT = 14, + + /* CRU_MODE */ + GPLL_MODE_MASK = 3, + GPLL_MODE_SHIFT = 12, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + GPLL_MODE_DEEP, + DPLL_MODE_MASK = 1, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_MASK = 1, + APLL_MODE_SHIFT = 0, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + CPU_CLK_PLL_SEL_MASK = 3, + CPU_CLK_PLL_SEL_SHIFT = 14, + CPU_CLK_PLL_SEL_APLL = 0, + CPU_CLK_PLL_SEL_DPLL, + CPU_CLK_PLL_SEL_GPLL, + ACLK_CPU_DIV_MASK = 0x1f, + ACLK_CPU_DIV_SHIFT = 8, + CORE_CLK_PLL_SEL_MASK = 1, + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_DIV_CON_MASK = 0x1f, + CORE_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL1_CON */ + CPU_PCLK_DIV_MASK = 7, + CPU_PCLK_DIV_SHIFT = 12, + CPU_HCLK_DIV_MASK = 3, + CPU_HCLK_DIV_SHIFT = 8, + CORE_ACLK_DIV_MASK = 7, + CORE_ACLK_DIV_SHIFT = 4, + CORE_PERI_DIV_MASK = 0xf, + CORE_PERI_DIV_SHIFT = 0, + + /* CRU_CLKSEL10_CON */ + PERI_PLL_SEL_MASK = 3, + PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_APLL = 0, + PERI_PLL_DPLL, + PERI_PLL_GPLL, + PERI_PCLK_DIV_MASK = 3, + PERI_PCLK_DIV_SHIFT = 12, + PERI_HCLK_DIV_MASK = 3, + PERI_HCLK_DIV_SHIFT = 8, + PERI_ACLK_DIV_MASK = 0x1f, + PERI_ACLK_DIV_SHIFT = 0, + + /* CRU_CLKSEL11_CON */ + SDIO_DIV_MASK = 0x7f, + SDIO_DIV_SHIFT = 8, + MMC0_DIV_MASK = 0x7f, + MMC0_DIV_SHIFT = 0, + + /* CRU_CLKSEL12_CON */ + EMMC_PLL_MASK = 3, + EMMC_PLL_SHIFT = 12, + EMMC_SEL_APLL = 0, + EMMC_SEL_DPLL, + EMMC_SEL_GPLL, + EMMC_SEL_24M, + SDIO_PLL_MASK = 3, + SDIO_PLL_SHIFT = 10, + SDIO_SEL_APLL = 0, + SDIO_SEL_DPLL, + SDIO_SEL_GPLL, + SDIO_SEL_24M, + MMC0_PLL_MASK = 3, + MMC0_PLL_SHIFT = 8, + MMC0_SEL_APLL = 0, + MMC0_SEL_DPLL, + MMC0_SEL_GPLL, + MMC0_SEL_24M, + EMMC_DIV_MASK = 0x7f, + EMMC_DIV_SHIFT = 0, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h new file mode 100644 index 0000000..72d133c --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -0,0 +1,493 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK3036_H +#define _ASM_ARCH_GRF_RK3036_H + +#include <common.h> + +struct rk3036_grf { + unsigned int reserved[0x2a]; + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + + unsigned int reserved2[0x0a]; + unsigned int gpiods; + unsigned int reserved3[0x05]; + unsigned int gpio0l_pull; + unsigned int gpio0h_pull; + unsigned int gpio1l_pull; + unsigned int gpio1h_pull; + unsigned int gpio2l_pull; + unsigned int gpio2h_pull; + unsigned int reserved4[4]; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_status0; + unsigned int reserved5; + unsigned int soc_con3; + unsigned int reserved6; + unsigned int dmac_con0; + unsigned int dmac_con1; + unsigned int dmac_con2; + unsigned int reserved7[5]; + unsigned int uoc0_con5; + unsigned int reserved8[4]; + unsigned int uoc1_con4; + unsigned int uoc1_con5; + unsigned int reserved9; + unsigned int ddrc_stat; + unsigned int uoc_con6; + unsigned int soc_status1; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int cpu_con2; + unsigned int cpu_con3; + unsigned int reserved10; + unsigned int reserved11; + unsigned int cpu_status0; + unsigned int cpu_status1; + unsigned int os_reg[8]; + unsigned int reserved12[6]; + unsigned int dll_con[4]; + unsigned int dll_status[4]; + unsigned int dfi_wrnum; + unsigned int dfi_rdnum; + unsigned int dfi_actnum; + unsigned int dfi_timerval; + unsigned int nfi_fifo[4]; + unsigned int reserved13[0x10]; + unsigned int usbphy0_con[8]; + unsigned int usbphy1_con[8]; + unsigned int reserved14[0x10]; + unsigned int chip_tag; + unsigned int sdmmc_det_cnt; +}; +check_member(rk3036_grf, sdmmc_det_cnt, 0x304); + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 1, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 1, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 3, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + GPIO0A1_PWM2, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 3, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, + GPIO0A0_PWM1, + +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3, + GPIO0B6_GPIO = 0, + GPIO0B6_MMC1_D3, + GPIO0B6_I2S1_SCLK, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3, + GPIO0B5_GPIO = 0, + GPIO0B5_MMC1_D2, + GPIO0B5_I2S1_SDI, + + GPIO0B4_SHIFT = 8, + GPIO0B4_MASK = 3, + GPIO0B4_GPIO = 0, + GPIO0B4_MMC1_D1, + GPIO0B4_I2S1_LRCKTX, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3, + GPIO0B3_GPIO = 0, + GPIO0B3_MMC1_D0, + GPIO0B3_I2S1_LRCKRX, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3, + GPIO0B1_GPIO = 0, + GPIO0B1_MMC1_CLKOUT, + GPIO0B1_I2S1_MCLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_MMC1_CMD, + GPIO0B0_I2S1_SDO, +}; + +/* GRF_GPIO0C_IOMUX */ +enum { + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 1, + GPIO0C4_GPIO = 0, + GPIO0C4_DRIVE_VBUS, + + GPIO0C3_SHIFT = 6, + GPIO0C3_MASK = 1, + GPIO0C3_GPIO = 0, + GPIO0C3_UART0_CTSN, + + GPIO0C2_SHIFT = 4, + GPIO0C2_MASK = 1, + GPIO0C2_GPIO = 0, + GPIO0C2_UART0_RTSN, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 1, + GPIO0C1_GPIO = 0, + GPIO0C1_UART0_SIN, + + + GPIO0C0_SHIFT = 0, + GPIO0C0_MASK = 1, + GPIO0C0_GPIO = 0, + GPIO0C0_UART0_SOUT, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 1, + GPIO0D4_GPIO = 0, + GPIO0D4_SPDIF, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 1, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM3, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 1, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 1, + GPIO1A5_GPIO = 0, + GPIO1A5_I2S_SDI, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 1, + GPIO1A4_GPIO = 0, + GPIO1A4_I2S_SD0, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1, + GPIO1A3_GPIO = 0, + GPIO1A3_I2S_LRCKTX, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 6, + GPIO1A2_GPIO = 0, + GPIO1A2_I2S_LRCKRX, + GPIO1A2_I2S_PWM1_0, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 1, + GPIO1A1_GPIO = 0, + GPIO1A1_I2S_SCLK, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 1, + GPIO1A0_GPIO = 0, + GPIO1A0_I2S_MCLK, + +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 1, + GPIO1B7_GPIO = 0, + GPIO1B7_MMC0_CMD, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 1, + GPIO1B3_GPIO = 0, + GPIO1B3_HDMI_HPD, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 1, + GPIO1B2_GPIO = 0, + GPIO1B2_HDMI_SCL, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 1, + GPIO1B1_GPIO = 0, + GPIO1B1_HDMI_SDA, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 1, + GPIO1B0_GPIO = 0, + GPIO1B0_HDMI_CEC, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3, + GPIO1C5_GPIO = 0, + GPIO1C5_MMC0_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3, + GPIO1C4_GPIO = 0, + GPIO1C4_MMC0_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3, + GPIO1C3_GPIO = 0, + GPIO1C3_MMC0_D1, + GPIO1C3_UART2_SOUT, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3, + GPIO1C2_GPIO = 0, + GPIO1C2_MMC0_D0, + GPIO1C2_UART2_SIN, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 1, + GPIO1C1_GPIO = 0, + GPIO1C1_MMC0_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 1, + GPIO1C0_GPIO = 0, + GPIO1C0_MMC0_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + GPIO1D7_SPI_CSN1, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + GPIO1D6_SPI_CSN0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + GPIO1D5_SPI_TXD, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + GPIO1D4_SPI_RXD, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + GPIO1D3_SFC_SIO3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + GPIO1D2_SFC_SIO2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + GPIO1D1_SFC_SIO1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, + GPIO1D0_SFC_SIO0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 1, + GPIO2A7_GPIO = 0, + GPIO2A7_TESTCLK_OUT, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 1, + GPIO2A6_GPIO = 0, + GPIO2A6_NAND_CS0, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + GPIO2A3_SFC_CLK, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SFC_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SFC_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_EMMC_CLKOUT, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI_CLK, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 1, + GPIO2B7_GPIO = 0, + GPIO2B7_MAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3, + GPIO2B6_GPIO = 0, + GPIO2B6_MAC_CLKOUT, + GPIO2B6_MAC_CLKIN, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 1, + GPIO2B5_GPIO = 0, + GPIO2B5_MAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 1, + GPIO2B4_GPIO = 0, + GPIO2B4_MAC_MDIO, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 1, + GPIO2B2_GPIO = 0, + GPIO2B2_MAC_CRS, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C7_SHIFT = 14, + GPIO2C7_MASK = 3, + GPIO2C7_GPIO = 0, + GPIO2C7_UART1_SOUT, + GPIO2C7_TESTCLK_OUT1, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 1, + GPIO2C6_GPIO = 0, + GPIO2C6_UART1_SIN, + + GPIO2C5_SHIFT = 10, + GPIO2C5_MASK = 1, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL, + + GPIO2C4_SHIFT = 8, + GPIO2C4_MASK = 1, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA, + + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 1, + GPIO2C3_GPIO = 0, + GPIO2C3_MAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 1, + GPIO2C2_GPIO = 0, + GPIO2C2_MAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 1, + GPIO2C1_GPIO = 0, + GPIO2C1_MAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 1, + GPIO2C0_GPIO = 0, + GPIO2C0_MAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 1, + GPIO2D6_GPIO = 0, + GPIO2D6_I2S_SDO1, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 1, + GPIO2D5_GPIO = 0, + GPIO2D5_I2S_SDO2, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 1, + GPIO2D4_GPIO = 0, + GPIO2D4_I2S_SDO3, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 1, + GPIO2D1_GPIO = 0, + GPIO2D1_MAC_MDC, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h new file mode 100644 index 0000000..4ce2ba5 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h @@ -0,0 +1,341 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SDRAM_RK3036_H +#define _ASM_ARCH_SDRAM_RK3036_H + +#include <common.h> + +struct rk3036_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 reserved5[47]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[2]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[2]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[3]; + u32 dfilpcfg0; + u32 reserved13[3]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[46]; + u32 ipvr; + u32 iptr; +}; +check_member(rk3036_ddr_pctl, iptr, 0x03fc); + +struct rk3036_ddr_phy { + u32 ddrphy_reg1; + u32 ddrphy_reg3; + u32 ddrphy_reg2; + u32 reserve[11]; + u32 ddrphy_reg4a; + u32 ddrphy_reg4b; + u32 reserve1[5]; + u32 ddrphy_reg16; + u32 reserve2; + u32 ddrphy_reg18; + u32 ddrphy_reg19; + u32 reserve3; + u32 ddrphy_reg21; + u32 reserve4; + u32 ddrphy_reg22; + u32 reserve5[3]; + u32 ddrphy_reg25; + u32 ddrphy_reg26; + u32 ddrphy_reg27; + u32 ddrphy_reg28; + u32 reserve6[17]; + u32 ddrphy_reg6; + u32 ddrphy_reg7; + u32 reserve7; + u32 ddrphy_reg8; + u32 ddrphy_reg0e4; + u32 reserve8[11]; + u32 ddrphy_reg9; + u32 ddrphy_reg10; + u32 reserve9; + u32 ddrphy_reg11; + u32 ddrphy_reg124; + u32 reserve10[38]; + u32 ddrphy_reg29; + u32 reserve11[40]; + u32 ddrphy_reg264; + u32 reserve12[18]; + u32 ddrphy_reg2a; + u32 reserve13[4]; + u32 ddrphy_reg30; + u32 ddrphy_reg31; + u32 ddrphy_reg32; + u32 ddrphy_reg33; + u32 ddrphy_reg34; + u32 ddrphy_reg35; + u32 ddrphy_reg36; + u32 ddrphy_reg37; + u32 ddrphy_reg38; + u32 ddrphy_reg39; + u32 ddrphy_reg40; + u32 ddrphy_reg41; + u32 ddrphy_reg42; + u32 ddrphy_reg43; + u32 ddrphy_reg44; + u32 ddrphy_reg45; + u32 ddrphy_reg46; + u32 ddrphy_reg47; + u32 ddrphy_reg48; + u32 ddrphy_reg49; + u32 ddrphy_reg50; + u32 ddrphy_reg51; + u32 ddrphy_reg52; + u32 ddrphy_reg53; + u32 reserve14; + u32 ddrphy_reg54; + u32 ddrphy_reg55; + u32 ddrphy_reg56; + u32 ddrphy_reg57; + u32 ddrphy_reg58; + u32 ddrphy_reg59; + u32 ddrphy_reg5a; + u32 ddrphy_reg5b; + u32 ddrphy_reg5c; + u32 ddrphy_reg5d; + u32 ddrphy_reg5e; + u32 reserve15[28]; + u32 ddrphy_reg5f; + u32 reserve16[6]; + u32 ddrphy_reg60; + u32 ddrphy_reg61; + u32 ddrphy_reg62; +}; +check_member(rk3036_ddr_phy, ddrphy_reg62, 0x03e8); + +struct rk3036_pctl_timing { + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; +}; + +struct rk3036_phy_timing { + u32 mr[4]; + u32 bl; + u32 cl_al; +}; + +typedef union { + u32 noc_timing; + struct { + u32 acttoact:6; + u32 rdtomiss:6; + u32 wrtomiss:6; + u32 burstlen:3; + u32 rdtowr:5; + u32 wrtord:5; + u32 bwratio:1; + }; +} rk3036_noc_timing; + +struct rk3036_ddr_timing { + u32 freq; + struct rk3036_pctl_timing pctl_timing; + struct rk3036_phy_timing phy_timing; + rk3036_noc_timing noc_timing; +}; + +struct rk3036_service_sys { + u32 id_coreid; + u32 id_revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; +}; + +struct rk3036_ddr_config { + /* + * 000: lpddr + * 001: ddr + * 010: ddr2 + * 011: ddr3 + * 100: lpddr2-s2 + * 101: lpddr2-s4 + * 110: lpddr3 + */ + u32 ddr_type; + u32 rank; + u32 cs0_row; + u32 cs1_row; + + /* 2: 4bank, 3: 8bank */ + u32 bank; + u32 col; + + /* bw(0: 8bit, 1: 16bit, 2: 32bit) */ + u32 bw; +}; + +/* rk3036 sdram initial */ +void sdram_init(void); + +/* get ddr die config, implement in specific board */ +void get_ddr_config(struct rk3036_ddr_config *config); + +/* get ddr size on board */ +size_t sdram_size(void); +#endif diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h new file mode 100644 index 0000000..1d044bb --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/timer.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_TIMER_H +#define __ASM_ARCH_TIMER_H + +struct rk_timer { + unsigned int timer_load_count0; + unsigned int timer_load_count1; + unsigned int timer_curr_value0; + unsigned int timer_curr_value1; + unsigned int timer_ctrl_reg; + unsigned int timer_int_status; +}; + +void rockchip_timer_init(void); +void rockchip_udelay(unsigned int usec); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/uart.h b/arch/arm/include/asm/arch-rockchip/uart.h new file mode 100644 index 0000000..ea86ce6 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/uart.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_UART_H +#define __ASM_ARCH_UART_H +struct rk_uart { + unsigned int rbr; /* Receive buffer register. */ + unsigned int ier; /* Interrupt enable register. */ + unsigned int fcr; /* FIFO control register. */ + unsigned int lcr; /* Line control register. */ + unsigned int mcr; /* Modem control register. */ + unsigned int lsr; /* Line status register. */ + unsigned int msr; /* Modem status register. */ + unsigned int scr; + unsigned int reserved1[(0x30 - 0x20) / 4]; + unsigned int srbr[(0x70 - 0x30) / 4]; + unsigned int far; + unsigned int tfr; + unsigned int rfw; + unsigned int usr; + unsigned int tfl; + unsigned int rfl; + unsigned int srr; + unsigned int srts; + unsigned int sbcr; + unsigned int sdmam; + unsigned int sfe; + unsigned int srt; + unsigned int stet; + unsigned int htx; + unsigned int dmasa; + unsigned int reserver2[(0xf4 - 0xac) / 4]; + unsigned int cpr; + unsigned int ucv; + unsigned int ctr; +}; + +void rk_uart_init(void *base); +void print_hex(unsigned int n); +void print(char *s); +#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/clk.h b/arch/arm/include/asm/arch-s5pc1xx/clk.h deleted file mode 100644 index 6457ac7..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/clk.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_CLK_H_ -#define __ASM_ARM_ARCH_CLK_H_ - -#define APLL 0 -#define MPLL 1 -#define EPLL 2 -#define HPLL 3 -#define VPLL 4 - -unsigned long get_pll_clk(int pllreg); -unsigned long get_arm_clk(void); -unsigned long get_pwm_clk(void); -unsigned long get_uart_clk(int dev_index); -void set_mmc_clk(int dev_index, unsigned int div); - -#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/clock.h b/arch/arm/include/asm/arch-s5pc1xx/clock.h deleted file mode 100644 index 858496a..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/clock.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_CLOCK_H_ -#define __ASM_ARM_ARCH_CLOCK_H_ - -#ifndef __ASSEMBLY__ -struct s5pc100_clock { - unsigned int apll_lock; - unsigned int mpll_lock; - unsigned int epll_lock; - unsigned int hpll_lock; - unsigned char res1[0xf0]; - unsigned int apll_con; - unsigned int mpll_con; - unsigned int epll_con; - unsigned int hpll_con; - unsigned char res2[0xf0]; - unsigned int src0; - unsigned int src1; - unsigned int src2; - unsigned int src3; - unsigned char res3[0xf0]; - unsigned int div0; - unsigned int div1; - unsigned int div2; - unsigned int div3; - unsigned int div4; - unsigned char res4[0x1ec]; - unsigned int gate_d00; - unsigned int gate_d01; - unsigned int gate_d02; - unsigned char res5[0x54]; - unsigned int gate_sclk0; - unsigned int gate_sclk1; -}; - -struct s5pc110_clock { - unsigned int apll_lock; - unsigned char res1[0x4]; - unsigned int mpll_lock; - unsigned char res2[0x4]; - unsigned int epll_lock; - unsigned char res3[0xc]; - unsigned int vpll_lock; - unsigned char res4[0xdc]; - unsigned int apll_con; - unsigned char res5[0x4]; - unsigned int mpll_con; - unsigned char res6[0x4]; - unsigned int epll_con; - unsigned char res7[0xc]; - unsigned int vpll_con; - unsigned char res8[0xdc]; - unsigned int src0; - unsigned int src1; - unsigned int src2; - unsigned int src3; - unsigned char res9[0xf0]; - unsigned int div0; - unsigned int div1; - unsigned int div2; - unsigned int div3; - unsigned int div4; - unsigned char res10[0x1ec]; - unsigned int gate_d00; - unsigned int gate_d01; - unsigned int gate_d02; - unsigned char res11[0x54]; - unsigned int gate_sclk0; - unsigned int gate_sclk1; -}; -#endif - -#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h deleted file mode 100644 index 5ae5c87..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _S5PC1XX_CPU_H -#define _S5PC1XX_CPU_H - -#define S5P_CPU_NAME "S5P" -#define S5PC1XX_ADDR_BASE 0xE0000000 - -/* S5PC100 */ -#define S5PC100_PRO_ID 0xE0000000 -#define S5PC100_CLOCK_BASE 0xE0100000 -#define S5PC100_GPIO_BASE 0xE0300000 -#define S5PC100_VIC0_BASE 0xE4000000 -#define S5PC100_VIC1_BASE 0xE4100000 -#define S5PC100_VIC2_BASE 0xE4200000 -#define S5PC100_DMC_BASE 0xE6000000 -#define S5PC100_SROMC_BASE 0xE7000000 -#define S5PC100_ONENAND_BASE 0xE7100000 -#define S5PC100_PWMTIMER_BASE 0xEA000000 -#define S5PC100_WATCHDOG_BASE 0xEA200000 -#define S5PC100_UART_BASE 0xEC000000 -#define S5PC100_MMC_BASE 0xED800000 - -/* S5PC110 */ -#define S5PC110_PRO_ID 0xE0000000 -#define S5PC110_CLOCK_BASE 0xE0100000 -#define S5PC110_GPIO_BASE 0xE0200000 -#define S5PC110_PWMTIMER_BASE 0xE2500000 -#define S5PC110_WATCHDOG_BASE 0xE2700000 -#define S5PC110_UART_BASE 0xE2900000 -#define S5PC110_SROMC_BASE 0xE8000000 -#define S5PC110_MMC_BASE 0xEB000000 -#define S5PC110_DMC0_BASE 0xF0000000 -#define S5PC110_DMC1_BASE 0xF1400000 -#define S5PC110_VIC0_BASE 0xF2000000 -#define S5PC110_VIC1_BASE 0xF2100000 -#define S5PC110_VIC2_BASE 0xF2200000 -#define S5PC110_VIC3_BASE 0xF2300000 -#define S5PC110_OTG_BASE 0xEC000000 -#define S5PC110_PHY_BASE 0xEC100000 -#define S5PC110_USB_PHY_CONTROL 0xE010E80C - - -#ifndef __ASSEMBLY__ -#include <asm/io.h> -/* CPU detection macros */ -extern unsigned int s5p_cpu_id; -extern unsigned int s5p_cpu_rev; - -static inline int s5p_get_cpu_rev(void) -{ - return s5p_cpu_rev; -} - -static inline void s5p_set_cpu_id(void) -{ - s5p_cpu_id = readl(S5PC100_PRO_ID); - s5p_cpu_rev = s5p_cpu_id & 0x000000FF; - s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); -} - -static inline char *s5p_get_cpu_name(void) -{ - return S5P_CPU_NAME; -} - -#define IS_SAMSUNG_TYPE(type, id) \ -static inline int cpu_is_##type(void) \ -{ \ - return s5p_cpu_id == id ? 1 : 0; \ -} - -IS_SAMSUNG_TYPE(s5pc100, 0xc100) -IS_SAMSUNG_TYPE(s5pc110, 0xc110) - -#define SAMSUNG_BASE(device, base) \ -static inline unsigned int samsung_get_base_##device(void) \ -{ \ - if (cpu_is_s5pc100()) \ - return S5PC100_##base; \ - else if (cpu_is_s5pc110()) \ - return S5PC110_##base; \ - else \ - return 0; \ -} - -SAMSUNG_BASE(clock, CLOCK_BASE) -SAMSUNG_BASE(gpio, GPIO_BASE) -SAMSUNG_BASE(pro_id, PRO_ID) -SAMSUNG_BASE(mmc, MMC_BASE) -SAMSUNG_BASE(sromc, SROMC_BASE) -SAMSUNG_BASE(timer, PWMTIMER_BASE) -SAMSUNG_BASE(uart, UART_BASE) -SAMSUNG_BASE(watchdog, WATCHDOG_BASE) -#endif - -#endif /* _S5PC1XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h deleted file mode 100644 index 2de205e..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ /dev/null @@ -1,843 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#ifndef __ASSEMBLY__ -struct s5p_gpio_bank { - unsigned int con; - unsigned int dat; - unsigned int pull; - unsigned int drv; - unsigned int pdn_con; - unsigned int pdn_pull; - unsigned char res1[8]; -}; - -/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ -enum s5pc100_gpio_pin { - S5PC100_GPIO_A00, - S5PC100_GPIO_A01, - S5PC100_GPIO_A02, - S5PC100_GPIO_A03, - S5PC100_GPIO_A04, - S5PC100_GPIO_A05, - S5PC100_GPIO_A06, - S5PC100_GPIO_A07, - S5PC100_GPIO_A10, - S5PC100_GPIO_A11, - S5PC100_GPIO_A12, - S5PC100_GPIO_A13, - S5PC100_GPIO_A14, - S5PC100_GPIO_A15, - S5PC100_GPIO_A16, - S5PC100_GPIO_A17, - S5PC100_GPIO_B0, - S5PC100_GPIO_B1, - S5PC100_GPIO_B2, - S5PC100_GPIO_B3, - S5PC100_GPIO_B4, - S5PC100_GPIO_B5, - S5PC100_GPIO_B6, - S5PC100_GPIO_B7, - S5PC100_GPIO_C0, - S5PC100_GPIO_C1, - S5PC100_GPIO_C2, - S5PC100_GPIO_C3, - S5PC100_GPIO_C4, - S5PC100_GPIO_C5, - S5PC100_GPIO_C6, - S5PC100_GPIO_C7, - S5PC100_GPIO_D0, - S5PC100_GPIO_D1, - S5PC100_GPIO_D2, - S5PC100_GPIO_D3, - S5PC100_GPIO_D4, - S5PC100_GPIO_D5, - S5PC100_GPIO_D6, - S5PC100_GPIO_D7, - S5PC100_GPIO_E00, - S5PC100_GPIO_E01, - S5PC100_GPIO_E02, - S5PC100_GPIO_E03, - S5PC100_GPIO_E04, - S5PC100_GPIO_E05, - S5PC100_GPIO_E06, - S5PC100_GPIO_E07, - S5PC100_GPIO_E10, - S5PC100_GPIO_E11, - S5PC100_GPIO_E12, - S5PC100_GPIO_E13, - S5PC100_GPIO_E14, - S5PC100_GPIO_E15, - S5PC100_GPIO_E16, - S5PC100_GPIO_E17, - S5PC100_GPIO_F00, - S5PC100_GPIO_F01, - S5PC100_GPIO_F02, - S5PC100_GPIO_F03, - S5PC100_GPIO_F04, - S5PC100_GPIO_F05, - S5PC100_GPIO_F06, - S5PC100_GPIO_F07, - S5PC100_GPIO_F10, - S5PC100_GPIO_F11, - S5PC100_GPIO_F12, - S5PC100_GPIO_F13, - S5PC100_GPIO_F14, - S5PC100_GPIO_F15, - S5PC100_GPIO_F16, - S5PC100_GPIO_F17, - S5PC100_GPIO_F20, - S5PC100_GPIO_F21, - S5PC100_GPIO_F22, - S5PC100_GPIO_F23, - S5PC100_GPIO_F24, - S5PC100_GPIO_F25, - S5PC100_GPIO_F26, - S5PC100_GPIO_F27, - S5PC100_GPIO_F30, - S5PC100_GPIO_F31, - S5PC100_GPIO_F32, - S5PC100_GPIO_F33, - S5PC100_GPIO_F34, - S5PC100_GPIO_F35, - S5PC100_GPIO_F36, - S5PC100_GPIO_F37, - S5PC100_GPIO_G00, - S5PC100_GPIO_G01, - S5PC100_GPIO_G02, - S5PC100_GPIO_G03, - S5PC100_GPIO_G04, - S5PC100_GPIO_G05, - S5PC100_GPIO_G06, - S5PC100_GPIO_G07, - S5PC100_GPIO_G10, - S5PC100_GPIO_G11, - S5PC100_GPIO_G12, - S5PC100_GPIO_G13, - S5PC100_GPIO_G14, - S5PC100_GPIO_G15, - S5PC100_GPIO_G16, - S5PC100_GPIO_G17, - S5PC100_GPIO_G20, - S5PC100_GPIO_G21, - S5PC100_GPIO_G22, - S5PC100_GPIO_G23, - S5PC100_GPIO_G24, - S5PC100_GPIO_G25, - S5PC100_GPIO_G26, - S5PC100_GPIO_G27, - S5PC100_GPIO_G30, - S5PC100_GPIO_G31, - S5PC100_GPIO_G32, - S5PC100_GPIO_G33, - S5PC100_GPIO_G34, - S5PC100_GPIO_G35, - S5PC100_GPIO_G36, - S5PC100_GPIO_G37, - S5PC100_GPIO_I0, - S5PC100_GPIO_I1, - S5PC100_GPIO_I2, - S5PC100_GPIO_I3, - S5PC100_GPIO_I4, - S5PC100_GPIO_I5, - S5PC100_GPIO_I6, - S5PC100_GPIO_I7, - S5PC100_GPIO_J00, - S5PC100_GPIO_J01, - S5PC100_GPIO_J02, - S5PC100_GPIO_J03, - S5PC100_GPIO_J04, - S5PC100_GPIO_J05, - S5PC100_GPIO_J06, - S5PC100_GPIO_J07, - S5PC100_GPIO_J10, - S5PC100_GPIO_J11, - S5PC100_GPIO_J12, - S5PC100_GPIO_J13, - S5PC100_GPIO_J14, - S5PC100_GPIO_J15, - S5PC100_GPIO_J16, - S5PC100_GPIO_J17, - S5PC100_GPIO_J20, - S5PC100_GPIO_J21, - S5PC100_GPIO_J22, - S5PC100_GPIO_J23, - S5PC100_GPIO_J24, - S5PC100_GPIO_J25, - S5PC100_GPIO_J26, - S5PC100_GPIO_J27, - S5PC100_GPIO_J30, - S5PC100_GPIO_J31, - S5PC100_GPIO_J32, - S5PC100_GPIO_J33, - S5PC100_GPIO_J34, - S5PC100_GPIO_J35, - S5PC100_GPIO_J36, - S5PC100_GPIO_J37, - S5PC100_GPIO_J40, - S5PC100_GPIO_J41, - S5PC100_GPIO_J42, - S5PC100_GPIO_J43, - S5PC100_GPIO_J44, - S5PC100_GPIO_J45, - S5PC100_GPIO_J46, - S5PC100_GPIO_J47, - S5PC100_GPIO_K00, - S5PC100_GPIO_K01, - S5PC100_GPIO_K02, - S5PC100_GPIO_K03, - S5PC100_GPIO_K04, - S5PC100_GPIO_K05, - S5PC100_GPIO_K06, - S5PC100_GPIO_K07, - S5PC100_GPIO_K10, - S5PC100_GPIO_K11, - S5PC100_GPIO_K12, - S5PC100_GPIO_K13, - S5PC100_GPIO_K14, - S5PC100_GPIO_K15, - S5PC100_GPIO_K16, - S5PC100_GPIO_K17, - S5PC100_GPIO_K20, - S5PC100_GPIO_K21, - S5PC100_GPIO_K22, - S5PC100_GPIO_K23, - S5PC100_GPIO_K24, - S5PC100_GPIO_K25, - S5PC100_GPIO_K26, - S5PC100_GPIO_K27, - S5PC100_GPIO_K30, - S5PC100_GPIO_K31, - S5PC100_GPIO_K32, - S5PC100_GPIO_K33, - S5PC100_GPIO_K34, - S5PC100_GPIO_K35, - S5PC100_GPIO_K36, - S5PC100_GPIO_K37, - S5PC100_GPIO_L00, - S5PC100_GPIO_L01, - S5PC100_GPIO_L02, - S5PC100_GPIO_L03, - S5PC100_GPIO_L04, - S5PC100_GPIO_L05, - S5PC100_GPIO_L06, - S5PC100_GPIO_L07, - S5PC100_GPIO_L10, - S5PC100_GPIO_L11, - S5PC100_GPIO_L12, - S5PC100_GPIO_L13, - S5PC100_GPIO_L14, - S5PC100_GPIO_L15, - S5PC100_GPIO_L16, - S5PC100_GPIO_L17, - S5PC100_GPIO_L20, - S5PC100_GPIO_L21, - S5PC100_GPIO_L22, - S5PC100_GPIO_L23, - S5PC100_GPIO_L24, - S5PC100_GPIO_L25, - S5PC100_GPIO_L26, - S5PC100_GPIO_L27, - S5PC100_GPIO_L30, - S5PC100_GPIO_L31, - S5PC100_GPIO_L32, - S5PC100_GPIO_L33, - S5PC100_GPIO_L34, - S5PC100_GPIO_L35, - S5PC100_GPIO_L36, - S5PC100_GPIO_L37, - S5PC100_GPIO_L40, - S5PC100_GPIO_L41, - S5PC100_GPIO_L42, - S5PC100_GPIO_L43, - S5PC100_GPIO_L44, - S5PC100_GPIO_L45, - S5PC100_GPIO_L46, - S5PC100_GPIO_L47, - S5PC100_GPIO_H00, - S5PC100_GPIO_H01, - S5PC100_GPIO_H02, - S5PC100_GPIO_H03, - S5PC100_GPIO_H04, - S5PC100_GPIO_H05, - S5PC100_GPIO_H06, - S5PC100_GPIO_H07, - S5PC100_GPIO_H10, - S5PC100_GPIO_H11, - S5PC100_GPIO_H12, - S5PC100_GPIO_H13, - S5PC100_GPIO_H14, - S5PC100_GPIO_H15, - S5PC100_GPIO_H16, - S5PC100_GPIO_H17, - S5PC100_GPIO_H20, - S5PC100_GPIO_H21, - S5PC100_GPIO_H22, - S5PC100_GPIO_H23, - S5PC100_GPIO_H24, - S5PC100_GPIO_H25, - S5PC100_GPIO_H26, - S5PC100_GPIO_H27, - S5PC100_GPIO_H30, - S5PC100_GPIO_H31, - S5PC100_GPIO_H32, - S5PC100_GPIO_H33, - S5PC100_GPIO_H34, - S5PC100_GPIO_H35, - S5PC100_GPIO_H36, - S5PC100_GPIO_H37, - - S5PC100_GPIO_MAX_PORT -}; - -enum s5pc110_gpio_pin { - S5PC110_GPIO_A00, - S5PC110_GPIO_A01, - S5PC110_GPIO_A02, - S5PC110_GPIO_A03, - S5PC110_GPIO_A04, - S5PC110_GPIO_A05, - S5PC110_GPIO_A06, - S5PC110_GPIO_A07, - S5PC110_GPIO_A10, - S5PC110_GPIO_A11, - S5PC110_GPIO_A12, - S5PC110_GPIO_A13, - S5PC110_GPIO_A14, - S5PC110_GPIO_A15, - S5PC110_GPIO_A16, - S5PC110_GPIO_A17, - S5PC110_GPIO_B0, - S5PC110_GPIO_B1, - S5PC110_GPIO_B2, - S5PC110_GPIO_B3, - S5PC110_GPIO_B4, - S5PC110_GPIO_B5, - S5PC110_GPIO_B6, - S5PC110_GPIO_B7, - S5PC110_GPIO_C00, - S5PC110_GPIO_C01, - S5PC110_GPIO_C02, - S5PC110_GPIO_C03, - S5PC110_GPIO_C04, - S5PC110_GPIO_C05, - S5PC110_GPIO_C06, - S5PC110_GPIO_C07, - S5PC110_GPIO_C10, - S5PC110_GPIO_C11, - S5PC110_GPIO_C12, - S5PC110_GPIO_C13, - S5PC110_GPIO_C14, - S5PC110_GPIO_C15, - S5PC110_GPIO_C16, - S5PC110_GPIO_C17, - S5PC110_GPIO_D00, - S5PC110_GPIO_D01, - S5PC110_GPIO_D02, - S5PC110_GPIO_D03, - S5PC110_GPIO_D04, - S5PC110_GPIO_D05, - S5PC110_GPIO_D06, - S5PC110_GPIO_D07, - S5PC110_GPIO_D10, - S5PC110_GPIO_D11, - S5PC110_GPIO_D12, - S5PC110_GPIO_D13, - S5PC110_GPIO_D14, - S5PC110_GPIO_D15, - S5PC110_GPIO_D16, - S5PC110_GPIO_D17, - S5PC110_GPIO_E00, - S5PC110_GPIO_E01, - S5PC110_GPIO_E02, - S5PC110_GPIO_E03, - S5PC110_GPIO_E04, - S5PC110_GPIO_E05, - S5PC110_GPIO_E06, - S5PC110_GPIO_E07, - S5PC110_GPIO_E10, - S5PC110_GPIO_E11, - S5PC110_GPIO_E12, - S5PC110_GPIO_E13, - S5PC110_GPIO_E14, - S5PC110_GPIO_E15, - S5PC110_GPIO_E16, - S5PC110_GPIO_E17, - S5PC110_GPIO_F00, - S5PC110_GPIO_F01, - S5PC110_GPIO_F02, - S5PC110_GPIO_F03, - S5PC110_GPIO_F04, - S5PC110_GPIO_F05, - S5PC110_GPIO_F06, - S5PC110_GPIO_F07, - S5PC110_GPIO_F10, - S5PC110_GPIO_F11, - S5PC110_GPIO_F12, - S5PC110_GPIO_F13, - S5PC110_GPIO_F14, - S5PC110_GPIO_F15, - S5PC110_GPIO_F16, - S5PC110_GPIO_F17, - S5PC110_GPIO_F20, - S5PC110_GPIO_F21, - S5PC110_GPIO_F22, - S5PC110_GPIO_F23, - S5PC110_GPIO_F24, - S5PC110_GPIO_F25, - S5PC110_GPIO_F26, - S5PC110_GPIO_F27, - S5PC110_GPIO_F30, - S5PC110_GPIO_F31, - S5PC110_GPIO_F32, - S5PC110_GPIO_F33, - S5PC110_GPIO_F34, - S5PC110_GPIO_F35, - S5PC110_GPIO_F36, - S5PC110_GPIO_F37, - S5PC110_GPIO_G00, - S5PC110_GPIO_G01, - S5PC110_GPIO_G02, - S5PC110_GPIO_G03, - S5PC110_GPIO_G04, - S5PC110_GPIO_G05, - S5PC110_GPIO_G06, - S5PC110_GPIO_G07, - S5PC110_GPIO_G10, - S5PC110_GPIO_G11, - S5PC110_GPIO_G12, - S5PC110_GPIO_G13, - S5PC110_GPIO_G14, - S5PC110_GPIO_G15, - S5PC110_GPIO_G16, - S5PC110_GPIO_G17, - S5PC110_GPIO_G20, - S5PC110_GPIO_G21, - S5PC110_GPIO_G22, - S5PC110_GPIO_G23, - S5PC110_GPIO_G24, - S5PC110_GPIO_G25, - S5PC110_GPIO_G26, - S5PC110_GPIO_G27, - S5PC110_GPIO_G30, - S5PC110_GPIO_G31, - S5PC110_GPIO_G32, - S5PC110_GPIO_G33, - S5PC110_GPIO_G34, - S5PC110_GPIO_G35, - S5PC110_GPIO_G36, - S5PC110_GPIO_G37, - S5PC110_GPIO_I0, - S5PC110_GPIO_I1, - S5PC110_GPIO_I2, - S5PC110_GPIO_I3, - S5PC110_GPIO_I4, - S5PC110_GPIO_I5, - S5PC110_GPIO_I6, - S5PC110_GPIO_I7, - S5PC110_GPIO_J00, - S5PC110_GPIO_J01, - S5PC110_GPIO_J02, - S5PC110_GPIO_J03, - S5PC110_GPIO_J04, - S5PC110_GPIO_J05, - S5PC110_GPIO_J06, - S5PC110_GPIO_J07, - S5PC110_GPIO_J10, - S5PC110_GPIO_J11, - S5PC110_GPIO_J12, - S5PC110_GPIO_J13, - S5PC110_GPIO_J14, - S5PC110_GPIO_J15, - S5PC110_GPIO_J16, - S5PC110_GPIO_J17, - S5PC110_GPIO_J20, - S5PC110_GPIO_J21, - S5PC110_GPIO_J22, - S5PC110_GPIO_J23, - S5PC110_GPIO_J24, - S5PC110_GPIO_J25, - S5PC110_GPIO_J26, - S5PC110_GPIO_J27, - S5PC110_GPIO_J30, - S5PC110_GPIO_J31, - S5PC110_GPIO_J32, - S5PC110_GPIO_J33, - S5PC110_GPIO_J34, - S5PC110_GPIO_J35, - S5PC110_GPIO_J36, - S5PC110_GPIO_J37, - S5PC110_GPIO_J40, - S5PC110_GPIO_J41, - S5PC110_GPIO_J42, - S5PC110_GPIO_J43, - S5PC110_GPIO_J44, - S5PC110_GPIO_J45, - S5PC110_GPIO_J46, - S5PC110_GPIO_J47, - S5PC110_GPIO_MP010, - S5PC110_GPIO_MP011, - S5PC110_GPIO_MP012, - S5PC110_GPIO_MP013, - S5PC110_GPIO_MP014, - S5PC110_GPIO_MP015, - S5PC110_GPIO_MP016, - S5PC110_GPIO_MP017, - S5PC110_GPIO_MP020, - S5PC110_GPIO_MP021, - S5PC110_GPIO_MP022, - S5PC110_GPIO_MP023, - S5PC110_GPIO_MP024, - S5PC110_GPIO_MP025, - S5PC110_GPIO_MP026, - S5PC110_GPIO_MP027, - S5PC110_GPIO_MP030, - S5PC110_GPIO_MP031, - S5PC110_GPIO_MP032, - S5PC110_GPIO_MP033, - S5PC110_GPIO_MP034, - S5PC110_GPIO_MP035, - S5PC110_GPIO_MP036, - S5PC110_GPIO_MP037, - S5PC110_GPIO_MP040, - S5PC110_GPIO_MP041, - S5PC110_GPIO_MP042, - S5PC110_GPIO_MP043, - S5PC110_GPIO_MP044, - S5PC110_GPIO_MP045, - S5PC110_GPIO_MP046, - S5PC110_GPIO_MP047, - S5PC110_GPIO_MP050, - S5PC110_GPIO_MP051, - S5PC110_GPIO_MP052, - S5PC110_GPIO_MP053, - S5PC110_GPIO_MP054, - S5PC110_GPIO_MP055, - S5PC110_GPIO_MP056, - S5PC110_GPIO_MP057, - S5PC110_GPIO_MP060, - S5PC110_GPIO_MP061, - S5PC110_GPIO_MP062, - S5PC110_GPIO_MP063, - S5PC110_GPIO_MP064, - S5PC110_GPIO_MP065, - S5PC110_GPIO_MP066, - S5PC110_GPIO_MP067, - S5PC110_GPIO_MP070, - S5PC110_GPIO_MP071, - S5PC110_GPIO_MP072, - S5PC110_GPIO_MP073, - S5PC110_GPIO_MP074, - S5PC110_GPIO_MP075, - S5PC110_GPIO_MP076, - S5PC110_GPIO_MP077, - S5PC110_GPIO_MP100, - S5PC110_GPIO_MP101, - S5PC110_GPIO_MP102, - S5PC110_GPIO_MP103, - S5PC110_GPIO_MP104, - S5PC110_GPIO_MP105, - S5PC110_GPIO_MP106, - S5PC110_GPIO_MP107, - S5PC110_GPIO_MP110, - S5PC110_GPIO_MP111, - S5PC110_GPIO_MP112, - S5PC110_GPIO_MP113, - S5PC110_GPIO_MP114, - S5PC110_GPIO_MP115, - S5PC110_GPIO_MP116, - S5PC110_GPIO_MP117, - S5PC110_GPIO_MP120, - S5PC110_GPIO_MP121, - S5PC110_GPIO_MP122, - S5PC110_GPIO_MP123, - S5PC110_GPIO_MP124, - S5PC110_GPIO_MP125, - S5PC110_GPIO_MP126, - S5PC110_GPIO_MP127, - S5PC110_GPIO_MP130, - S5PC110_GPIO_MP131, - S5PC110_GPIO_MP132, - S5PC110_GPIO_MP133, - S5PC110_GPIO_MP134, - S5PC110_GPIO_MP135, - S5PC110_GPIO_MP136, - S5PC110_GPIO_MP137, - S5PC110_GPIO_MP140, - S5PC110_GPIO_MP141, - S5PC110_GPIO_MP142, - S5PC110_GPIO_MP143, - S5PC110_GPIO_MP144, - S5PC110_GPIO_MP145, - S5PC110_GPIO_MP146, - S5PC110_GPIO_MP147, - S5PC110_GPIO_MP150, - S5PC110_GPIO_MP151, - S5PC110_GPIO_MP152, - S5PC110_GPIO_MP153, - S5PC110_GPIO_MP154, - S5PC110_GPIO_MP155, - S5PC110_GPIO_MP156, - S5PC110_GPIO_MP157, - S5PC110_GPIO_MP160, - S5PC110_GPIO_MP161, - S5PC110_GPIO_MP162, - S5PC110_GPIO_MP163, - S5PC110_GPIO_MP164, - S5PC110_GPIO_MP165, - S5PC110_GPIO_MP166, - S5PC110_GPIO_MP167, - S5PC110_GPIO_MP170, - S5PC110_GPIO_MP171, - S5PC110_GPIO_MP172, - S5PC110_GPIO_MP173, - S5PC110_GPIO_MP174, - S5PC110_GPIO_MP175, - S5PC110_GPIO_MP176, - S5PC110_GPIO_MP177, - S5PC110_GPIO_MP180, - S5PC110_GPIO_MP181, - S5PC110_GPIO_MP182, - S5PC110_GPIO_MP183, - S5PC110_GPIO_MP184, - S5PC110_GPIO_MP185, - S5PC110_GPIO_MP186, - S5PC110_GPIO_MP187, - S5PC110_GPIO_MP200, - S5PC110_GPIO_MP201, - S5PC110_GPIO_MP202, - S5PC110_GPIO_MP203, - S5PC110_GPIO_MP204, - S5PC110_GPIO_MP205, - S5PC110_GPIO_MP206, - S5PC110_GPIO_MP207, - S5PC110_GPIO_MP210, - S5PC110_GPIO_MP211, - S5PC110_GPIO_MP212, - S5PC110_GPIO_MP213, - S5PC110_GPIO_MP214, - S5PC110_GPIO_MP215, - S5PC110_GPIO_MP216, - S5PC110_GPIO_MP217, - S5PC110_GPIO_MP220, - S5PC110_GPIO_MP221, - S5PC110_GPIO_MP222, - S5PC110_GPIO_MP223, - S5PC110_GPIO_MP224, - S5PC110_GPIO_MP225, - S5PC110_GPIO_MP226, - S5PC110_GPIO_MP227, - S5PC110_GPIO_MP230, - S5PC110_GPIO_MP231, - S5PC110_GPIO_MP232, - S5PC110_GPIO_MP233, - S5PC110_GPIO_MP234, - S5PC110_GPIO_MP235, - S5PC110_GPIO_MP236, - S5PC110_GPIO_MP237, - S5PC110_GPIO_MP240, - S5PC110_GPIO_MP241, - S5PC110_GPIO_MP242, - S5PC110_GPIO_MP243, - S5PC110_GPIO_MP244, - S5PC110_GPIO_MP245, - S5PC110_GPIO_MP246, - S5PC110_GPIO_MP247, - S5PC110_GPIO_MP250, - S5PC110_GPIO_MP251, - S5PC110_GPIO_MP252, - S5PC110_GPIO_MP253, - S5PC110_GPIO_MP254, - S5PC110_GPIO_MP255, - S5PC110_GPIO_MP256, - S5PC110_GPIO_MP257, - S5PC110_GPIO_MP260, - S5PC110_GPIO_MP261, - S5PC110_GPIO_MP262, - S5PC110_GPIO_MP263, - S5PC110_GPIO_MP264, - S5PC110_GPIO_MP265, - S5PC110_GPIO_MP266, - S5PC110_GPIO_MP267, - S5PC110_GPIO_MP270, - S5PC110_GPIO_MP271, - S5PC110_GPIO_MP272, - S5PC110_GPIO_MP273, - S5PC110_GPIO_MP274, - S5PC110_GPIO_MP275, - S5PC110_GPIO_MP276, - S5PC110_GPIO_MP277, - S5PC110_GPIO_MP280, - S5PC110_GPIO_MP281, - S5PC110_GPIO_MP282, - S5PC110_GPIO_MP283, - S5PC110_GPIO_MP284, - S5PC110_GPIO_MP285, - S5PC110_GPIO_MP286, - S5PC110_GPIO_MP287, - S5PC110_GPIO_H00, - S5PC110_GPIO_H01, - S5PC110_GPIO_H02, - S5PC110_GPIO_H03, - S5PC110_GPIO_H04, - S5PC110_GPIO_H05, - S5PC110_GPIO_H06, - S5PC110_GPIO_H07, - S5PC110_GPIO_H10, - S5PC110_GPIO_H11, - S5PC110_GPIO_H12, - S5PC110_GPIO_H13, - S5PC110_GPIO_H14, - S5PC110_GPIO_H15, - S5PC110_GPIO_H16, - S5PC110_GPIO_H17, - S5PC110_GPIO_H20, - S5PC110_GPIO_H21, - S5PC110_GPIO_H22, - S5PC110_GPIO_H23, - S5PC110_GPIO_H24, - S5PC110_GPIO_H25, - S5PC110_GPIO_H26, - S5PC110_GPIO_H27, - S5PC110_GPIO_H30, - S5PC110_GPIO_H31, - S5PC110_GPIO_H32, - S5PC110_GPIO_H33, - S5PC110_GPIO_H34, - S5PC110_GPIO_H35, - S5PC110_GPIO_H36, - S5PC110_GPIO_H37, - - S5PC110_GPIO_MAX_PORT -}; - -struct gpio_info { - unsigned int reg_addr; /* Address of register for this part */ - unsigned int max_gpio; /* Maximum GPIO in this part */ -}; - -#define S5PC100_GPIO_NUM_PARTS 1 -static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = { - { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT }, -}; - -#define S5PC110_GPIO_NUM_PARTS 1 -static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = { - { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT }, -}; - -static inline struct gpio_info *get_gpio_data(void) -{ - if (cpu_is_s5pc100()) - return s5pc100_gpio_data; - else if (cpu_is_s5pc110()) - return s5pc110_gpio_data; - - return NULL; -} - -static inline unsigned int get_bank_num(void) -{ - if (cpu_is_s5pc100()) - return S5PC100_GPIO_NUM_PARTS; - else if (cpu_is_s5pc110()) - return S5PC110_GPIO_NUM_PARTS; - - return 0; -} - -/* - * This structure helps mapping symbolic GPIO names into indices from - * exynos5_gpio_pin/exynos5420_gpio_pin enums. - * - * By convention, symbolic GPIO name is defined as follows: - * - * g[p]<bank><set><bit>, where - * p is optional - * <bank> - a single character bank name, as defined by the SOC - * <set> - a single digit set number - * <bit> - bit number within the set (in 0..7 range). - * - * <set><bit> essentially form an octal number of the GPIO pin within the bank - * space. On the 5420 architecture some banks' sets do not start not from zero - * ('d' starts from 1 and 'j' starts from 4). To compensate for that and - * maintain flat number space withoout holes, those banks use offsets to be - * deducted from the pin number. - */ -struct gpio_name_num_table { - char bank; /* bank name symbol */ - u8 bank_size; /* total number of pins in the bank */ - char bank_offset; /* offset of the first bank's pin */ - unsigned int base; /* index of the first bank's pin in the enum */ -}; - -#define GPIO_PER_BANK 8 -#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base } -static const struct gpio_name_num_table s5pc100_gpio_table[] = { - GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0), - GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0), - GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0), - GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0), - GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0), - GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0), - GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0), - GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0), - GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0), - GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0), - GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0), - GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0), - { 0 } -}; - -static const struct gpio_name_num_table s5pc110_gpio_table[] = { - GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0), - GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0), - GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0), - GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0), - GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0), - GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0), - GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0), - GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0), - GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0), - GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0), - { 0 } -}; - -/* functions */ -void gpio_cfg_pin(int gpio, int cfg); -void gpio_set_pull(int gpio, int mode); -void gpio_set_drv(int gpio, int mode); -void gpio_set_rate(int gpio, int mode); -int s5p_gpio_get_pin(unsigned gpio); - -/* GPIO pins per bank */ -#define GPIO_PER_BANK 8 -#endif - -/* Pin configurations */ -#define S5P_GPIO_INPUT 0x0 -#define S5P_GPIO_OUTPUT 0x1 -#define S5P_GPIO_IRQ 0xf -#define S5P_GPIO_FUNC(x) (x) - -/* Pull mode */ -#define S5P_GPIO_PULL_NONE 0x0 -#define S5P_GPIO_PULL_DOWN 0x1 -#define S5P_GPIO_PULL_UP 0x2 - -/* Drive Strength level */ -#define S5P_GPIO_DRV_1X 0x0 -#define S5P_GPIO_DRV_3X 0x1 -#define S5P_GPIO_DRV_2X 0x2 -#define S5P_GPIO_DRV_4X 0x3 -#define S5P_GPIO_DRV_FAST 0x0 -#define S5P_GPIO_DRV_SLOW 0x1 - -#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h deleted file mode 100644 index dd473c8..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MMC_H_ -#define __ASM_ARCH_MMC_H_ - -#define S5P_MMC_DEV_OFFSET 0x100000 - -#define SDHCI_CONTROL2 0x80 -#define SDHCI_CONTROL3 0x84 -#define SDHCI_CONTROL4 0x8C - -#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) -#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) -#define SDHCI_CTRL2_CDINVRXD3 (1 << 29) -#define SDHCI_CTRL2_SLCARDOUT (1 << 28) - -#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) -#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) -#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) - -#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) -#define SDHCI_CTRL2_LVLDAT_SHIFT (16) -#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) - -#define SDHCI_CTRL2_ENFBCLKTX (1 << 15) -#define SDHCI_CTRL2_ENFBCLKRX (1 << 14) -#define SDHCI_CTRL2_SDCDSEL (1 << 13) -#define SDHCI_CTRL2_SDSIGPC (1 << 12) -#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) - -#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9) -#define SDHCI_CTRL2_DFCNT_SHIFT (9) - -#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) -#define SDHCI_CTRL2_RWAITMODE (1 << 7) -#define SDHCI_CTRL2_DISBUFRD (1 << 6) -#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4) -#define SDHCI_CTRL2_SELBASECLK_SHIFT (4) -#define SDHCI_CTRL2_PWRSYNC (1 << 3) -#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) -#define SDHCI_CTRL2_HWINITFIN (1 << 0) - -#define SDHCI_CTRL3_FCSEL3 (1 << 31) -#define SDHCI_CTRL3_FCSEL2 (1 << 23) -#define SDHCI_CTRL3_FCSEL1 (1 << 15) -#define SDHCI_CTRL3_FCSEL0 (1 << 7) - -#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) -#define SDHCI_CTRL4_DRIVE_SHIFT (16) - -int s5p_sdhci_init(u32 regbase, int index, int bus_width); - -static inline int s5p_mmc_init(int index, int bus_width) -{ - unsigned int base = samsung_get_base_mmc() + - (S5P_MMC_DEV_OFFSET * index); - - return s5p_sdhci_init(base, index, bus_width); -} -#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/periph.h b/arch/arm/include/asm/arch-s5pc1xx/periph.h deleted file mode 100644 index 5c1c3d4..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/periph.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * Rajeshwari Shinde <rajeshwari.s@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_PERIPH_H -#define __ASM_ARM_ARCH_PERIPH_H - -/* - * Peripherals required for pinmux configuration. List will - * grow with support for more devices getting added. - * Numbering based on interrupt table. - * - */ -enum periph_id { - PERIPH_ID_UART0 = 51, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - PERIPH_ID_UART3, - PERIPH_ID_I2C0 = 56, - PERIPH_ID_I2C1, - PERIPH_ID_I2C2, - PERIPH_ID_I2C3, - PERIPH_ID_I2C4, - PERIPH_ID_I2C5, - PERIPH_ID_I2C6, - PERIPH_ID_I2C7, - PERIPH_ID_SPI0 = 68, - PERIPH_ID_SPI1, - PERIPH_ID_SPI2, - PERIPH_ID_SDMMC0 = 75, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC2, - PERIPH_ID_SDMMC3, - PERIPH_ID_I2C8 = 87, - PERIPH_ID_I2C9, - PERIPH_ID_I2S0 = 98, - PERIPH_ID_I2S1 = 99, - - /* Since following peripherals do - * not have shared peripheral interrupts (SPIs) - * they are numbered arbitiraly after the maximum - * SPIs Exynos has (128) - */ - PERIPH_ID_SROMC = 128, - PERIPH_ID_SPI3, - PERIPH_ID_SPI4, - PERIPH_ID_SDMMC4, - PERIPH_ID_PWM0, - PERIPH_ID_PWM1, - PERIPH_ID_PWM2, - PERIPH_ID_PWM3, - PERIPH_ID_PWM4, - PERIPH_ID_I2C10 = 203, - - PERIPH_ID_NONE = -1, -}; - -#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h deleted file mode 100644 index 0b91ef6..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * Abhilash Kesavan <a.kesavan@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_PINMUX_H -#define __ASM_ARM_ARCH_PINMUX_H - -#include "periph.h" - -/* - * Flags for setting specific configarations of peripherals. - * List will grow with support for more devices getting added. - */ -enum { - PINMUX_FLAG_NONE = 0x00000000, - - /* Flags for eMMC */ - PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ - - /* Flags for SROM controller */ - PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ - PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ -}; - -/** - * Configures the pinmux for a particular peripheral. - * - * Each gpio can be configured in many different ways (4 bits on exynos) - * such as "input", "output", "special function", "external interrupt" - * etc. This function will configure the peripheral pinmux along with - * pull-up/down and drive strength. - * - * @param peripheral peripheral to be configured - * @param flags configure flags - * @return 0 if ok, -1 on error (e.g. unsupported peripheral) - */ -int exynos_pinmux_config(int peripheral, int flags); - -/** - * Decode the peripheral id using the interrpt numbers. - * - * @param blob Device tree blob - * @param node FDT I2C node to find - * @return peripheral id if ok, PERIPH_ID_NONE on error - */ -int pinmux_decode_periph_id(const void *blob, int node); -#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/power.h b/arch/arm/include/asm/arch-s5pc1xx/power.h deleted file mode 100644 index 8400cda..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/power.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2009 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_POWER_H_ -#define __ASM_ARM_ARCH_POWER_H_ - -/* - * Power control - */ -#define S5PC100_OTHERS 0xE0108200 -#define S5PC100_RST_STAT 0xE0108300 -#define S5PC100_SLEEP_WAKEUP (1 << 3) -#define S5PC100_WAKEUP_STAT 0xE0108304 -#define S5PC100_INFORM0 0xE0108400 - -#define S5PC110_RST_STAT 0xE010A000 -#define S5PC110_SLEEP_WAKEUP (1 << 3) -#define S5PC110_WAKEUP_STAT 0xE010C200 -#define S5PC110_OTHERS 0xE010E000 -#define S5PC110_USB_PHY_CON 0xE010E80C -#define S5PC110_INFORM0 0xE010F000 - -#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/include/asm/arch-s5pc1xx/pwm.h deleted file mode 100644 index 7a33ed8..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_PWM_H_ -#define __ASM_ARM_ARCH_PWM_H_ - -#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */ -#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ - -/* Divider MUX */ -#define MUX_DIV_1 0 /* 1/1 period */ -#define MUX_DIV_2 1 /* 1/2 period */ -#define MUX_DIV_4 2 /* 1/4 period */ -#define MUX_DIV_8 3 /* 1/8 period */ -#define MUX_DIV_16 4 /* 1/16 period */ - -#define MUX_DIV_SHIFT(x) (x * 4) - -#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2) - -#define TCON_START(x) (1 << TCON_OFFSET(x)) -#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) -#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) -#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) -#define TCON4_AUTO_RELOAD (1 << 22) - -#ifndef __ASSEMBLY__ -struct s5p_timer { - unsigned int tcfg0; - unsigned int tcfg1; - unsigned int tcon; - unsigned int tcntb0; - unsigned int tcmpb0; - unsigned int tcnto0; - unsigned int tcntb1; - unsigned int tcmpb1; - unsigned int tcnto1; - unsigned int tcntb2; - unsigned int tcmpb2; - unsigned int tcnto2; - unsigned int tcntb3; - unsigned int res1; - unsigned int tcnto3; - unsigned int tcntb4; - unsigned int tcnto4; - unsigned int tintcstat; -}; -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/sromc.h b/arch/arm/include/asm/arch-s5pc1xx/sromc.h deleted file mode 100644 index df1bf51..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/sromc.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2010 Samsung Electronics - * Naveen Krishna Ch <ch.naveen@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Note: This file contains the register description for Memory subsystem - * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. - * - * Only SROMC is defined as of now - */ - -#ifndef __ASM_ARCH_SROMC_H_ -#define __ASM_ARCH_SROMC_H_ - -#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) -#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ - /* 1-> Byte base address*/ -#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) -#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) - -#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ -#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ -#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ -#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ -#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ -#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ -#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ - -#ifndef __ASSEMBLY__ -struct s5p_sromc { - unsigned int bw; - unsigned int bc[6]; -}; -#endif /* __ASSEMBLY__ */ - -/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ -void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); - -#endif /* __ASM_ARCH_SMC_H_ */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h b/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h deleted file mode 100644 index 647d6c4..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electrnoics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -u32 get_device_type(void); - -#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/uart.h b/arch/arm/include/asm/arch-s5pc1xx/uart.h deleted file mode 100644 index 26db098..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/uart.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_UART_H_ -#define __ASM_ARCH_UART_H_ - -#ifndef __ASSEMBLY__ -/* baudrate rest value */ -union br_rest { - unsigned short slot; /* udivslot */ - unsigned char value; /* ufracval */ -}; - -struct s5p_uart { - unsigned int ulcon; - unsigned int ucon; - unsigned int ufcon; - unsigned int umcon; - unsigned int utrstat; - unsigned int uerstat; - unsigned int ufstat; - unsigned int umstat; - unsigned char utxh; - unsigned char res1[3]; - unsigned char urxh; - unsigned char res2[3]; - unsigned int ubrdiv; - union br_rest rest; - unsigned char res3[0x3d0]; -}; - -static inline int s5p_uart_divslot(void) -{ - return 1; -} - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/watchdog.h b/arch/arm/include/asm/arch-s5pc1xx/watchdog.h deleted file mode 100644 index 2f9746c..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/watchdog.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics - * Heungjun Kim <riverful.kim@samsung.com> - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_WATCHDOG_H_ -#define __ASM_ARM_ARCH_WATCHDOG_H_ - -#define WTCON_RESET_OFFSET 0 -#define WTCON_INTEN_OFFSET 2 -#define WTCON_CLKSEL_OFFSET 3 -#define WTCON_EN_OFFSET 5 -#define WTCON_PRE_OFFSET 8 - -#define WTCON_CLK_16 0x0 -#define WTCON_CLK_32 0x1 -#define WTCON_CLK_64 0x2 -#define WTCON_CLK_128 0x3 - -#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET) -#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET) -#define WTCON_EN (0x1 << WTCON_EN_OFFSET) -#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET) -#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET) - -#ifndef __ASSEMBLY__ -struct s5p_watchdog { - unsigned int wtcon; - unsigned int wtdat; - unsigned int wtcnt; - unsigned int wtclrint; -}; - -/* functions */ -void wdt_stop(void); -void wdt_start(unsigned int timeout); -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/arm/include/asm/arch-stm32f1/gpio.h b/arch/arm/include/asm/arch-stm32f1/gpio.h index 6976e1f..8e8712f 100644 --- a/arch/arm/include/asm/arch-stm32f1/gpio.h +++ b/arch/arm/include/asm/arch-stm32f1/gpio.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h index 686cb4f..4094a75 100644 --- a/arch/arm/include/asm/arch-stm32f1/stm32.h +++ b/arch/arm/include/asm/arch-stm32f1/stm32.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/include/asm/arch-stm32f4/fmc.h b/arch/arm/include/asm/arch-stm32f4/fmc.h index 4ab3031..7dd5077 100644 --- a/arch/arm/include/asm/arch-stm32f4/fmc.h +++ b/arch/arm/include/asm/arch-stm32f4/fmc.h @@ -3,7 +3,7 @@ * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h index dd33b96..831c542 100644 --- a/arch/arm/include/asm/arch-stm32f4/gpio.h +++ b/arch/arm/include/asm/arch-stm32f4/gpio.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 7ca6dc3..6b64d03 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -106,6 +106,14 @@ struct stm32_flash_regs { #define STM32_FLASH_CR_SNB_OFFSET 3 #define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET) +/* + * Peripheral base addresses + */ +#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000) +#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400) +#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800) +#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400) + enum clock { CLOCK_CORE, CLOCK_AHB, diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 3e5d999..8ca58ae 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -15,7 +15,9 @@ #define CLK_GATE_CLOSE 0x0 /* clock control module regs definition */ -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) +#if defined(CONFIG_MACH_SUN8I_A83T) +#include <asm/arch/clock_sun8i_a83t.h> +#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) #include <asm/arch/clock_sun6i.h> #elif defined(CONFIG_MACH_SUN9I) #include <asm/arch/clock_sun9i.h> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 9b7b90c..5c76275 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -201,6 +201,7 @@ struct sunxi_ccm_reg { #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) #define CCM_PLL6_CTRL_K_SHIFT 4 #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) +#define CCM_PLL6_CTRL_LOCK (1 << 28) #define CCM_MIPI_PLL_CTRL_M_SHIFT 0 #define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) @@ -219,7 +220,7 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31) -#define AHB1_ABP1_DIV_DEFAULT 0x00002020 +#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ #define AXI_GATE_OFFSET_DRAM 0 @@ -282,6 +283,9 @@ struct sunxi_ccm_reg { #define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) #define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) #define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) +#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20) +#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20) +#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20) #define CCM_DRAMCLK_CFG_UPD (0x1 << 16) #define CCM_DRAMCLK_CFG_RST (0x1 << 31) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h new file mode 100644 index 0000000..5f93d7f --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -0,0 +1,304 @@ +/* + * sun8i a83t clock register definitions + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * from sun6i.h + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN8I_A83T_H +#define _SUNXI_CLOCK_SUN8I_A83T_H + +struct sunxi_ccm_reg { + u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */ + u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */ + u32 pll2_cfg; /* 0x08 pll2 audio control */ + u32 reserved1; + u32 pll3_cfg; /* 0x10 pll3 video0 control */ + u32 reserved2; + u32 pll4_cfg; /* 0x18 pll4 ve control */ + u32 reserved3; + u32 pll5_cfg; /* 0x20 pll5 ddr control */ + u32 reserved4; + u32 pll6_cfg; /* 0x28 pll6 peripheral control */ + u32 reserved5[3]; /* 0x2c */ + u32 pll7_cfg; /* 0x38 pll7 gpu control */ + u32 reserved6[2]; /* 0x3c */ + u32 pll8_cfg; /* 0x44 pll8 hsic control */ + u32 pll9_cfg; /* 0x48 pll9 de control */ + u32 pll10_cfg; /* 0x4c pll10 video1 control */ + u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ + u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ + u32 apb2_div; /* 0x58 APB2 divide ratio */ + u32 ahb2_div; /* 0x5c AHB2 divide ratio */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb1_gate; /* 0x68 apb1 module clock gating 3 */ + u32 apb2_gate; /* 0x6c apb2 module clock gating 4 */ + u32 reserved7[2]; /* 0x70 */ + u32 cci400_cfg; /* 0x78 cci400 clock configuration A83T only */ + u32 reserved8; /* 0x7c */ + u32 nand0_clk_cfg; /* 0x80 nand clock control */ + u32 reserved9; /* 0x84 */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 reserved10; /* 0x98 */ + u32 ss_clk_cfg; /* 0x9c security system clock control */ + u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ + u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ + u32 reserved11[2]; /* 0xa8 */ + u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control */ + u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ + u32 i2s2_clk_cfg; /* 0xb8 I2S2 clock control */ + u32 tdm_clk_cfg; /* 0xbc TDM clock control */ + u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ + u32 reserved12[2]; /* 0xc4 */ + u32 usb_clk_cfg; /* 0xcc USB clock control */ + u32 reserved13[9]; /* 0xd0 */ + u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ + u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register */ + u32 mbus_reset; /* 0xfc MBUS reset control */ + u32 dram_clk_gate; /* 0x100 DRAM module gating */ + u32 reserved14[5]; /* 0x104 BE0 */ + u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */ + u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */ + u32 reserved15[4]; /* 0x120 */ + u32 mipi_csi_clk_cfg; /* 0x130 MIPI CSI module clock */ + u32 csi_clk_cfg; /* 0x134 CSI module clock */ + u32 reserved16; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c VE module clock */ + u32 reserved17; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 AVS module clock */ + u32 reserved18[2]; /* 0x148 */ + u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ + u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */ + u32 reserved19; /* 0x158 */ + u32 mbus_clk_cfg; /* 0x15c MBUS module clock */ + u32 reserved20[2]; /* 0x160 */ + u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ + u32 reserved21[13]; /* 0x16c */ + u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ + u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ + u32 gpu_hyd_clk_cfg; /* 0x1a8 GPU HYD clock config */ + u32 reserved22[21]; /* 0x1ac */ + u32 pll_stable0; /* 0x200 PLL stable time 0 */ + u32 pll_stable1; /* 0x204 PLL stable time 1 */ + u32 reserved23; /* 0x208 */ + u32 pll_stable_status; /* 0x20c PLL stable status register */ + u32 reserved24[4]; /* 0x210 */ + u32 pll1_c0_bias_cfg; /* 0x220 PLL1 c0cpu# Bias config */ + u32 pll2_bias_cfg; /* 0x224 PLL2 audio Bias config */ + u32 pll3_bias_cfg; /* 0x228 PLL3 video Bias config */ + u32 pll4_bias_cfg; /* 0x22c PLL4 ve Bias config */ + u32 pll5_bias_cfg; /* 0x230 PLL5 ddr Bias config */ + u32 pll6_bias_cfg; /* 0x234 PLL6 periph Bias config */ + u32 pll1_c1_bias_cfg; /* 0x238 PLL1 c1cpu# Bias config */ + u32 pll8_bias_cfg; /* 0x23c PLL7 Bias config */ + u32 reserved25; /* 0x240 */ + u32 pll9_bias_cfg; /* 0x244 PLL9 hsic Bias config */ + u32 de_bias_cfg; /* 0x248 display engine Bias config */ + u32 video1_bias_cfg; /* 0x24c pll video1 bias register */ + u32 c0_tuning_cfg; /* 0x250 pll c0cpu# tuning register */ + u32 c1_tuning_cfg; /* 0x254 pll c1cpu# tuning register */ + u32 reserved26[11]; /* 0x258 */ + u32 pll2_pattern_cfg0; /* 0x284 PLL2 Pattern register 0 */ + u32 pll3_pattern_cfg0; /* 0x288 PLL3 Pattern register 0 */ + u32 reserved27; /* 0x28c */ + u32 pll5_pattern_cfg0; /* 0x290 PLL5 Pattern register 0*/ + u32 reserved28[4]; /* 0x294 */ + u32 pll2_pattern_cfg1; /* 0x2a4 PLL2 Pattern register 1 */ + u32 pll3_pattern_cfg1; /* 0x2a8 PLL3 Pattern register 1 */ + u32 reserved29; /* 0x2ac */ + u32 pll5_pattern_cfg1; /* 0x2b0 PLL5 Pattern register 1 */ + u32 reserved30[3]; /* 0x2b4 */ + u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ + u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ + u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ + u32 reserved31; + u32 ahb_reset3_cfg; /* 0x2d0 AHB1 Reset 3 config */ + u32 reserved32; /* 0x2d4 */ + u32 apb2_reset_cfg; /* 0x2d8 BUS Reset 4 config */ +}; + +/* apb2 bit field */ +#define APB2_CLK_SRC_LOSC (0x0 << 24) +#define APB2_CLK_SRC_OSC24M (0x1 << 24) +#define APB2_CLK_SRC_PLL6 (0x2 << 24) +#define APB2_CLK_SRC_MASK (0x3 << 24) +#define APB2_CLK_RATE_N_1 (0x0 << 16) +#define APB2_CLK_RATE_N_2 (0x1 << 16) +#define APB2_CLK_RATE_N_4 (0x2 << 16) +#define APB2_CLK_RATE_N_8 (0x3 << 16) +#define APB2_CLK_RATE_N_MASK (3 << 16) +#define APB2_CLK_RATE_M(m) (((m)-1) << 0) +#define APB2_CLK_RATE_M_MASK (0x1f << 0) + +/* apb2 gate field */ +#define APB2_GATE_UART_SHIFT (16) +#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) +#define APB2_GATE_TWI_SHIFT (0) +#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) + +/* cpu_axi_cfg bits */ +#define AXI0_DIV_SHIFT 0 +#define AXI1_DIV_SHIFT 16 +#define C0_CPUX_CLK_SRC_SHIFT 12 +#define C1_CPUX_CLK_SRC_SHIFT 28 + +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define CPU_CLK_SRC_OSC24M 0 +#define CPU_CLK_SRC_PLL1 1 + +#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0xff) << 8) +#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) +#define CCM_PLL1_CTRL_EN (0x1 << 31) +#define CMM_PLL1_CLOCK_TIME_2 (0x2 << 24) + +#define PLL8_CFG_DEFAULT 0x42800 +#define CCM_CCI400_CLK_SEL_HSIC (0x2<<24) + +#define CCM_PLL5_DIV1_SHIFT 16 +#define CCM_PLL5_DIV2_SHIFT 18 +#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) +#define CCM_PLL5_CTRL_UPD (0x1 << 30) +#define CCM_PLL5_CTRL_EN (0x1 << 31) + +#define PLL6_CFG_DEFAULT 0x80001900 /* 600 MHz */ +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_DIV1_SHIFT 16 +#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) +#define CCM_PLL6_CTRL_DIV2_SHIFT 18 +#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) + +#define AHB1_ABP1_DIV_DEFAULT 0x00002190 +#define AHB1_CLK_SRC_MASK (0x3<<12) +#define AHB1_CLK_SRC_INTOSC (0x0<<12) +#define AHB1_CLK_SRC_OSC24M (0x1<<12) +#define AHB1_CLK_SRC_PLL6 (0x2<<12) + +#define AXI_GATE_OFFSET_DRAM 0 + +/* ahb_gate0 offsets */ +#define AHB_GATE_OFFSET_USB_OHCI1 30 +#define AHB_GATE_OFFSET_USB_OHCI0 29 +#define AHB_GATE_OFFSET_USB_EHCI1 27 +#define AHB_GATE_OFFSET_USB_EHCI0 26 +#define AHB_GATE_OFFSET_USB0 24 +#define AHB_GATE_OFFSET_SPI1 21 +#define AHB_GATE_OFFSET_SPI0 20 +#define AHB_GATE_OFFSET_HSTIMER 19 +#define AHB_GATE_OFFSET_EMAC 17 +#define AHB_GATE_OFFSET_MCTL 14 +#define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_NAND0 13 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +#define AHB_GATE_OFFSET_DMA 6 +#define AHB_GATE_OFFSET_SS 5 + +/* ahb_gate1 offsets */ +#define AHB_GATE_OFFSET_DRC0 25 +#define AHB_GATE_OFFSET_DE_FE0 14 +#define AHB_GATE_OFFSET_DE_BE0 12 +#define AHB_GATE_OFFSET_HDMI 11 +#define AHB_GATE_OFFSET_LCD1 5 +#define AHB_GATE_OFFSET_LCD0 4 + +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) +#define CCM_MMC_CTRL_N(x) ((x) << 16) +#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) +#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) +#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +/* There is no global phy clk gate on sun6i, define as 0 */ +#define CCM_USB_CTRL_PHYGATE 0 +#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) +#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) +#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) + +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) + +#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ + +#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0) +#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) +#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) +#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) +#define CCM_DRAMCLK_CFG_UPD (0x1 << 16) +#define CCM_DRAMCLK_CFG_RST (0x1 << 31) + +#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */ +#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */ +#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16) + +#define CCM_MBUS_RESET_RESET (0x1 << 31) + +#define CCM_DRAM_GATE_OFFSET_DE_FE0 24 +#define CCM_DRAM_GATE_OFFSET_DE_FE1 25 +#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 +#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 + + +#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */ + +#define MBUS_CLK_GATE (0x1 << 31) + +/* ahb_reset0 offsets */ +#define AHB_RESET_OFFSET_GMAC 17 +#define AHB_RESET_OFFSET_MCTL 14 +#define AHB_RESET_OFFSET_MMC3 11 +#define AHB_RESET_OFFSET_MMC2 10 +#define AHB_RESET_OFFSET_MMC1 9 +#define AHB_RESET_OFFSET_MMC0 8 +#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) +#define AHB_RESET_OFFSET_SS 5 + +/* ahb_reset1 offsets */ +#define AHB_RESET_OFFSET_SAT 26 +#define AHB_RESET_OFFSET_DRC0 25 +#define AHB_RESET_OFFSET_DE_FE0 14 +#define AHB_RESET_OFFSET_DE_BE0 12 +#define AHB_RESET_OFFSET_HDMI 11 +#define AHB_RESET_OFFSET_LCD1 5 +#define AHB_RESET_OFFSET_LCD0 4 + +/* ahb_reset2 offsets */ +#define AHB_RESET_OFFSET_LVDS 0 + +/* apb2 reset */ +#define APB2_RESET_UART_SHIFT (16) +#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) +#define APB2_RESET_TWI_SHIFT (0) +#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) + + +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +void clock_set_pll5(unsigned int clk); +unsigned int clock_get_pll6(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN8I_A83T_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 273f80f..675876f 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -22,6 +22,10 @@ #include <asm/arch/dram_sun8i_a23.h> #elif defined(CONFIG_MACH_SUN8I_A33) #include <asm/arch/dram_sun8i_a33.h> +#elif defined(CONFIG_MACH_SUN8I_A83T) +#include <asm/arch/dram_sun8i_a83t.h> +#elif defined(CONFIG_MACH_SUN8I_H3) +#include <asm/arch/dram_sun8i_h3.h> #else #include <asm/arch/dram_sun4i.h> #endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h new file mode 100644 index 0000000..2891b71 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h @@ -0,0 +1,201 @@ +/* + * Sun8i platform dram controller register and constant defines + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang <wangflord@allwinnertech.com> + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN8I_A83T_H +#define _SUNXI_DRAM_SUN8I_A83T_H + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u8 res0[0x4]; /* 0x0c */ + u32 mcr0_0; /* 0x10 */ + u32 mcr1_0; /* 0x14 */ + u32 mcr0_1; /* 0x18 */ + u32 mcr1_1; /* 0x1c */ + u32 mcr0_2; /* 0x20 */ + u32 mcr1_2; /* 0x24 */ + u32 mcr0_3; /* 0x28 */ + u32 mcr1_3; /* 0x2c */ + u32 mcr0_4; /* 0x30 */ + u32 mcr1_4; /* 0x34 */ + u32 mcr0_5; /* 0x38 */ + u32 mcr1_5; /* 0x3c */ + u32 mcr0_6; /* 0x40 */ + u32 mcr1_6; /* 0x44 */ + u32 mcr0_7; /* 0x48 */ + u32 mcr1_7; /* 0x4c */ + u32 mcr0_8; /* 0x50 */ + u32 mcr1_8; /* 0x54 */ + u32 mcr0_9; /* 0x58 */ + u32 mcr1_9; /* 0x5c */ + u32 mcr0_10; /* 0x60 */ + u32 mcr1_10; /* 0x64 */ + u32 mcr0_11; /* 0x68 */ + u32 mcr1_11; /* 0x6c */ + u32 mcr0_12; /* 0x70 */ + u32 mcr1_12; /* 0x74 */ + u32 mcr0_13; /* 0x78 */ + u32 mcr1_13; /* 0x7c */ + u32 mcr0_14; /* 0x80 */ + u32 mcr1_14; /* 0x84 */ + u32 mcr0_15; /* 0x88 */ + u32 mcr1_15; /* 0x8c */ + u32 bwcr; /* 0x90 */ + u32 maer; /* 0x94 */ + u32 mapr; /* 0x98 */ + u32 mcgcr; /* 0x9c */ + u32 bwctr; /* 0xa0 */ + u8 res2[0x8]; /* 0xa4 */ + u32 swoffr; /* 0xac */ + u8 res3[0x10]; /* 0xb0 */ + u32 swonr; /* 0xc0 */ + u8 res4[0x3c]; /* 0xc4 */ + u32 mdfscr; /* 0x100 */ + u32 mdfsmer; /* 0x104 */ +}; + +struct sunxi_mctl_ctl_reg { + u32 pir; /* 0x00 */ + u32 pwrctl; /* 0x04 */ + u32 mrctrl0; /* 0x08 */ + u32 clken; /* 0x0c */ + u32 pgsr0; /* 0x10 */ + u32 pgsr1; /* 0x14 */ + u32 statr; /* 0x18 */ + u8 res1[0x14]; /* 0x1c */ + u32 mr0; /* 0x30 */ + u32 mr1; /* 0x34 */ + u32 mr2; /* 0x38 */ + u32 mr3; /* 0x3c */ + u32 pllgcr; /* 0x40 */ + u32 ptr0; /* 0x44 */ + u32 ptr1; /* 0x48 */ + u32 ptr2; /* 0x4c */ + u32 ptr3; /* 0x50 */ + u32 ptr4; /* 0x54 */ + u32 dramtmg0; /* 0x58 dram timing parameters register 0 */ + u32 dramtmg1; /* 0x5c dram timing parameters register 1 */ + u32 dramtmg2; /* 0x60 dram timing parameters register 2 */ + u32 dramtmg3; /* 0x64 dram timing parameters register 3 */ + u32 dramtmg4; /* 0x68 dram timing parameters register 4 */ + u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ + u32 dramtmg6; /* 0x70 dram timing parameters register 6 */ + u32 dramtmg7; /* 0x74 dram timing parameters register 7 */ + u32 dramtmg8; /* 0x78 dram timing parameters register 8 */ + u32 odtcfg; /* 0x7c */ + u32 pitmg0; /* 0x80 */ + u32 pitmg1; /* 0x84 */ + u8 res2[0x4]; /* 0x88 */ + u32 rfshctl0; /* 0x8c */ + u32 rfshtmg; /* 0x90 */ + u32 rfshctl1; /* 0x94 */ + u32 pwrtmg; /* 0x98 */ + u8 res3[0x20]; /* 0x9c */ + u32 dqsgmr; /* 0xbc */ + u32 dtcr; /* 0xc0 */ + u32 dtar0; /* 0xc4 */ + u32 dtar1; /* 0xc8 */ + u32 dtar2; /* 0xcc */ + u32 dtar3; /* 0xd0 */ + u32 dtdr0; /* 0xd4 */ + u32 dtdr1; /* 0xd8 */ + u32 dtmr0; /* 0xdc */ + u32 dtmr1; /* 0xe0 */ + u32 dtbmr; /* 0xe4 */ + u32 catr0; /* 0xe8 */ + u32 catr1; /* 0xec */ + u32 dtedr0; /* 0xf0 */ + u32 dtedr1; /* 0xf4 */ + u8 res4[0x8]; /* 0xf8 */ + u32 pgcr0; /* 0x100 */ + u32 pgcr1; /* 0x104 */ + u32 pgcr2; /* 0x108 */ + u32 pgcr3; /* 0x10c */ + u32 iovcr0; /* 0x110 */ + u32 iovcr1; /* 0x114 */ + u32 dqsdr; /* 0x118 */ + u32 dxccr; /* 0x11c */ + u32 odtmap; /* 0x120 */ + u32 zqctl0; /* 0x124 */ + u32 zqctl1; /* 0x128 */ + u8 res6[0x14]; /* 0x12c */ + u32 zqncr; /* 0x140 zq control register 0 */ + u32 zqnpr; /* 0x144 zq control register 1 */ + u32 zqndr; /* 0x148 zq control register 2 */ + u32 zqnsr; /* 0x14c zq status register 0 */ + u32 res7; /* 0x150 zq status register 1 */ + u8 res8[0x6c]; /* 0x154 */ + u32 sched; /* 0x1c0 */ + u32 perfhpr0; /* 0x1c4 */ + u32 perfhpr1; /* 0x1c8 */ + u32 perflpr0; /* 0x1cc */ + u32 perflpr1; /* 0x1d0 */ + u32 perfwr0; /* 0x1d4 */ + u32 perfwr1; /* 0x1d8 */ +}; + + +#define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x) +#define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x) +#define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x) + +#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x) +#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) +#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x) +#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x) +#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x) + +#define CAIOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x)) +#define DXnMDLR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x) +#define DXMDLR0 (SUNXI_DRAM_CTL0_BASE + 0x00000300) +#define DXnLCDLR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000304 + 0x80 * x) +#define DXnLCDLR1(x) (SUNXI_DRAM_CTL0_BASE + 0x00000308 + 0x80 * x) +#define DXnLCDLR2(x) (SUNXI_DRAM_CTL0_BASE + 0x0000030c + 0x80 * x) +#define DATX0IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000310 + 0x4 * x) +#define DATX1IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000390 + 0x4 * x) +#define DATX2IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000410 + 0x4 * x) +#define DATX3IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000490 + 0x4 * x) +#define MX_UPD0 (SUNXI_DRAM_CTL0_BASE + 0x00000880) +#define MX_UPD2 (SUNXI_DRAM_CTL0_BASE + 0x00000888) + +#define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800) +#define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x) +#define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x) + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_RANK_MASK (3 << 0) +#define MCTL_CR_RANK(x) (((x) - 1) << 0) +#define MCTL_CR_BANK_MASK (3 << 2) +#define MCTL_CR_BANK(x) ((x) << 2) +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_BUSW_MASK (7 << 12) +#define MCTL_CR_BUSW8 (0 << 12) +#define MCTL_CR_BUSW16 (1 << 12) +#define MCTL_CR_SEQUENCE (1 << 15) +#define MCTL_CR_DDR3 (3 << 16) +#define MCTL_CR_CHANNEL_MASK (1 << 19) +#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) +#define MCTL_CR_UNKNOWN (0x4 << 20) +#define MCTL_CR_CS1_CONTROL(x) ((x) << 24) + +/* DRAM control (sunxi_mctl_ctl_reg) register constants */ +#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */ +#define MCTL_MR1 0x40 +#define MCTL_MR2 0x18 /* CWL=8 */ +#define MCTL_MR3 0x0 + +#endif /* _SUNXI_DRAM_SUN8I_A83T_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h new file mode 100644 index 0000000..d0f2b8a --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h @@ -0,0 +1,185 @@ +/* + * sun8i H3 platform dram controller register and constant defines + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang <wangflord@allwinnertech.com> + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> + * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN8I_H3_H +#define _SUNXI_DRAM_SUN8I_H3_H + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 control register */ + u8 res0[0xc]; /* 0x04 */ + u32 mcr[16][2]; /* 0x10 */ + u32 bwcr; /* 0x90 bandwidth control register */ + u32 maer; /* 0x94 master enable register */ + u32 mapr; /* 0x98 master priority register */ + u32 mcgcr; /* 0x9c */ + u32 cpu_bwcr; /* 0xa0 */ + u32 gpu_bwcr; /* 0xa4 */ + u32 ve_bwcr; /* 0xa8 */ + u32 disp_bwcr; /* 0xac */ + u32 other_bwcr; /* 0xb0 */ + u32 total_bwcr; /* 0xb4 */ + u8 res1[0x8]; /* 0xb8 */ + u32 swonr; /* 0xc0 */ + u32 swoffr; /* 0xc4 */ + u8 res2[0x8]; /* 0xc8 */ + u32 cccr; /* 0xd0 */ + u8 res3[0x72c]; /* 0xd4 */ + u32 protect; /* 0x800 */ +}; + +#define MCTL_CR_BL8 (0x4 << 20) + +#define MCTL_CR_1T (0x1 << 19) +#define MCTL_CR_2T (0x0 << 19) + +#define MCTL_CR_LPDDR3 (0x7 << 16) +#define MCTL_CR_LPDDR2 (0x6 << 16) +#define MCTL_CR_DDR3 (0x3 << 16) +#define MCTL_CR_DDR2 (0x2 << 16) + +#define MCTL_CR_SEQUENTIAL (0x1 << 15) +#define MCTL_CR_INTERLEAVED (0x0 << 15) + +#define MCTL_CR_32BIT (0x1 << 12) +#define MCTL_CR_16BIT (0x0 << 12) +#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT) + +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) +#define MCTL_CR_EIGHT_BANKS (0x1 << 2) +#define MCTL_CR_FOUR_BANKS (0x0 << 2) +#define MCTL_CR_DUAL_RANK (0x1 << 0) +#define MCTL_CR_SINGLE_RANK (0x0 << 0) + +#define PROTECT_MAGIC (0x94be6fa3) + +struct sunxi_mctl_ctl_reg { + u32 pir; /* 0x00 PHY initialization register */ + u32 pwrctl; /* 0x04 */ + u32 mrctrl; /* 0x08 */ + u32 clken; /* 0x0c */ + u32 pgsr[2]; /* 0x10 PHY general status registers */ + u32 statr; /* 0x18 */ + u8 res1[0x14]; /* 0x1c */ + u32 mr[4]; /* 0x30 mode registers */ + u32 pllgcr; /* 0x40 */ + u32 ptr[5]; /* 0x44 PHY timing registers */ + u32 dramtmg[9]; /* 0x58 DRAM timing registers */ + u32 odtcfg; /* 0x7c */ + u32 pitmg[2]; /* 0x80 PHY interface timing registers */ + u8 res2[0x4]; /* 0x88 */ + u32 rfshctl0; /* 0x8c */ + u32 rfshtmg; /* 0x90 refresh timing */ + u32 rfshctl1; /* 0x94 */ + u32 pwrtmg; /* 0x98 */ + u8 res3[0x20]; /* 0x9c */ + u32 dqsgmr; /* 0xbc */ + u32 dtcr; /* 0xc0 */ + u32 dtar[4]; /* 0xc4 */ + u32 dtdr[2]; /* 0xd4 */ + u32 dtmr[2]; /* 0xdc */ + u32 dtbmr; /* 0xe4 */ + u32 catr[2]; /* 0xe8 */ + u32 dtedr[2]; /* 0xf0 */ + u8 res4[0x8]; /* 0xf8 */ + u32 pgcr[4]; /* 0x100 PHY general configuration registers */ + u32 iovcr[2]; /* 0x110 */ + u32 dqsdr; /* 0x118 */ + u32 dxccr; /* 0x11c */ + u32 odtmap; /* 0x120 */ + u32 zqctl[2]; /* 0x124 */ + u8 res6[0x14]; /* 0x12c */ + u32 zqcr; /* 0x140 ZQ control register */ + u32 zqsr; /* 0x144 ZQ status register */ + u32 zqdr[3]; /* 0x148 ZQ data registers */ + u8 res7[0x6c]; /* 0x154 */ + u32 sched; /* 0x1c0 */ + u32 perfhpr[2]; /* 0x1c4 */ + u32 perflpr[2]; /* 0x1cc */ + u32 perfwr[2]; /* 0x1d4 */ + u8 res8[0x2c]; /* 0x1dc */ + u32 aciocr; /* 0x208 */ + u8 res9[0xf4]; /* 0x20c */ + struct { /* 0x300 DATX8 modules*/ + u32 mdlr; /* 0x00 */ + u32 lcdlr[3]; /* 0x04 */ + u32 iocr[11]; /* 0x10 IO configuration register */ + u32 bdlr6; /* 0x3c */ + u32 gtr; /* 0x40 */ + u32 gcr; /* 0x44 */ + u32 gsr[3]; /* 0x48 */ + u8 res0[0x2c]; /* 0x54 */ + } datx[4]; + u8 res10[0x388]; /* 0x500 */ + u32 upd2; /* 0x888 */ +}; + +#define PTR3_TDINIT1(x) ((x) << 20) +#define PTR3_TDINIT0(x) ((x) << 0) + +#define PTR4_TDINIT3(x) ((x) << 20) +#define PTR4_TDINIT2(x) ((x) << 0) + +#define DRAMTMG0_TWTP(x) ((x) << 24) +#define DRAMTMG0_TFAW(x) ((x) << 16) +#define DRAMTMG0_TRAS_MAX(x) ((x) << 8) +#define DRAMTMG0_TRAS(x) ((x) << 0) + +#define DRAMTMG1_TXP(x) ((x) << 16) +#define DRAMTMG1_TRTP(x) ((x) << 8) +#define DRAMTMG1_TRC(x) ((x) << 0) + +#define DRAMTMG2_TCWL(x) ((x) << 24) +#define DRAMTMG2_TCL(x) ((x) << 16) +#define DRAMTMG2_TRD2WR(x) ((x) << 8) +#define DRAMTMG2_TWR2RD(x) ((x) << 0) + +#define DRAMTMG3_TMRW(x) ((x) << 16) +#define DRAMTMG3_TMRD(x) ((x) << 12) +#define DRAMTMG3_TMOD(x) ((x) << 0) + +#define DRAMTMG4_TRCD(x) ((x) << 24) +#define DRAMTMG4_TCCD(x) ((x) << 16) +#define DRAMTMG4_TRRD(x) ((x) << 8) +#define DRAMTMG4_TRP(x) ((x) << 0) + +#define DRAMTMG5_TCKSRX(x) ((x) << 24) +#define DRAMTMG5_TCKSRE(x) ((x) << 16) +#define DRAMTMG5_TCKESR(x) ((x) << 8) +#define DRAMTMG5_TCKE(x) ((x) << 0) + +#define RFSHTMG_TREFI(x) ((x) << 16) +#define RFSHTMG_TRFC(x) ((x) << 0) + +#define PIR_CLRSR (0x1 << 27) /* clear status registers */ +#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */ +#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */ +#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */ +#define PIR_PHYRST (0x1 << 6) /* PHY reset */ +#define PIR_DCAL (0x1 << 5) /* DDL calibration */ +#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */ +#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */ +#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */ + +#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */ + +#define ZQCR_PWRDOWN (0x1 << 31) /* ZQ power down */ + +#define DATX_IOCR_DQ(x) (x) /* DQ0-7 IOCR index */ +#define DATX_IOCR_DM (8) /* DM IOCR index */ +#define DATX_IOCR_DQS (9) /* DQS IOCR index */ +#define DATX_IOCR_DQSN (10) /* DQSN IOCR index */ + +#define DATX_IOCR_WRITE_DELAY(x) ((x) << 8) +#define DATX_IOCR_READ_DELAY(x) ((x) << 0) + +#endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 8382101..a2a9a38 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -147,6 +147,7 @@ enum sunxi_gpio_number { #define SUN7I_GPA_GMAC 5 #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4 +#define SUN8I_H3_GPA_UART0 2 #define SUN4I_GPB_TWI0 2 #define SUN4I_GPB_TWI1 2 @@ -157,6 +158,7 @@ enum sunxi_gpio_number { #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 #define SUN8I_A33_GPB_UART0 3 +#define SUN8I_A83T_GPB_UART0 2 #define SUNXI_GPC_NAND 2 #define SUNXI_GPC_SDC2 3 diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 0f03c24..bbf89d9 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -8,9 +8,6 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define ZYNQ_SERIAL_BASEADDR0 0xFF000000 -#define ZYNQ_SERIAL_BASEADDR1 0xFF001000 - #define ZYNQ_GEM_BASEADDR0 0xFF0B0000 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 @@ -22,9 +19,6 @@ #define ZYNQ_I2C_BASEADDR0 0xFF020000 #define ZYNQ_I2C_BASEADDR1 0xFF030000 -#define ZYNQ_SDHCI_BASEADDR0 0xFF160000 -#define ZYNQ_SDHCI_BASEADDR1 0xFF170000 - #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index f1e95a2..021626d 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -13,7 +13,6 @@ static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) { } -int zynq_sdhci_init(phys_addr_t regbase); int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h index d2aa1c4..200444d 100644 --- a/arch/arm/include/asm/armv7m.h +++ b/arch/arm/include/asm/armv7m.h @@ -3,7 +3,7 @@ * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index d8d9af4..2e2a3a8 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -119,7 +119,7 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, - u64 share); + u64 attribute); void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr); diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index f2d4c3c..806302b 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -11,13 +11,17 @@ #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM #define CONFIG_RSA #define CONFIG_RSA_FREESCALE_EXP + #ifndef CONFIG_FSL_CAAM #define CONFIG_FSL_CAAM #endif +#ifndef CONFIG_DM +#define CONFIG_DM +#endif + #define CONFIG_KEY_REVOCATION #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 4e3ea55..bd27281 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -46,7 +46,7 @@ struct arch_global_data { u32 omap_boot_mode; u8 omap_ch_flags; #endif -#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) unsigned long mem2_clk; #endif }; |