diff options
Diffstat (limited to 'arch/arm/include/asm')
58 files changed, 3899 insertions, 673 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 70f521d..63ed10b 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -23,9 +23,11 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_SPL_H_ +#define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #define BOOT_DEVICE_UART 65 +#define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF #endif diff --git a/arch/arm/include/asm/arch-tegra20/board.h b/arch/arm/include/asm/arch-armv7/globaltimer.h index a90d36c..0ac70fd 100644 --- a/arch/arm/include/asm/arch-tegra20/board.h +++ b/arch/arm/include/asm/arch-armv7/globaltimer.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. * * See file CREDITS for list of people who contributed to this * project. @@ -20,11 +20,17 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +#ifndef _GLOBALTIMER_H_ +#define _GLOBALTIMER_H_ -#ifndef _TEGRA_BOARD_H_ -#define _TEGRA_BOARD_H_ +struct globaltimer { + u32 cnt_l; /* 0x00 */ + u32 cnt_h; + u32 ctl; + u32 stat; + u32 cmp_l; /* 0x10 */ + u32 cmp_h; + u32 inc; +}; -/* Setup UARTs for the board according to the selected config */ -void board_init_uart_f(void); - -#endif +#endif /* _GLOBALTIMER_H_ */ diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index d28c51a..57bfe8e 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -155,10 +155,10 @@ struct kwgpio_registers { /* * functions */ -void reset_cpu(unsigned long ignored); unsigned char get_random_hex(void); unsigned int kw_sdram_bar(enum memory_bank bank); unsigned int kw_sdram_bs(enum memory_bank bank); +void kw_sdram_size_adjust(enum memory_bank bank); int kw_config_adr_windows(void); void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h index 8e50ee7..8ceea7b 100644 --- a/arch/arm/include/asm/arch-kirkwood/mpp.h +++ b/arch/arm/include/asm/arch-kirkwood/mpp.h @@ -85,7 +85,7 @@ #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) #define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h index a313b80..efbe038 100644 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ b/arch/arm/include/asm/arch-mx25/clock.h @@ -41,6 +41,7 @@ #endif enum mxc_clock { + /* PER clocks (do not change order) */ MXC_CSI_CLK, MXC_EPIT_CLK, MXC_ESAI_CLK, @@ -57,17 +58,18 @@ enum mxc_clock { MXC_SSI1_CLK, MXC_SSI2_CLK, MXC_UART_CLK, + /* Other clocks */ MXC_ARM_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_CSPI_CLK, MXC_FEC_CLK, MXC_CLK_NUM }; -ulong imx_get_perclk(int clk); -ulong imx_get_ahbclk(void); - -#define imx_get_uartclk() imx_get_perclk(15) -#define imx_get_fecclk() (imx_get_ahbclk()/2) - unsigned int mxc_get_clock(enum mxc_clock clk); +#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK) +#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) + #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 672f9d7..e780296 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -357,5 +357,6 @@ struct aips_regs { #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 +#define CHIP_REV_1_2 0x12 #endif /* _IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h index 3b694da..56cae36 100644 --- a/arch/arm/include/asm/arch-mx25/macro.h +++ b/arch/arm/include/asm/arch-mx25/macro.h @@ -32,32 +32,75 @@ #include <asm/arch/imx-regs.h> #include <generated/asm-offsets.h> +#include <asm/macro.h> -.macro init_aips - write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777 - write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777 - write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777 - write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777 +/* + * AIPS setup - Only setup MPROTx registers. + * The PACR default values are good. + * + * Default argument values: + * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to + * user-mode. + */ +.macro init_aips mpr=0x77777777 + ldr r0, =IMX_AIPS1_BASE + ldr r1, =\mpr + str r1, [r0, #AIPS_MPR_0_7] + str r1, [r0, #AIPS_MPR_8_15] + ldr r2, =IMX_AIPS2_BASE + str r1, [r2, #AIPS_MPR_0_7] + str r1, [r2, #AIPS_MPR_8_15] .endm -.macro init_max - write32 IMX_MAX_BASE + MAX_MPR0, 0x43210 - write32 IMX_MAX_BASE + MAX_MPR1, 0x43210 - write32 IMX_MAX_BASE + MAX_MPR2, 0x43210 - write32 IMX_MAX_BASE + MAX_MPR3, 0x43210 - write32 IMX_MAX_BASE + MAX_MPR4, 0x43210 - - write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10 - write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10 - write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10 - write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10 - write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10 +/* + * MAX (Multi-Layer AHB Crossbar Switch) setup + * + * Default argument values: + * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA + * - SGPCR: always park on last master + * - MGPCR: restore default values + */ +.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000 + ldr r0, =IMX_MAX_BASE + ldr r1, =\mpr + str r1, [r0, #MAX_MPR0] /* for S0 */ + str r1, [r0, #MAX_MPR1] /* for S1 */ + str r1, [r0, #MAX_MPR2] /* for S2 */ + str r1, [r0, #MAX_MPR3] /* for S3 */ + str r1, [r0, #MAX_MPR4] /* for S4 */ + ldr r1, =\sgpcr + str r1, [r0, #MAX_SGPCR0] /* for S0 */ + str r1, [r0, #MAX_SGPCR1] /* for S1 */ + str r1, [r0, #MAX_SGPCR2] /* for S2 */ + str r1, [r0, #MAX_SGPCR3] /* for S3 */ + str r1, [r0, #MAX_SGPCR4] /* for S4 */ + ldr r1, =\mgpcr + str r1, [r0, #MAX_MGPCR0] /* for M0 */ + str r1, [r0, #MAX_MGPCR1] /* for M1 */ + str r1, [r0, #MAX_MGPCR2] /* for M2 */ + str r1, [r0, #MAX_MGPCR3] /* for M3 */ + str r1, [r0, #MAX_MGPCR4] /* for M4 */ +.endm - write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0 - write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0 - write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0 - write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0 - write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0 +/* + * M3IF setup + * + * Default argument values: + * - CTL: + * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 + * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 + * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 + * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 + * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000 + * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000 + * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 + * ------------ + * 0x00000001 + */ +.macro init_m3if ctl=0x00000001 + /* M3IF Control Register (M3IFCTL) */ + write32 IMX_M3IF_CTRL_BASE, \ctl .endm #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 9468b45..1dbb8da 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -46,6 +46,7 @@ enum mxc_clock { MXC_UART_CLK, MXC_IPU_CLK, MXC_ESDHC_CLK, + MXC_I2C_CLK, }; unsigned int mxc_get_clock(enum mxc_clock clk); diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 1dd952c..8fd3d08 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -569,7 +569,8 @@ struct esdc_regs { #define MX31_IIM_BASE_ADDR 0x5001C000 -#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) +#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26) +#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23) #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) @@ -577,12 +578,23 @@ struct esdc_regs { #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) #define PDR0_MCU_PODF(x) ((x) & 0x7) +#define PDR1_USB_PRDF(x) (((x) & 0x3) << 30) +#define PDR1_USB_PODF(x) (((x) & 0x7) << 27) +#define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24) +#define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18) +#define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15) +#define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9) +#define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6) +#define PDR1_SSI1_PODF(x) ((x) & 0x3f) + +#define PLL_BRMO(x) (((x) & 0x1) << 31) #define PLL_PD(x) (((x) & 0xf) << 26) #define PLL_MFD(x) (((x) & 0x3ff) << 16) #define PLL_MFI(x) (((x) & 0xf) << 10) #define PLL_MFN(x) (((x) & 0x3ff) << 0) -#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff) +#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f) +#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7) #define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f) #define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7) #define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7) diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h index eb7458a..2eff08d 100644 --- a/arch/arm/include/asm/arch-mx35/clock.h +++ b/arch/arm/include/asm/arch-mx35/clock.h @@ -48,6 +48,7 @@ enum mxc_clock { MXC_USB_CLK, MXC_CSPI_CLK, MXC_FEC_CLK, + MXC_I2C_CLK, }; enum mxc_main_clock { diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index 2c6e59c..7b09809 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -314,6 +314,58 @@ struct esdc_regs { #define ESDC_MISC_DDR_EN (1 << 8) #define ESDC_MISC_DDR2_EN (1 << 9) +/* Multi-Layer AHB Crossbar Switch (MAX) registers */ +struct max_regs { + u32 mpr0; + u32 pad00[3]; + u32 sgpcr0; + u32 pad01[59]; + u32 mpr1; + u32 pad02[3]; + u32 sgpcr1; + u32 pad03[59]; + u32 mpr2; + u32 pad04[3]; + u32 sgpcr2; + u32 pad05[59]; + u32 mpr3; + u32 pad06[3]; + u32 sgpcr3; + u32 pad07[59]; + u32 mpr4; + u32 pad08[3]; + u32 sgpcr4; + u32 pad09[251]; + u32 mgpcr0; + u32 pad10[63]; + u32 mgpcr1; + u32 pad11[63]; + u32 mgpcr2; + u32 pad12[63]; + u32 mgpcr3; + u32 pad13[63]; + u32 mgpcr4; + u32 pad14[63]; + u32 mgpcr5; +}; + +/* AHB <-> IP-Bus Interface (AIPS) */ +struct aips_regs { + u32 mpr_0_7; + u32 mpr_8_15; + u32 pad0[6]; + u32 pacr_0_7; + u32 pacr_8_15; + u32 pacr_16_23; + u32 pacr_24_31; + u32 pad1[4]; + u32 opacr_0_7; + u32 opacr_8_15; + u32 opacr_16_23; + u32 opacr_24_31; + u32 opacr_32_39; +}; + /* * NFMS bit in RCSR register for pagesize of nandflash */ diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 8d8fa18..9cdfb48 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -24,6 +24,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include <common.h> + +#ifdef CONFIG_SYS_MX5_HCLK +#define MXC_HCLK CONFIG_SYS_MX5_HCLK +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_SYS_MX5_CLK32 +#define MXC_CLK32 CONFIG_SYS_MX5_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_ARM_CLK = 0, MXC_AHB_CLK, @@ -31,18 +45,24 @@ enum mxc_clock { MXC_IPG_PERCLK, MXC_UART_CLK, MXC_CSPI_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_ESDHC4_CLK, MXC_FEC_CLK, MXC_SATA_CLK, MXC_DDR_CLK, MXC_NFC_CLK, MXC_PERIPH_CLK, + MXC_I2C_CLK, }; u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); -void set_usb_phy2_clk(void); +void set_usb_phy_clk(void); +void enable_usb_phy1_clk(unsigned char enable); void enable_usb_phy2_clk(unsigned char enable); void set_usboh3_clk(void); void enable_usboh3_clk(unsigned char enable); diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index 4e0fc1b..ddfab70 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -82,129 +82,526 @@ struct mxc_ccm_reg { u32 cmeor; }; +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (0x1 << 12) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCR_FPM_MULT (0x1 << 11) +#endif +#define MXC_CCM_CCR_CAMP2_EN (0x1 << 10) +#define MXC_CCM_CCR_CAMP1_EN (0x1 << 9) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCR_FPM_EN (0x1 << 8) +#endif +#define MXC_CCM_CCR_OSCNT_OFFSET 0 +#define MXC_CCM_CCR_OSCNT_MASK 0xFF +#define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) +#define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF) + +/* Define the bits in register CCSR */ +#if defined(CONFIG_MX51) +#define MXC_CCM_CCSR_LP_APM (0x1 << 9) +#elif defined(CONFIG_MX53) +#define MXC_CCM_CCSR_LP_APM (0x1 << 10) +#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9) +#endif +#define MXC_CCM_CCSR_STEP_SEL_OFFSET 7 +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) +#define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) +#define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3) +#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5 +#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5) +#define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5) +#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3) +#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3 +#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3) +#define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3) +#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2) +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1 + /* Define the bits in register CACRR */ #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 +#define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) +#define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7) /* Define the bits in register CBCDR */ #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) -#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) #define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) +#define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7) #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) +#define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7) #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19) +#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7) #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16) +#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7) #define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) +#define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13) +#define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7) #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10) +#define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7) #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8) +#define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3) #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3) #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3) +#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7) #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 +#define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7) +#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7) /* Define the bits in register CSCMR1 */ #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3) #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26 +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3) #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3) #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3) #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3) #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3) #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3) #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3) #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3) #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3) #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 /* Define the bits in register CSCDR2 */ #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7) #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F) #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7) #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F) #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 -#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0 -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0 +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F) /* Define the bits in register CBCMR */ #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3) #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3) #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3) #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3) #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3) #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3) #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) /* Define the bits in register CSCDR1 */ #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7) #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7) #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7) #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3) #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7) #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3) #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7) #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 +#define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7) /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) /* Define the bits in register CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 +#define MXC_CCM_CCGR_CG_OFF 0x0 +#define MXC_CCM_CCGR_CG_RUN_ON 0x1 +#define MXC_CCM_CCGR_CG_ON 0x3 + +#define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0 +#define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2 +#define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4 +#define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR0_TZIC_OFFSET 6 +#define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR0_DAP_OFFSET 8 +#define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR0_TPIU_OFFSET 10 +#define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR0_CTI2_OFFSET 12 +#define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR0_CTI3_OFFSET 14 +#define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16 +#define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18 +#define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR0_ROMCP_OFFSET 20 +#define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR0_ROM_OFFSET 22 +#define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24 +#define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26 +#define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28 +#define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR0_IIM_OFFSET 30 +#define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30) + +#define MXC_CCM_CCGR1_TMAX1_OFFSET 0 +#define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR1_TMAX2_OFFSET 2 +#define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR1_TMAX3_OFFSET 4 +#define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6 +#define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR1_UART1_PER_OFFSET 8 +#define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10 +#define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR1_UART2_PER_OFFSET 12 +#define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14 +#define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR1_UART3_PER_OFFSET 16 +#define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR1_I2C1_OFFSET 18 +#define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR1_I2C2_OFFSET 20 +#define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22 +#define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24 +#define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24) +#elif defined(CONFIG_MX53) +#define MXC_CCM_CCGR1_I2C3_OFFSET 22 +#define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22) +#endif +#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26 +#define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28 +#define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR1_SCC_OFFSET 30 +#define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30) + +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR2_USB_PHY_OFFSET 0 +#define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0) +#endif +#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2 +#define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4 +#define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6 +#define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8 +#define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10 +#define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12 +#define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14 +#define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16 +#define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18 +#define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR2_GPT_HF_OFFSET 20 +#define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR2_OWIRE_OFFSET 22 +#define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR2_FEC_OFFSET 24 +#define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26 +#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28 +#define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR2_TVE_OFFSET 30 +#define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30) -#define MXC_CCM_CCGR4_CG5_OFFSET 10 -#define MXC_CCM_CCGR4_CG6_OFFSET 12 -#define MXC_CCM_CCGR5_CG5_OFFSET 10 -#define MXC_CCM_CCGR2_CG14_OFFSET 28 +#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0 +#define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2 +#define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4 +#define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6 +#define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8 +#define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10 +#define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12 +#define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14 +#define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16 +#define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18 +#define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20 +#define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22 +#define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24 +#define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26 +#define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28 +#define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30 +#define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30) + +#define MXC_CCM_CCGR4_PATA_OFFSET 0 +#define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2 +#define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4 +#define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4) +#elif defined(CONFIG_MX53) +#define MXC_CCM_CCGR4_SATA_OFFSET 2 +#define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6 +#define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8 +#define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10 +#define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12 +#define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12) +#endif +#define MXC_CCM_CCGR4_SAHARA_OFFSET 14 +#define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR4_RTIC_OFFSET 16 +#define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18 +#define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20 +#define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22 +#define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24 +#define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26 +#define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR4_SRTC_OFFSET 28 +#define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR4_SDMA_OFFSET 30 +#define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30) + +#define MXC_CCM_CCGR5_SPBA_OFFSET 0 +#define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR5_GPU_OFFSET 2 +#define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR5_GARB_OFFSET 4 +#define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR5_VPU_OFFSET 6 +#define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR5_VPU_REF_OFFSET 8 +#define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR5_IPU_OFFSET 10 +#define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12 +#define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12) +#elif defined(CONFIG_MX53) +#define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12 +#define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12) +#endif +#define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14 +#define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14) +#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16 +#define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18 +#define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20 +#define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22 +#define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24 +#define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR5_SPDIF0_OFFSET 26 +#define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR5_SPDIF1_OFFSET 28 +#define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28) +#endif +#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30 +#define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30) + +#if defined(CONFIG_MX53) +#define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0 +#define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR6_OCRAM_OFFSET 2 +#define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2) +#endif +#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4 +#define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4) +#if defined(CONFIG_MX51) +#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6 +#define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8 +#define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8) +#elif defined(CONFIG_MX53) +#define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8 +#define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8) +#endif +#define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10 +#define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12 +#define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR6_GPU2D_OFFSET 14 +#define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14) +#if defined(CONFIG_MX53) +#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16 +#define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16) +#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18 +#define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18) +#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20 +#define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20) +#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22 +#define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22) +#define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24 +#define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24) +#define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26 +#define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26) +#define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28 +#define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28) +#define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30 +#define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30) + +#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0 +#define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0) +#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2 +#define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2) +#define MXC_CCM_CCGR7_MLB_OFFSET 4 +#define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4) +#define MXC_CCM_CCGR7_IEEE1588_OFFSET 6 +#define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6) +#define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8 +#define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8) +#define MXC_CCM_CCGR7_UART4_PER_OFFSET 10 +#define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10) +#define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12 +#define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12) +#define MXC_CCM_CCGR7_UART5_PER_OFFSET 14 +#define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14) +#endif /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) @@ -213,8 +610,10 @@ struct mxc_ccm_reg { #define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) #define MXC_DPLLC_OP_PDF_MASK 0xf -#define MXC_DPLLC_OP_MFI_MASK (0xf << 4) #define MXC_DPLLC_OP_MFI_OFFSET 4 +#define MXC_DPLLC_OP_MFI_MASK (0xf << 4) +#define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4) +#define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf) #define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index d1ef15d..46017f4 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -321,6 +321,8 @@ #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 +#define BOARD_VER_OFFSET 0x8 + #define IMX_IIM_BASE (IIM_BASE_ADDR) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index c55c18d..db377cc 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -24,6 +24,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include <common.h> + +#ifdef CONFIG_SYS_MX6_HCLK +#define MXC_HCLK CONFIG_SYS_MX6_HCLK +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_SYS_MX6_CLK32 +#define MXC_CLK32 CONFIG_SYS_MX6_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_ARM_CLK = 0, MXC_PER_CLK, @@ -41,6 +55,7 @@ enum mxc_clock { MXC_ESDHC4_CLK, MXC_SATA_CLK, MXC_NFC_CLK, + MXC_I2C_CLK, }; u32 imx_get_uartclk(void); diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 0e605c2..d670f30 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -34,7 +34,7 @@ struct mxc_ccm_reg { u32 cs1cdr; u32 cs2cdr; u32 cdcdr; /* 0x0030 */ - u32 chscdr; + u32 chsccdr; u32 cscdr2; u32 cscdr3; u32 cscdr4; /* 0x0040 */ @@ -294,6 +294,10 @@ struct mxc_ccm_reg { #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 +#define CHSCCDR_CLK_SEL_LDB_DI0 3 +#define CHSCCDR_PODF_DIVIDE_BY_3 2 +#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 + /* Define the bits in register CSCDR2 */ #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 @@ -395,185 +399,185 @@ struct mxc_ccm_reg { /* Define the bits in registers CCGRx */ #define MXC_CCM_CCGR_CG_MASK 3 -#define MXC_CCM_CCGR0_CG15_OFFSET 30 -#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) -#define MXC_CCM_CCGR0_CG14_OFFSET 28 -#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) -#define MXC_CCM_CCGR0_CG13_OFFSET 26 -#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) -#define MXC_CCM_CCGR0_CG12_OFFSET 24 -#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) -#define MXC_CCM_CCGR0_CG11_OFFSET 22 -#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22) -#define MXC_CCM_CCGR0_CG10_OFFSET 20 -#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20) -#define MXC_CCM_CCGR0_CG9_OFFSET 18 -#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18) -#define MXC_CCM_CCGR0_CG8_OFFSET 16 -#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16) -#define MXC_CCM_CCGR0_CG7_OFFSET 14 -#define MXC_CCM_CCGR0_CG6_OFFSET 12 -#define MXC_CCM_CCGR0_CG5_OFFSET 10 -#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10) -#define MXC_CCM_CCGR0_CG4_OFFSET 8 -#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8) -#define MXC_CCM_CCGR0_CG3_OFFSET 6 -#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6) -#define MXC_CCM_CCGR0_CG2_OFFSET 4 -#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) -#define MXC_CCM_CCGR0_CG1_OFFSET 2 -#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) -#define MXC_CCM_CCGR0_CG0_OFFSET 0 -#define MXC_CCM_CCGR0_CG0_MASK 3 - -#define MXC_CCM_CCGR1_CG15_OFFSET 30 -#define MXC_CCM_CCGR1_CG14_OFFSET 28 -#define MXC_CCM_CCGR1_CG13_OFFSET 26 -#define MXC_CCM_CCGR1_CG12_OFFSET 24 -#define MXC_CCM_CCGR1_CG11_OFFSET 22 -#define MXC_CCM_CCGR1_CG10_OFFSET 20 -#define MXC_CCM_CCGR1_CG9_OFFSET 18 -#define MXC_CCM_CCGR1_CG8_OFFSET 16 -#define MXC_CCM_CCGR1_CG7_OFFSET 14 -#define MXC_CCM_CCGR1_CG6_OFFSET 12 -#define MXC_CCM_CCGR1_CG5_OFFSET 10 -#define MXC_CCM_CCGR1_CG4_OFFSET 8 -#define MXC_CCM_CCGR1_CG3_OFFSET 6 -#define MXC_CCM_CCGR1_CG2_OFFSET 4 -#define MXC_CCM_CCGR1_CG1_OFFSET 2 -#define MXC_CCM_CCGR1_CG0_OFFSET 0 - -#define MXC_CCM_CCGR2_CG15_OFFSET 30 -#define MXC_CCM_CCGR2_CG14_OFFSET 28 -#define MXC_CCM_CCGR2_CG13_OFFSET 26 -#define MXC_CCM_CCGR2_CG12_OFFSET 24 -#define MXC_CCM_CCGR2_CG11_OFFSET 22 -#define MXC_CCM_CCGR2_CG10_OFFSET 20 -#define MXC_CCM_CCGR2_CG9_OFFSET 18 -#define MXC_CCM_CCGR2_CG8_OFFSET 16 -#define MXC_CCM_CCGR2_CG7_OFFSET 14 -#define MXC_CCM_CCGR2_CG6_OFFSET 12 -#define MXC_CCM_CCGR2_CG5_OFFSET 10 -#define MXC_CCM_CCGR2_CG4_OFFSET 8 -#define MXC_CCM_CCGR2_CG3_OFFSET 6 -#define MXC_CCM_CCGR2_CG2_OFFSET 4 -#define MXC_CCM_CCGR2_CG1_OFFSET 2 -#define MXC_CCM_CCGR2_CG0_OFFSET 0 - -#define MXC_CCM_CCGR3_CG15_OFFSET 30 -#define MXC_CCM_CCGR3_CG14_OFFSET 28 -#define MXC_CCM_CCGR3_CG13_OFFSET 26 -#define MXC_CCM_CCGR3_CG12_OFFSET 24 -#define MXC_CCM_CCGR3_CG11_OFFSET 22 -#define MXC_CCM_CCGR3_CG10_OFFSET 20 -#define MXC_CCM_CCGR3_CG9_OFFSET 18 -#define MXC_CCM_CCGR3_CG8_OFFSET 16 -#define MXC_CCM_CCGR3_CG7_OFFSET 14 -#define MXC_CCM_CCGR3_CG6_OFFSET 12 -#define MXC_CCM_CCGR3_CG5_OFFSET 10 -#define MXC_CCM_CCGR3_CG4_OFFSET 8 -#define MXC_CCM_CCGR3_CG3_OFFSET 6 -#define MXC_CCM_CCGR3_CG2_OFFSET 4 -#define MXC_CCM_CCGR3_CG1_OFFSET 2 -#define MXC_CCM_CCGR3_CG0_OFFSET 0 - -#define MXC_CCM_CCGR4_CG15_OFFSET 30 -#define MXC_CCM_CCGR4_CG14_OFFSET 28 -#define MXC_CCM_CCGR4_CG13_OFFSET 26 -#define MXC_CCM_CCGR4_CG12_OFFSET 24 -#define MXC_CCM_CCGR4_CG11_OFFSET 22 -#define MXC_CCM_CCGR4_CG10_OFFSET 20 -#define MXC_CCM_CCGR4_CG9_OFFSET 18 -#define MXC_CCM_CCGR4_CG8_OFFSET 16 -#define MXC_CCM_CCGR4_CG7_OFFSET 14 -#define MXC_CCM_CCGR4_CG6_OFFSET 12 -#define MXC_CCM_CCGR4_CG5_OFFSET 10 -#define MXC_CCM_CCGR4_CG4_OFFSET 8 -#define MXC_CCM_CCGR4_CG3_OFFSET 6 -#define MXC_CCM_CCGR4_CG2_OFFSET 4 -#define MXC_CCM_CCGR4_CG1_OFFSET 2 -#define MXC_CCM_CCGR4_CG0_OFFSET 0 - -#define MXC_CCM_CCGR5_CG15_OFFSET 30 -#define MXC_CCM_CCGR5_CG14_OFFSET 28 -#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) -#define MXC_CCM_CCGR5_CG13_OFFSET 26 -#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) -#define MXC_CCM_CCGR5_CG12_OFFSET 24 -#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) -#define MXC_CCM_CCGR5_CG11_OFFSET 22 -#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) -#define MXC_CCM_CCGR5_CG10_OFFSET 20 -#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20) -#define MXC_CCM_CCGR5_CG9_OFFSET 18 -#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18) -#define MXC_CCM_CCGR5_CG8_OFFSET 16 -#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16) -#define MXC_CCM_CCGR5_CG7_OFFSET 14 -#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) -#define MXC_CCM_CCGR5_CG6_OFFSET 12 -#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12) -#define MXC_CCM_CCGR5_CG5_OFFSET 10 -#define MXC_CCM_CCGR5_CG4_OFFSET 8 -#define MXC_CCM_CCGR5_CG3_OFFSET 6 -#define MXC_CCM_CCGR5_CG2_OFFSET 4 -#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) -#define MXC_CCM_CCGR5_CG1_OFFSET 2 -#define MXC_CCM_CCGR5_CG0_OFFSET 0 - -#define MXC_CCM_CCGR6_CG15_OFFSET 30 -#define MXC_CCM_CCGR6_CG14_OFFSET 28 -#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28) -#define MXC_CCM_CCGR6_CG13_OFFSET 26 -#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26) -#define MXC_CCM_CCGR6_CG12_OFFSET 24 -#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24) -#define MXC_CCM_CCGR6_CG11_OFFSET 22 -#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22) -#define MXC_CCM_CCGR6_CG10_OFFSET 20 -#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20) -#define MXC_CCM_CCGR6_CG9_OFFSET 18 -#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18) -#define MXC_CCM_CCGR6_CG8_OFFSET 16 -#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16) -#define MXC_CCM_CCGR6_CG7_OFFSET 14 -#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14) -#define MXC_CCM_CCGR6_CG6_OFFSET 12 -#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12) -#define MXC_CCM_CCGR6_CG5_OFFSET 10 -#define MXC_CCM_CCGR6_CG4_OFFSET 8 -#define MXC_CCM_CCGR6_CG3_OFFSET 6 -#define MXC_CCM_CCGR6_CG2_OFFSET 4 -#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4) -#define MXC_CCM_CCGR6_CG1_OFFSET 2 -#define MXC_CCM_CCGR6_CG0_OFFSET 0 - -#define MXC_CCM_CCGR7_CG15_OFFSET 30 -#define MXC_CCM_CCGR7_CG14_OFFSET 28 -#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28) -#define MXC_CCM_CCGR7_CG13_OFFSET 26 -#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26) -#define MXC_CCM_CCGR7_CG12_OFFSET 24 -#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24) -#define MXC_CCM_CCGR7_CG11_OFFSET 22 -#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22) -#define MXC_CCM_CCGR7_CG10_OFFSET 20 -#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20) -#define MXC_CCM_CCGR7_CG9_OFFSET 18 -#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18) -#define MXC_CCM_CCGR7_CG8_OFFSET 16 -#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16) -#define MXC_CCM_CCGR7_CG7_OFFSET 14 -#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14) -#define MXC_CCM_CCGR7_CG6_OFFSET 12 -#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12) -#define MXC_CCM_CCGR7_CG5_OFFSET 10 -#define MXC_CCM_CCGR7_CG4_OFFSET 8 -#define MXC_CCM_CCGR7_CG3_OFFSET 6 -#define MXC_CCM_CCGR7_CG2_OFFSET 4 -#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4) -#define MXC_CCM_CCGR7_CG1_OFFSET 2 -#define MXC_CCM_CCGR7_CG0_OFFSET 0 +#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 +#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) +#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 +#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) +#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4 +#define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA) +#define MXC_CCM_CCGR0_ASRC_OFFSET 6 +#define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET) +#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 +#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) +#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 +#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) +#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 +#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) +#define MXC_CCM_CCGR0_CAN1_OFFSET 14 +#define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET) +#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 +#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) +#define MXC_CCM_CCGR0_CAN2_OFFSET 18 +#define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET) +#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 +#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) +#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 +#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) +#define MXC_CCM_CCGR0_DCIC1_OFFSET 24 +#define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET) +#define MXC_CCM_CCGR0_DCIC2_OFFSET 26 +#define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET) +#define MXC_CCM_CCGR0_DTCP_OFFSET 28 +#define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET) + +#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 +#define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 +#define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 +#define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 +#define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 +#define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET) +#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 +#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) +#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 +#define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET) +#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 +#define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET) +#define MXC_CCM_CCGR1_ESAIS_OFFSET 16 +#define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET) +#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 +#define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET) +#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 +#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) +#define MXC_CCM_CCGR1_GPU2D_OFFSET 24 +#define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET) +#define MXC_CCM_CCGR1_GPU3D_OFFSET 26 +#define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET) + +#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 +#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) +#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 +#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) +#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 +#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) +#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 +#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) +#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 +#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) +#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 +#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) +#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 +#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) +#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 +#define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET) +#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 +#define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET) +#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 +#define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET) +#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 +#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) +#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 +#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) +#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 +#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) + +#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 +#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET) +#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 +#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) +#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 +#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) +#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 +#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET) +#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 +#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) +#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 +#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) +#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 +#define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET) +#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 +#define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET) +#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 +#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) +#define MXC_CCM_CCGR3_MLB_OFFSET 18 +#define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET) +#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 +#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) +#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 +#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) +#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 +#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) +#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 +#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) +#define MXC_CCM_CCGR3_OCRAM_OFFSET 28 +#define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET) +#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 +#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) + +#define MXC_CCM_CCGR4_PCIE_OFFSET 0 +#define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET) +#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 +#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) +#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 +#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) +#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 +#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) +#define MXC_CCM_CCGR4_PWM1_OFFSET 16 +#define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET) +#define MXC_CCM_CCGR4_PWM2_OFFSET 18 +#define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET) +#define MXC_CCM_CCGR4_PWM3_OFFSET 20 +#define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET) +#define MXC_CCM_CCGR4_PWM4_OFFSET 22 +#define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 +#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) + +#define MXC_CCM_CCGR5_ROM_OFFSET 0 +#define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET) +#define MXC_CCM_CCGR5_SATA_OFFSET 4 +#define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET) +#define MXC_CCM_CCGR5_SDMA_OFFSET 6 +#define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET) +#define MXC_CCM_CCGR5_SPBA_OFFSET 12 +#define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET) +#define MXC_CCM_CCGR5_SPDIF_OFFSET 14 +#define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET) +#define MXC_CCM_CCGR5_SSI1_OFFSET 18 +#define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET) +#define MXC_CCM_CCGR5_SSI2_OFFSET 20 +#define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET) +#define MXC_CCM_CCGR5_SSI3_OFFSET 22 +#define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET) +#define MXC_CCM_CCGR5_UART_OFFSET 24 +#define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET) +#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 +#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET) + +#define MXC_CCM_CCGR6_USBOH3_OFFSET 0 +#define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET) +#define MXC_CCM_CCGR6_USDHC1_OFFSET 2 +#define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET) +#define MXC_CCM_CCGR6_USDHC2_OFFSET 4 +#define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET) +#define MXC_CCM_CCGR6_USDHC3_OFFSET 6 +#define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET) +#define MXC_CCM_CCGR6_USDHC4_OFFSET 8 +#define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET) +#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 +#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET) +#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 +#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET) + #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 #define BP_ANADIG_PLL_SYS_RSVD0 20 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 8834c59..dc737ba 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -200,6 +200,127 @@ struct src { u32 gpr10; }; +/* GPR3 bitfields */ +#define IOMUXC_GPR3_GPU_DBG_OFFSET 29 +#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) +#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 +#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 +#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 +#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 +#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 +#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) +#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 +#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) +#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 +#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 +#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 +#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 +#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 +#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) +#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 +#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) +#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 +#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) + +#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 +#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 +#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 +#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 + +#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 +#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) + +#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 +#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) + +#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 +#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) + +#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 +#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) + + +struct iomuxc { + u32 gpr[14]; + u32 omux[5]; + /* mux and pad registers */ +}; + +#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 +#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) +#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 +#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) + +#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 +#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) +#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) +#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) +#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 +#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 + +#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 +#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) +#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) +#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) + +#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 +#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) +#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) +#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) + +#define IOMUXC_GPR2_BITMAP_SPWG 0 +#define IOMUXC_GPR2_BITMAP_JEIDA 1 + +#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 +#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) +#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) +#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) + +#define IOMUXC_GPR2_DATA_WIDTH_18 0 +#define IOMUXC_GPR2_DATA_WIDTH_24 1 + +#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 +#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) +#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) +#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) + +#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 +#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) +#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) +#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) + +#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 +#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) +#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) +#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) + +#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 +#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) + +#define IOMUXC_GPR2_MODE_DISABLED 0 +#define IOMUXC_GPR2_MODE_ENABLED_DI0 1 +#define IOMUXC_GPR2_MODE_ENABLED_DI1 2 + +#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 +#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) + +#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 +#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) + /* ECSPI registers */ struct cspi_regs { u32 rxdata; @@ -439,6 +560,30 @@ struct anatop_regs { u32 digprog; /* 0x260 */ }; +#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 +#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6 +#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7 +#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT) +#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8 +#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14 +#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15 +#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT) +#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16 +#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22 +#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23 +#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT) +#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24 +#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30 +#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31 + struct iomuxc_base_regs { u32 gpr[14]; /* 0x000 */ u32 obsrv[5]; /* 0x038 */ @@ -448,26 +593,5 @@ struct iomuxc_base_regs { u32 daisy[104]; /* 0x7b0..94c */ }; -struct src_regs { - u32 scr; /* 0x00 */ - u32 sbmr1; /* 0x04 */ - u32 srsr; /* 0x08 */ - u32 reserved1; /* 0x0c */ - u32 reserved2; /* 0x10 */ - u32 sisr; /* 0x14 */ - u32 simr; /* 0x18 */ - u32 sbmr2; /* 0x1c */ - u32 gpr1; /* 0x20 */ - u32 gpr2; /* 0x24 */ - u32 gpr3; /* 0x28 */ - u32 gpr4; /* 0x2c */ - u32 gpr5; /* 0x30 */ - u32 gpr6; /* 0x34 */ - u32 gpr7; /* 0x38 */ - u32 gpr8; /* 0x3c */ - u32 gpr9; /* 0x40 */ - u32 gpr10; /* 0x44 */ -}; - #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index 2f52ca8..17b9b69 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -251,7 +251,6 @@ struct orion5x_ddr_addr_decode_registers { /* * functions */ -void reset_cpu(unsigned long ignored); u32 orion5x_device_id(void); u32 orion5x_device_rev(void); unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); diff --git a/arch/arm/include/asm/arch-pxa/pxa.h b/arch/arm/include/asm/arch-pxa/pxa.h index 49c6552..b67d8f2 100644 --- a/arch/arm/include/asm/arch-pxa/pxa.h +++ b/arch/arm/include/asm/arch-pxa/pxa.h @@ -22,8 +22,21 @@ #ifndef __PXA_H__ #define __PXA_H__ +#define PXA255_A0 0x00000106 +#define PXA250_C0 0x00000105 +#define PXA250_B2 0x00000104 +#define PXA250_B1 0x00000103 +#define PXA250_B0 0x00000102 +#define PXA250_A1 0x00000101 +#define PXA250_A0 0x00000100 +#define PXA210_C0 0x00000125 +#define PXA210_B2 0x00000124 +#define PXA210_B1 0x00000123 +#define PXA210_B0 0x00000122 + int cpu_is_pxa25x(void); int cpu_is_pxa27x(void); +uint32_t pxa_get_cpu_revision(void); void pxa2xx_dram_init(void); #endif /* __PXA_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h new file mode 100644 index 0000000..6b5e4ed --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/gpio.h @@ -0,0 +1,12 @@ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#if defined(CONFIG_SH73A0) +#include "sh73a0-gpio.h" +void sh73a0_pinmux_init(void); +#elif defined(CONFIG_R8A7740) +#include "r8a7740-gpio.h" +void r8a7740_pinmux_init(void); +#endif + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/include/asm/arch-rmobile/irqs.h b/arch/arm/include/asm/arch-rmobile/irqs.h new file mode 100644 index 0000000..dcb714f --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/irqs.h @@ -0,0 +1,18 @@ +#ifndef __ASM_MACH_IRQS_H +#define __ASM_MACH_IRQS_H + +#define NR_IRQS 1024 + +/* GIC */ +#define gic_spi(nr) ((nr) + 32) + +/* INTCA */ +#define evt2irq(evt) (((evt) >> 5) - 16) +#define irq2evt(irq) (((irq) + 16) << 5) + +/* INTCS */ +#define INTCS_VECT_BASE 0x2200 +#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) +#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) + +#endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h new file mode 100644 index 0000000..9d447ab --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h @@ -0,0 +1,584 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ASM_R8A7740_H__ +#define __ASM_R8A7740_H__ + +/* + * MD_CKx pin + */ +#define MD_CK2 (1 << 2) +#define MD_CK1 (1 << 1) +#define MD_CK0 (1 << 0) + +/* + * Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* PORT */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, + + GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, + GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, + + GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, + GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, + + GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, + GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, + + GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, + + /* IRQ */ + GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13, + GPIO_FN_IRQ1, + GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12, + GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14, + GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172, + GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1, + GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173, + GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209, + GPIO_FN_IRQ8, + GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210, + GPIO_FN_IRQ10, + GPIO_FN_IRQ11, + GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97, + GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98, + GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99, + GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100, + GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211, + GPIO_FN_IRQ17, + GPIO_FN_IRQ18, + GPIO_FN_IRQ19, + GPIO_FN_IRQ20, + GPIO_FN_IRQ21, + GPIO_FN_IRQ22, + GPIO_FN_IRQ23, + GPIO_FN_IRQ24, + GPIO_FN_IRQ25, + GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81, + GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168, + GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169, + GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170, + GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171, + GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167, + + /* Function */ + + /* DBGT */ + GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0, + GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20, + GPIO_FN_DBGMD21, + + /* FSI */ + GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */ + GPIO_FN_FSIAISLD_PORT5, + GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */ + GPIO_FN_FSIASPDIF_PORT18, + GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2, + GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, + GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC, + GPIO_FN_FSIACK, GPIO_FN_FSIAILR, + GPIO_FN_FSIAIBT, + + /* FMSI */ + GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */ + GPIO_FN_FMSISLD_PORT6, + GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT, + GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT, + GPIO_FN_FMSICK, GPIO_FN_FMSOILR, + GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR, + GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD, + GPIO_FN_FMSOCK, + + /* SCIFA0 */ + GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS, + GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_TXD, + + /* SCIFA1 */ + GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK, + GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD, + GPIO_FN_SCIFA1_RTS, + + /* SCIFA2 */ + GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */ + GPIO_FN_SCIFA2_SCK_PORT199, + GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD, + GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS, + + /* SCIFA3 */ + GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */ + GPIO_FN_SCIFA3_SCK_PORT116, + GPIO_FN_SCIFA3_CTS_PORT117, + GPIO_FN_SCIFA3_RXD_PORT174, + GPIO_FN_SCIFA3_TXD_PORT175, + + GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */ + GPIO_FN_SCIFA3_SCK_PORT158, + GPIO_FN_SCIFA3_CTS_PORT162, + GPIO_FN_SCIFA3_RXD_PORT159, + GPIO_FN_SCIFA3_TXD_PORT160, + + /* SCIFA4 */ + GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */ + GPIO_FN_SCIFA4_TXD_PORT13, + + GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */ + GPIO_FN_SCIFA4_TXD_PORT203, + + GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */ + GPIO_FN_SCIFA4_TXD_PORT93, + + GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */ + GPIO_FN_SCIFA4_SCK_PORT205, + + /* SCIFA5 */ + GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */ + GPIO_FN_SCIFA5_RXD_PORT10, + + GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */ + GPIO_FN_SCIFA5_TXD_PORT208, + + GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */ + GPIO_FN_SCIFA5_RXD_PORT92, + + GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */ + GPIO_FN_SCIFA5_SCK_PORT206, + + /* SCIFA6 */ + GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD, + + /* SCIFA7 */ + GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD, + + /* SCIFAB */ + GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */ + GPIO_FN_SCIFB_RXD_PORT191, + GPIO_FN_SCIFB_TXD_PORT192, + GPIO_FN_SCIFB_RTS_PORT186, + GPIO_FN_SCIFB_CTS_PORT187, + + GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */ + GPIO_FN_SCIFB_RXD_PORT3, + GPIO_FN_SCIFB_TXD_PORT4, + GPIO_FN_SCIFB_RTS_PORT172, + GPIO_FN_SCIFB_CTS_PORT173, + + /* LCD0 */ + GPIO_FN_LCDC0_SELECT, + GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2, + GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5, + GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8, + GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11, + GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14, + GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17, + GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC, + + GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */ + GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */ + + GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */ + GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */ + + GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162, + GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158, + GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159, + GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */ + + GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4, + GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2, + GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1, + GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */ + + /* LCD1 */ + GPIO_FN_LCDC1_SELECT, + GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2, + GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5, + GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8, + GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11, + GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14, + GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17, + GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20, + GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23, + GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC, + GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC, + + GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */ + GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */ + + GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */ + GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */ + + /* RSPI */ + GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, + GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A, + GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A, + GPIO_FN_RSPI_CK_A, + + /* VIO CKO */ + GPIO_FN_VIO_CKO1, + GPIO_FN_VIO_CKO2, + GPIO_FN_VIO_CKO_1, + GPIO_FN_VIO_CKO, + + /* VIO0 */ + GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2, + GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5, + GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8, + GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11, + GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD, + GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD, + + GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */ + GPIO_FN_VIO0_D14_PORT25, + GPIO_FN_VIO0_D15_PORT24, + + GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */ + GPIO_FN_VIO0_D14_PORT95, + GPIO_FN_VIO0_D15_PORT96, + + /* VIO1 */ + GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2, + GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5, + GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD, + GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD, + + /* TPU0 */ + GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, + GPIO_FN_TPU0TO3, + GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */ + GPIO_FN_TPU0TO2_PORT202, + + /* SSP1 0 */ + GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2, + GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5, + GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN, + GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC, + + /* SSP1 1 */ + GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3, + GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6, + GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC, + + GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */ + GPIO_FN_STP1_IPEN_PORT187, + + GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */ + GPIO_FN_STP1_IPEN_PORT193, + + /* SIM */ + GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, + GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ + GPIO_FN_SIM_D_PORT199, + + /* SDHI0 */ + GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2, + GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP, + GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK, + + /* SDHI1 */ + GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2, + GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP, + GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK, + + /* SDHI2 */ + GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2, + GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD, + + GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */ + GPIO_FN_SDHI2_WP_PORT25, + + GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */ + GPIO_FN_SDHI2_CD_PORT202, + + /* MSIOF2 */ + GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, + GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, + GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_MSIOF2_RSCK, + + /* KEYSC */ + GPIO_FN_KEYIN4, GPIO_FN_KEYIN5, + GPIO_FN_KEYIN6, GPIO_FN_KEYIN7, + GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, + GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5, + GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7, + + GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */ + GPIO_FN_KEYIN1_PORT44, + GPIO_FN_KEYIN2_PORT45, + GPIO_FN_KEYIN3_PORT46, + + GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */ + GPIO_FN_KEYIN1_PORT57, + GPIO_FN_KEYIN2_PORT56, + GPIO_FN_KEYIN3_PORT55, + + /* VOU */ + GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3, + GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7, + GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11, + GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15, + GPIO_FN_DV_CLK, + GPIO_FN_DV_VSYNC, + GPIO_FN_DV_HSYNC, + + /* MEMC */ + GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, + GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, + GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, + GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, + GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, + GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT, + GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE, + + GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */ + GPIO_FN_MEMC_ADV, + GPIO_FN_MEMC_WAIT, + GPIO_FN_MEMC_BUSCLK, + + GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */ + GPIO_FN_MEMC_DREQ0, + GPIO_FN_MEMC_DREQ1, + GPIO_FN_MEMC_A0, + + /* MMC */ + GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69, + GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71, + GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73, + GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75, + GPIO_FN_MMC0_CLK_PORT66, + GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */ + + GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148, + GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146, + GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144, + GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142, + GPIO_FN_MMC1_CLK_PORT103, + GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */ + + /* MSIOF0 */ + GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, + GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, + GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC, + + /* MSIOF1 */ + GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, + + GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117, + GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119, + GPIO_FN_MSIOF1_TSYNC_PORT120, + GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */ + + GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72, + GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74, + GPIO_FN_MSIOF1_RXD_PORT75, + GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */ + + /* GPIO */ + GPIO_FN_GPO0, GPIO_FN_GPI0, + GPIO_FN_GPO1, GPIO_FN_GPI1, + + /* USB0 */ + GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS, + + /* USB1 */ + GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON, + + /* BBIF1 */ + GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, + GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N, + + /* BBIF2 */ + GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */ + GPIO_FN_BBIF2_RXD2_PORT60, + GPIO_FN_BBIF2_TSYNC2_PORT6, + GPIO_FN_BBIF2_TSCK2_PORT59, + + GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */ + GPIO_FN_BBIF2_TXD2_PORT183, + GPIO_FN_BBIF2_TSCK2_PORT89, + GPIO_FN_BBIF2_TSYNC2_PORT184, + + /* BSC / FLCTL / PCMCIA */ + GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, + GPIO_FN_CS5B, GPIO_FN_CS6A, + GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */ + GPIO_FN_CS5A_PORT19, + GPIO_FN_IOIS16, /* ? */ + + GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, + GPIO_FN_A4_FOE, /* share with FLCTL */ + GPIO_FN_A5_FCDE, /* share with FLCTL */ + GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, + GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, + GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, + GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, + GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, + GPIO_FN_A26, + + GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */ + GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */ + GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */ + GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */ + GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */ + GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */ + GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */ + GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */ + + GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19, + GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23, + GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27, + GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31, + + GPIO_FN_WE0_FWE, /* share with FLCTL */ + GPIO_FN_WE1, + GPIO_FN_WE2_ICIORD, /* share with PCMCIA */ + GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */ + GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR, + GPIO_FN_RD_FSC, /* share with FLCTL */ + GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */ + GPIO_FN_WAIT_PORT90, + + GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */ + + /* IRDA */ + GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, + + /* ATAPI */ + GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2, + GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5, + GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8, + GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11, + GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14, + GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1, + GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1, + GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY, + GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION, + GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ, + + /* RMII */ + GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0, + GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0, + GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO, + GPIO_FN_RMII_REF50CK, /* for RMII */ + GPIO_FN_RMII_REF125CK, /* for GMII */ + + /* GEther */ + GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0, + GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3, + GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */ + GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */ + GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER, + GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV, + GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1, + GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3, + GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */ + GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */ + GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS, + GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO, + GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT, + GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK, + + /* DMA0 */ + GPIO_FN_DREQ0, GPIO_FN_DACK0, + + /* DMA1 */ + GPIO_FN_DREQ1, GPIO_FN_DACK1, + + /* SYSC */ + GPIO_FN_RESETOUTS, + GPIO_FN_RESETP_PULLUP, + GPIO_FN_RESETP_PLAIN, + + /* SDENC */ + GPIO_FN_SDENC_CPG, + GPIO_FN_SDENC_DV_CLKI, + + /* IRREM */ + GPIO_FN_IROUT, + + /* DEBUG */ + GPIO_FN_EDEBGREQ_PULLDOWN, + GPIO_FN_EDEBGREQ_PULLUP, + + GPIO_FN_TRACEAUD_FROM_VIO, + GPIO_FN_TRACEAUD_FROM_LCDC0, + GPIO_FN_TRACEAUD_FROM_MEMC, +}; + +#endif /* __ASM_R8A7740_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740.h b/arch/arm/include/asm/arch-rmobile/r8a7740.h new file mode 100644 index 0000000..8f17950 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7740.h @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_R8A7740_H +#define __ASM_ARCH_R8A7740_H + +/* + * R8A7740 I/O Addresses + */ + +#define MERAM_BASE 0xE5580000 +#define DDRP_BASE 0xC12A0000 +#define HPB_BASE 0xE6000000 +#define RWDT0_BASE 0xE6020000 +#define RWDT1_BASE 0xE6030000 +#define GPIO_BASE 0xE6050000 +#define CMT1_BASE 0xE6138000 +#define CPG_BASE 0xE6150000 +#define SYSC_BASE 0xE6180000 +#define SDHI0_BASE 0xE6850000 +#define SDHI1_BASE 0xE6860000 +#define MMCIF_BASE 0xE6BD0000 +#define SCIF5_BASE 0xE6CB0000 +#define SCIF6_BASE 0xE6CC0000 +#define DBSC_BASE 0xFE400000 +#define BSC_BASE 0xFEC10000 +#define I2C0_BASE 0xFFF20000 +#define I2C1_BASE 0xE6C20000 +#define TMU_BASE 0xFFF80000 + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct r8a7740_rwdt { + u16 rwtcnt0; /* 0x00 */ + u16 dummy0; /* 0x02 */ + u16 rwtcsra0; /* 0x04 */ + u16 dummy1; /* 0x06 */ + u16 rwtcsrb0; /* 0x08 */ + u16 dummy2; /* 0x0A */ +}; + +/* HPB Semaphore Control Registers */ +struct r8a7740_hpb { + u32 hpbctrl0; + u32 hpbctrl1; + u32 hpbctrl2; + u32 cccr; + u32 dummy0; /* 0x20 */ + u32 hpbctrl4; + u32 hpbctrl5; +}; + +/* CPG */ +struct r8a7740_cpg { + u32 frqcra; + u32 frqcrb; + u32 vclkcr1; + u32 vclkcr2; + u32 fmsickcr; + u32 fmsockcr; + u32 fsiackcr; + u32 dummy0; /* 0x1c */ + u32 rtstbcr; + u32 systbcr; + u32 pllc01cr; + u32 pllc2cr; + u32 mstpsr0; + u32 dummy1; /* 0x34 */ + u32 mstpsr1; + u32 mstpsr5; + u32 mstpsr2; + u32 dummy2; /* 0x44 */ + u32 mstpsr3; + u32 mstpsr4; + u32 dummy3; /* 0x50 */ + u32 astat; + u32 dummy4[4]; /* 0x58 .. 0x64 */ + u32 ztrckcr; + u32 dummy5[5]; /* 0x6c .. 0x7c */ + u32 subckcr; + u32 spuckcr; + u32 vouckcr; + u32 usbckcr; + u32 dummy6[3]; /* 0x90 .. 0x98 */ + u32 stprckcr; + u32 srcr0; + u32 dummy7; /* 0xa4 */ + u32 srcr1; + u32 dummy8; /* 0xac */ + u32 srcr2; + u32 dummy9; /* 0xb4 */ + u32 srcr3; + u32 srcr4; + u32 dummy10; /* 0xc0 */ + u32 srcr5; + u32 pllc01stpcr; + u32 dummy11[5]; /* 0xcc .. 0xdc */ + u32 frqcrc; + u32 frqcrd; + u32 dummy12[10]; /* 0xe8 .. 0x10c */ + u32 rmstpcr0; + u32 rmstpcr1; + u32 rmstpcr2; + u32 rmstpcr3; + u32 rmstpcr4; + u32 rmstpcr5; + u32 dummy13[2]; /* 0x128 .. 0x12c */ + u32 smstpcr0; + u32 smstpcr1; + u32 smstpcr2; + u32 smstpcr3; + u32 smstpcr4; + u32 smstpcr5; +}; + +/* BSC */ +struct r8a7740_bsc { + u32 cmncr; + u32 cs0bcr; + u32 cs2bcr; + u32 dummy0; /* 0x0c */ + u32 cs4bcr; + u32 cs5abcr; + u32 cs5bbcr; + u32 cs6abcr; + u32 dummy1; /* 0x20 */ + u32 cs0wcr; + u32 cs2wcr; + u32 dummy2; /* 0x2c */ + u32 cs4wcr; + u32 cs5awcr; + u32 cs5bwcr; + u32 cs6awcr; + u32 dummy3[5]; /* 0x40 .. 0x50 */ + u32 rbwtcnt; + u32 busycr; + u32 dummy4[5]; /* 0x5c .. 0x6c */ + u32 bromtimcr; + u32 dummy5[7]; /* 0x74 .. 0x8c */ + u32 bptcr00; + u32 bptcr01; + u32 bptcr02; + u32 bptcr03; + u32 bptcr04; + u32 bptcr05; + u32 bptcr06; + u32 bptcr07; + u32 bptcr08; + u32 bptcr09; + u32 bptcr10; + u32 bptcr11; + u32 bptcr12; + u32 bptcr13; + u32 bptcr14; + u32 bptcr15; + u32 bptcr16; + u32 bptcr17; + u32 bptcr18; + u32 bptcr19; + u32 bptcr20; + u32 bptcr21; + u32 bptcr22; + u32 bptcr23; + u32 bptcr24; + u32 bptcr25; + u32 bptcr26; + u32 bptcr27; + u32 bptcr28; + u32 bptcr29; + u32 bptcr30; + u32 bptcr31; + u32 bswcr; + u32 dummy6[68]; /* 0x114 .. 0x220 */ + u32 cs0wcr2; + u32 cs2wcr2; + u32 dummy7; /* 0x22c */ + u32 cs4wcr2; +}; + +#define CS0WCR2 0xFEC10224 +#define CS2WCR2 0xFEC10228 +#define CS4WCR2 0xFEC10230 + +/* DDRP */ +struct r8a7740_ddrp { + u32 funcctrl; + u32 dllctrl; + u32 zqcalctrl; + u32 zqodtctrl; + u32 rdctrl; + u32 rdtmg; + u32 fifoinit; + u32 outctrl; + u32 dummy0[50]; /* 0x20 .. 0xe4 */ + u32 dqcalofs1; + u32 dqcalofs2; + u32 dummy1[2]; /* 0xf0 .. 0xf4 */ + u32 dqcalexp; +}; + +#define DDRPNCNT 0xE605803C +#define DDRVREFCNT 0xE61500EC + +/* DBSC */ +struct r8a7740_dbsc { + u32 dummy0; + u32 dbsvcr; + u32 dbstate0; + u32 dbstate1; + u32 dbacen; + u32 dbrfen; + u32 dbcmd; + u32 dbwait; + u32 dbkind; + u32 dbconf0; + u32 dummy1[2]; /* 0x28 .. 0x2c */ + u32 dbphytype; + u32 dummy2[3]; /* 0x34 .. 0x3c */ + u32 dbtr0; + u32 dbtr1; + u32 dbtr2; + u32 dummy3; /* 0x4c */ + u32 dbtr3; + u32 dbtr4; + u32 dbtr5; + u32 dbtr6; + u32 dbtr7; + u32 dbtr8; + u32 dbtr9; + u32 dbtr10; + u32 dbtr11; + u32 dbtr12; + u32 dbtr13; + u32 dbtr14; + u32 dbtr15; + u32 dbtr16; + u32 dbtr17; + u32 dbtr18; + u32 dbtr19; + u32 dummy4[7]; /* 0x94 .. 0xac */ + u32 dbbl; + u32 dummy5[3]; /* 0xb4 .. 0xbc */ + u32 dbadj0; + u32 dbadj1; + u32 dbadj2; + u32 dummy6[5]; /* 0xcc .. 0xdc */ + u32 dbrfcnf0; + u32 dbrfcnf1; + u32 dbrfcnf2; + u32 dbrfcnf3; + u32 dummy7; /* 0xf0 */ + u32 dbcalcnf; + u32 dbcaltr; + u32 dummy8; /* 0xfc */; + u32 dbrnk0; + u32 dummy9[31]; /* 0x104 .. 0x17C */ + u32 dbpdncnf; + u32 dummy10[7]; /* 0x184 .. 0x19C */ + u32 dbmrrdr; + u32 dummy11[39]; /* 0x1A4 .. 0x23C */ + u32 dbdfistat; + u32 dbdficnt; + u32 dummy12[46]; /* 0x248 .. 0x2FC */ + u32 dbbs0cnt0; + u32 dbbs0cnt1; +}; + +#endif + +#endif /* __ASM_ARCH_R8A7740_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h new file mode 100644 index 0000000..ac17561 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/rmobile.h @@ -0,0 +1,14 @@ +#ifndef __ASM_ARCH_RMOBILE_H +#define __ASM_ARCH_RMOBILE_H + +#if defined(CONFIG_RMOBILE) +#if defined(CONFIG_SH73A0) +#include <asm/arch/sh73a0.h> +#elif defined(CONFIG_R8A7740) +#include <asm/arch/r8a7740.h> +#else +#error "SOC Name not defined" +#endif +#endif /* CONFIG_RMOBILE */ + +#endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h b/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h new file mode 100644 index 0000000..398e2c1 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h @@ -0,0 +1,553 @@ +#ifndef __ASM_SH73A0_H__ +#define __ASM_SH73A0_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function and MSEL switch + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* Hardware manual Table 25-1 (GPIO) */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, + + GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + + GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, + GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, + + GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, + GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, + + GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, + GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, + + GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, + GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, + + GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, + GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, + + GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, + GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, + + GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, + GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, + + GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, + + GPIO_PORT288, GPIO_PORT289, + + GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, + GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, + + GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, + GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, + + /* Table 25-1 (Function 0-7) */ + GPIO_FN_VBUS_0, + GPIO_FN_GPI0, + GPIO_FN_GPI1, + GPIO_FN_GPI2, + GPIO_FN_GPI3, + GPIO_FN_GPI4, + GPIO_FN_GPI5, + GPIO_FN_GPI6, + GPIO_FN_GPI7, + GPIO_FN_SCIFA7_RXD, + GPIO_FN_SCIFA7_CTS_, + GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, + GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, + GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ + GPIO_FN_PORT16_VIO_CKOR, + GPIO_FN_SCIFA0_TXD, + GPIO_FN_SCIFA7_TXD, + GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2, + GPIO_FN_GPO0, + GPIO_FN_GPO1, + GPIO_FN_GPO2, GPIO_FN_STATUS0, + GPIO_FN_GPO3, GPIO_FN_STATUS1, + GPIO_FN_GPO4, GPIO_FN_STATUS2, + GPIO_FN_VINT, + GPIO_FN_TCKON, + GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ + GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, + GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ + GPIO_FN_PORT28_TPU1TO1, + GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, + GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, + GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, + GPIO_FN_SCIFA4_TXD, + GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, + GPIO_FN_SCIFA4_RTS_, + GPIO_FN_SCIFA4_CTS_, + GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, + GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, + GPIO_FN_FSIBOSLD, + GPIO_FN_FSIBISLD, + GPIO_FN_VACK, + GPIO_FN_XTAL1L, + GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, + GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, + GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, + GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, + GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, + GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, + GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ + GPIO_FN_FSIAOMC, + GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR, + + GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT, + GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2, + GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \ + GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF, + GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \ + GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC, + GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0, + GPIO_FN_A0, GPIO_FN_BS_, + GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, + GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, + GPIO_FN_A14, GPIO_FN_KEYOUT5, + GPIO_FN_A15, GPIO_FN_KEYOUT4, + GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_KEYIN6, + GPIO_FN_KEYIN7, + GPIO_FN_D0_NAF0, + GPIO_FN_D1_NAF1, + GPIO_FN_D2_NAF2, + GPIO_FN_D3_NAF3, + GPIO_FN_D4_NAF4, + GPIO_FN_D5_NAF5, + GPIO_FN_D6_NAF6, + GPIO_FN_D7_NAF7, + GPIO_FN_D8_NAF8, + GPIO_FN_D9_NAF9, + GPIO_FN_D10_NAF10, + GPIO_FN_D11_NAF11, + GPIO_FN_D12_NAF12, + GPIO_FN_D13_NAF13, + GPIO_FN_D14_NAF14, + GPIO_FN_D15_NAF15, + GPIO_FN_CS4_, + GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR, + GPIO_FN_CS5B_, GPIO_FN_FCE1_, + GPIO_FN_CS6B_, GPIO_FN_DACK0, + GPIO_FN_FCE0_, GPIO_FN_CS6A_, + GPIO_FN_WAIT_, GPIO_FN_DREQ0, + GPIO_FN_RD__FSC, + GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE, + GPIO_FN_WE1_, + GPIO_FN_FRB, + GPIO_FN_CKO, + GPIO_FN_NBRSTOUT_, + GPIO_FN_NBRST_, + GPIO_FN_BBIF2_TXD, + GPIO_FN_BBIF2_RXD, + GPIO_FN_BBIF2_SYNC, + GPIO_FN_BBIF2_SCK, + GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, + GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, + GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, + GPIO_FN_SCIFA3_TXD, + GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, + GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, + GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, + GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ + GPIO_FN_PORT115_I2C_SCL3, + GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \ + GPIO_FN_PORT116_I2C_SDA3, + GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, + GPIO_FN_HSI_TX_FLAG, + GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ + GPIO_FN_LCD2D0, + + GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ + GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, + GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, + GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ + GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, + GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ + GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, + GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, + GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, + GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, + GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, + GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, + GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ + GPIO_FN_LCD2D6, + GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ + GPIO_FN_LCD2D7, + GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, + GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, + GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ + GPIO_FN_LCD2D2, + GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ + GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, + GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ + GPIO_FN_LCD2D4, + GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \ + GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5, + GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \ + GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18, + GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19, + GPIO_FN_VIO_CKO, + GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ + GPIO_FN_PORT149_KEYOUT9, + GPIO_FN_MFG0_IN2, + GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, + GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, + GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, + GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, + GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, + GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, + GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, + GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, + GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_, + GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, + GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ + GPIO_FN_TPU3TO0, + GPIO_FN_LCDD0, + GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, + GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, + GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD, + GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \ + GPIO_FN_TPU2TO1, + GPIO_FN_LCDD6, + GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, + GPIO_FN_LCDD8, GPIO_FN_D16, + GPIO_FN_LCDD9, GPIO_FN_D17, + GPIO_FN_LCDD10, GPIO_FN_D18, + GPIO_FN_LCDD11, GPIO_FN_D19, + GPIO_FN_LCDD12, GPIO_FN_D20, + GPIO_FN_LCDD13, GPIO_FN_D21, + GPIO_FN_LCDD14, GPIO_FN_D22, + GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, + GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, + GPIO_FN_LCDD17, GPIO_FN_D25, + GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, + GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, + GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, + GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, + GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, + GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, + GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ + GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP, + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \ + GPIO_FN_PORT218_VIO_CKOR, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \ + GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ + GPIO_FN_LCD2DCK_2, + GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, + GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \ + GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ + GPIO_FN_PORT221_LCD2HSYN, + GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ + GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, + + GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, + GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, + GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, + GPIO_FN_SCIFA1_RXD, + GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, + GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, + GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, + GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ + GPIO_FN_LCD2D20, + GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ + GPIO_FN_LCD2D21, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, + GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, + GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, + GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, + GPIO_FN_SCIFA6_TXD, + GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ + GPIO_FN_TPU4TO0, + GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, + GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, + GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ + GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, + GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ + GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, + GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ + GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, + GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ + GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, + GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ + GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ + GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, + GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ + GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, + GPIO_FN_SDHICLK0, + GPIO_FN_SDHICD0, + GPIO_FN_SDHID0_0, + GPIO_FN_SDHID0_1, + GPIO_FN_SDHID0_2, + GPIO_FN_SDHID0_3, + GPIO_FN_SDHICMD0, + GPIO_FN_SDHIWP0, + GPIO_FN_SDHICLK1, + GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2, + GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2, + GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2, + GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2, + GPIO_FN_SDHICMD1, + GPIO_FN_SDHICLK2, + GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4, + GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4, + GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4, + GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4, + GPIO_FN_SDHICMD2, + GPIO_FN_MMCCLK0, + GPIO_FN_MMCD0_0, + GPIO_FN_MMCD0_1, + GPIO_FN_MMCD0_2, + GPIO_FN_MMCD0_3, + GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5, + GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5, + GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5, + GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5, + GPIO_FN_MMCCMD0, + GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT, + GPIO_FN_MCP_WAIT__MCP_FRB, + GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1, + GPIO_FN_MCP_D15_MCP_NAF15, + GPIO_FN_MCP_D14_MCP_NAF14, + GPIO_FN_MCP_D13_MCP_NAF13, + GPIO_FN_MCP_D12_MCP_NAF12, + GPIO_FN_MCP_D11_MCP_NAF11, + GPIO_FN_MCP_D10_MCP_NAF10, + GPIO_FN_MCP_D9_MCP_NAF9, + GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1, + GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7, + + GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6, + GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5, + GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4, + GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3, + GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2, + GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1, + GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0, + GPIO_FN_MCP_NBRSTOUT_, + GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE, + + /* MSEL2 special case */ + GPIO_FN_TSIF2_TS_XX1, + GPIO_FN_TSIF2_TS_XX2, + GPIO_FN_TSIF2_TS_XX3, + GPIO_FN_TSIF2_TS_XX4, + GPIO_FN_TSIF2_TS_XX5, + GPIO_FN_TSIF1_TS_XX1, + GPIO_FN_TSIF1_TS_XX2, + GPIO_FN_TSIF1_TS_XX3, + GPIO_FN_TSIF1_TS_XX4, + GPIO_FN_TSIF1_TS_XX5, + GPIO_FN_TSIF0_TS_XX1, + GPIO_FN_TSIF0_TS_XX2, + GPIO_FN_TSIF0_TS_XX3, + GPIO_FN_TSIF0_TS_XX4, + GPIO_FN_TSIF0_TS_XX5, + GPIO_FN_MST1_TS_XX1, + GPIO_FN_MST1_TS_XX2, + GPIO_FN_MST1_TS_XX3, + GPIO_FN_MST1_TS_XX4, + GPIO_FN_MST1_TS_XX5, + GPIO_FN_MST0_TS_XX1, + GPIO_FN_MST0_TS_XX2, + GPIO_FN_MST0_TS_XX3, + GPIO_FN_MST0_TS_XX4, + GPIO_FN_MST0_TS_XX5, + + /* MSEL3 special cases */ + GPIO_FN_SDHI0_VCCQ_MC0_ON, + GPIO_FN_SDHI0_VCCQ_MC0_OFF, + GPIO_FN_DEBUG_MON_VIO, + GPIO_FN_DEBUG_MON_LCDD, + GPIO_FN_LCDC_LCDC0, + GPIO_FN_LCDC_LCDC1, + + /* MSEL4 special cases */ + GPIO_FN_IRQ9_MEM_INT, + GPIO_FN_IRQ9_MCP_INT, + GPIO_FN_A11, + GPIO_FN_KEYOUT8, + GPIO_FN_TPU4TO3, + GPIO_FN_RESETA_N_PU_ON, + GPIO_FN_RESETA_N_PU_OFF, + GPIO_FN_EDBGREQ_PD, + GPIO_FN_EDBGREQ_PU, + + /* Functions with pull-ups */ + GPIO_FN_KEYIN0_PU, + GPIO_FN_KEYIN1_PU, + GPIO_FN_KEYIN2_PU, + GPIO_FN_KEYIN3_PU, + GPIO_FN_KEYIN4_PU, + GPIO_FN_KEYIN5_PU, + GPIO_FN_KEYIN6_PU, + GPIO_FN_KEYIN7_PU, + GPIO_FN_SDHICD0_PU, + GPIO_FN_SDHID0_0_PU, + GPIO_FN_SDHID0_1_PU, + GPIO_FN_SDHID0_2_PU, + GPIO_FN_SDHID0_3_PU, + GPIO_FN_SDHICMD0_PU, + GPIO_FN_SDHIWP0_PU, + GPIO_FN_SDHID1_0_PU, + GPIO_FN_SDHID1_1_PU, + GPIO_FN_SDHID1_2_PU, + GPIO_FN_SDHID1_3_PU, + GPIO_FN_SDHICMD1_PU, + GPIO_FN_SDHID2_0_PU, + GPIO_FN_SDHID2_1_PU, + GPIO_FN_SDHID2_2_PU, + GPIO_FN_SDHID2_3_PU, + GPIO_FN_SDHICMD2_PU, + GPIO_FN_MMCCMD0_PU, + GPIO_FN_MMCCMD1_PU, + GPIO_FN_MMCD0_0_PU, + GPIO_FN_MMCD0_1_PU, + GPIO_FN_MMCD0_2_PU, + GPIO_FN_MMCD0_3_PU, + GPIO_FN_MMCD0_4_PU, + GPIO_FN_MMCD0_5_PU, + GPIO_FN_MMCD0_6_PU, + GPIO_FN_MMCD0_7_PU, + GPIO_FN_FSIACK_PU, + GPIO_FN_FSIAILR_PU, + GPIO_FN_FSIAIBT_PU, + GPIO_FN_FSIAISLD_PU, + + /* end of GPIO */ + GPIO_NR, +}; + +/* DMA slave IDs */ +enum { + SHDMA_SLAVE_INVALID, + SHDMA_SLAVE_SCIF0_TX, + SHDMA_SLAVE_SCIF0_RX, + SHDMA_SLAVE_SCIF1_TX, + SHDMA_SLAVE_SCIF1_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SCIF3_TX, + SHDMA_SLAVE_SCIF3_RX, + SHDMA_SLAVE_SCIF4_TX, + SHDMA_SLAVE_SCIF4_RX, + SHDMA_SLAVE_SCIF5_TX, + SHDMA_SLAVE_SCIF5_RX, + SHDMA_SLAVE_SCIF6_TX, + SHDMA_SLAVE_SCIF6_RX, + SHDMA_SLAVE_SCIF7_TX, + SHDMA_SLAVE_SCIF7_RX, + SHDMA_SLAVE_SCIF8_TX, + SHDMA_SLAVE_SCIF8_RX, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI0_RX, + SHDMA_SLAVE_SDHI1_TX, + SHDMA_SLAVE_SDHI1_RX, + SHDMA_SLAVE_SDHI2_TX, + SHDMA_SLAVE_SDHI2_RX, + SHDMA_SLAVE_MMCIF_TX, + SHDMA_SLAVE_MMCIF_RX, +}; + +/* + * SH73A0 IRQ LOCATION TABLE + * + * 416 ----------------------------------------- + * IRQ0-IRQ15 + * 431 ----------------------------------------- + * ... + * 448 ----------------------------------------- + * sh73a0-intcs + * sh73a0-intca-irq-pins + * 680 ----------------------------------------- + * ... + * 700 ----------------------------------------- + * sh73a0-pint0 + * 731 ----------------------------------------- + * 732 ----------------------------------------- + * sh73a0-pint1 + * 739 ----------------------------------------- + * ... + * 800 ----------------------------------------- + * IRQ16-IRQ31 + * 815 ----------------------------------------- + * ... + * 928 ----------------------------------------- + * sh73a0-intca-irq-pins + * 943 ----------------------------------------- + */ + +/* PINT interrupts are located at Linux IRQ 700 and up */ +#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) +#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) + +#endif /* __ASM_SH73A0_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0.h b/arch/arm/include/asm/arch-rmobile/sh73a0.h new file mode 100644 index 0000000..bdbb408 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sh73a0.h @@ -0,0 +1,289 @@ +#ifndef __ASM_ARCH_RMOBILE_SH73A0_H +#define __ASM_ARCH_RMOBILE_SH73A0_H + +/* Global Timer */ +#define GLOBAL_TIMER_BASE_ADDR (0xF0000200) +#define MERAM_BASE (0xE5580000) + +/* GIC */ +#define GIC_BASE (0xF0000100) +#define ICCICR GIC_BASE + +/* Secure control register */ +#define LIFEC_SEC_SRC (0xE6110008) + +/* RWDT */ +#define RWDT_BASE (0xE6020000) + +/* HPB Semaphore Control Registers */ +#define HPB_BASE (0xE6001010) + +/* Bus Semaphore Control Registers */ +#define HPBSCR_BASE (0xE6001600) + +/* SBSC1 */ +#define SBSC1_BASE (0xFE400000) +#define SDMRA1A (SBSC1_BASE + 0x100000) +#define SDMRA2A (SBSC1_BASE + 0x1C0000) +#define SDMRA3A (SBSC1_BASE + 0x104000) + +/* SBSC2 */ +#define SBSC2_BASE (0xFB400000) +#define SDMRA1B (SBSC2_BASE + 0x100000) +#define SDMRA2B (SBSC2_BASE + 0x1C0000) +#define SDMRA3B (SBSC2_BASE + 0x104000) + +/* CPG */ +#define CPG_BASE (0xE6150000) +#define CPG_SRCR_BASE (CPG_BASE + 0x80A0) +#define WUPCR (CPG_BASE + 0x1010) +#define SRESCR (CPG_BASE + 0x1018) +#define PCLKCR (CPG_BASE + 0x1020) + +/* SYSC */ +#define SYSC_BASE (0xE6180000) +#define RESCNT2 (SYSC_BASE + 0x8020) + +/* BSC */ +#define BSC_BASE (0xFEC10000) + +/* SCIF */ +#define SCIF0_BASE (0xE6C40000) +#define SCIF1_BASE (0xE6C50000) +#define SCIF2_BASE (0xE6C60000) +#define SCIF3_BASE (0xE6C70000) +#define SCIF4_BASE (0xE6C80000) +#define SCIF5_BASE (0xE6CB0000) +#define SCIF6_BASE (0xE6CC0000) +#define SCIF7_BASE (0xE6CD0000) + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct sh73a0_rwdt { + u16 rwtcnt0; /* 0x00 */ + u16 dummy0; /* 0x02 */ + u16 rwtcsra0; /* 0x04 */ + u16 dummy1; /* 0x06 */ + u16 rwtcsrb0; /* 0x08 */ +}; + +/* HPB Semaphore Control Registers */ +struct sh73a0_hpb { + u32 hpbctrl0; + u32 hpbctrl1; + u32 hpbctrl2; + u32 cccr; + u32 dummy0; /* 0x20 */ + u32 hpbctrl4; + u32 hpbctrl5; + u32 dummy1; /* 0x2C */ + u32 hpbctrl6; +}; + +/* Bus Semaphore Control Registers */ +struct sh73a0_hpb_bscr { + u32 mpsrc; /* 0x00 */ + u32 mpacctl; /* 0x04 */ + u32 dummy0[6]; + u32 smgpiosrc; /* 0x20 */ + u32 smgpioerr; + u32 smgpiotime; + u32 smgpiocnt; + u32 dummy1[4]; /* 0x30 .. 0x3C */ + u32 smcmt2src; + u32 smcmt2err; + u32 smcmt2time; + u32 smcmt2cnt; + u32 smcpgsrc; + u32 smcpgerr; + u32 smcpgtime; + u32 smcpgcnt; + u32 dummy2[4]; /* 0x60 - 0x6C */ + u32 smsyscsrc; + u32 smsyscerr; + u32 smsysctime; + u32 smsysccnt; +}; + +/* SBSC */ +struct sh73a0_sbsc { + u32 dummy0[2]; /* 0x00, 0x04 */ + u32 sdcr0; + u32 sdcr1; + u32 sdpcr; + u32 dummy1; /* 0x14 */ + u32 sdcr0s; + u32 sdcr1s; + u32 rtcsr; + u32 dummy2; /* 0x24 */ + u32 rtcor; + u32 rtcorh; + u32 rtcors; + u32 rtcorsh; + u32 dummy3[2]; /* 0x38, 0x3C */ + u32 sdwcrc0; + u32 sdwcrc1; + u32 sdwcr00; + u32 sdwcr01; + u32 sdwcr10; + u32 sdwcr11; + u32 sdpdcr0; + u32 dummy4; /* 0x5C */ + u32 sdwcr2; + u32 sdwcrc2; + u32 zqccr; + u32 dummy5[6]; /* 0x6C .. 0x80 */ + u32 sdmracr0; + u32 dummy6; /* 0x88 */ + u32 sdmrtmpcr; + u32 dummy7; /* 0x90 */ + u32 sdmrtmpmsk; + u32 dummy8; /* 0x98 */ + u32 sdgencnt; + u32 dphycnt0; + u32 dphycnt1; + u32 dphycnt2; + u32 dummy9[2]; /* 0xAC .. 0xB0 */ + u32 sddrvcr0; + u32 dummy10[14]; /* 0xB8 .. 0xEC */ + u32 dptdivcr0; + u32 dptdivcr1; + u32 dptdivcr2; + u32 dummy11; /* 0xFC */ + u32 sdptcr0; + u32 sdptcr1; + u32 sdptcr2; + u32 sdptcr3; /* 0x10C */ + u32 dummy12[145]; /* 0x110 .. 0x350 */ + u32 dllcnt0; /* 0x354 */ + u32 sbscmon0; +}; + +/* CPG */ +struct sh73a0_sbsc_cpg { + u32 frqcra; /* 0x00 */ + u32 frqcrb; + u32 vclkcr1; + u32 vclkcr2; + u32 zbckcr; + u32 flckcr; + u32 fsiackcr; + u32 vclkcr3; + u32 rtstbcr; + u32 systbcr; + u32 pll1cr; + u32 pll2cr; + u32 mstpsr0; + u32 dummy0; /* 0x34 */ + u32 mstpsr1; + u32 mstpsr5; + u32 mstpsr2; + u32 dummy1; /* 0x44 */ + u32 mstpsr3; + u32 mstpsr4; + u32 dummy2; /* 0x50 */ + u32 astat; + u32 dvfscr0; + u32 dvfscr1; + u32 dsitckcr; + u32 dsi0pckcr; + u32 dsi1pckcr; + u32 dsi0phycr; + u32 dsi1phycr; + u32 sd0ckcr; + u32 sd1ckcr; + u32 sd2ckcr; + u32 subckcr; + u32 spuackcr; + u32 msuckcr; + u32 hsickcr; + u32 fsibckcr; + u32 spuvckcr; + u32 mfck1cr; + u32 mfck2cr; + u32 dummy3[8]; /* 0xA0 .. 0xBC */ + u32 ckscr; + u32 dummy4; /* 0xC4 */ + u32 pll1stpcr; + u32 mpmode; + u32 pllecr; + u32 dummy5; /* 0xD4 */ + u32 pll0cr; + u32 pll3cr; + u32 dummy6; /* 0xE0 */ + u32 frqcrd; + u32 dummyi7; /* 0xE8 */ + u32 vrefcr; + u32 pll0stpcr; + u32 dummy8; /* 0xF4 */ + u32 pll2stpcr; + u32 pll3stpcr; + u32 dummy9[4]; /* 0x100 .. 0x10c */ + u32 rmstpcr0; + u32 rmstpcr1; + u32 rmstpcr2; + u32 rmstpcr3; + u32 rmstpcr4; + u32 rmstpcr5; + u32 dummy10[2]; /* 0x128 .. 0x12c */ + u32 smstpcr0; + u32 smstpcr1; + u32 smstpcr2; + u32 smstpcr3; + u32 smstpcr4; + u32 smstpcr5; + u32 dummy11[2]; /* 0x148 .. 0x14c */ + u32 cpgxxcs4; + u32 dummy12[7]; /* 0x154 .. 0x16c */ + u32 dvfscr2; + u32 dvfscr3; + u32 dvfscr4; + u32 dvfscr5; /* 0x17C */ +}; + +/* CPG SRCR part OK */ +struct sh73a0_sbsc_cpg_srcr { + u32 srcr0; + u32 dummy0; /* 0xA4 */ + u32 srcr1; + u32 dummy1; /* 0xAC */ + u32 srcr2; + u32 dummy2; /* 0xB4 */ + u32 srcr3; + u32 srcr4; + u32 dummy3; /* 0xC0 */ + u32 srcr5; +}; + +/* BSC */ +struct sh73a0_bsc { + u32 cmncr; + u32 cs0bcr; + u32 cs2bcr; + u32 dummy0; /* 0x0C */ + u32 cs4bcr; + u32 cs5abcr; + u32 cs5bbcr; + u32 cs6abcr; + u32 cs6bbcr; + u32 cs0wcr; + u32 cs2wcr; + u32 dummy1; /* 0x2C */ + u32 cs4wcr; + u32 cs5awcr; + u32 cs5bwcr; + u32 cs6awcr; + u32 cs6bwcr; + u32 rbwtcnt; + u32 busycr; + u32 dummy2; /* 0x5c */ + u32 cs7abcr; + u32 cs7awcr; + u32 dummy3[2]; /* 0x68, 0x6C */ + u32 bromtimcr; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */ diff --git a/arch/arm/include/asm/arch-rmobile/sys_proto.h b/arch/arm/include/asm/arch-rmobile/sys_proto.h new file mode 100644 index 0000000..fad4e4e --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sys_proto.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +struct rmobile_sysinfo { + char *board_string; +}; +extern const struct rmobile_sysinfo sysinfo; + +#endif diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h new file mode 100644 index 0000000..76bc52c --- /dev/null +++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2012. + * + * Gabriel Huau <contact@huau-gabriel.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _S3C24X0_GPIO_H_ +#define _S3C24X0_GPIO_H_ + +enum s3c2440_gpio { + GPA0, + GPA1, + GPA2, + GPA3, + GPA4, + GPA5, + GPA6, + GPA7, + GPA8, + GPA9, + GPA10, + GPA11, + GPA12, + GPA13, + GPA14, + GPA15, + GPA16, + GPA17, + GPA18, + GPA19, + GPA20, + GPA21, + GPA22, + GPA23, + GPA24, + + GPB0 = 32, + GPB1, + GPB2, + GPB3, + GPB4, + GPB5, + GPB6, + GPB7, + GPB8, + GPB9, + GPB10, + + GPC0 = 64, + GPC1, + GPC2, + GPC3, + GPC4, + GPC5, + GPC6, + GPC7, + GPC8, + GPC9, + GPC10, + GPC11, + GPC12, + GPC13, + GPC14, + GPC15, + + GPD0 = 96, + GPD1, + GPD2, + GPD3, + GPD4, + GPD5, + GPD6, + GPD7, + GPD8, + GPD9, + GPD10, + GPD11, + GPD12, + GPD13, + GPD14, + GPD15, + + GPE0 = 128, + GPE1, + GPE2, + GPE3, + GPE4, + GPE5, + GPE6, + GPE7, + GPE8, + GPE9, + GPE10, + GPE11, + GPE12, + GPE13, + GPE14, + GPE15, + + GPF0 = 160, + GPF1, + GPF2, + GPF3, + GPF4, + GPF5, + GPF6, + GPF7, + + GPG0 = 192, + GPG1, + GPG2, + GPG3, + GPG4, + GPG5, + GPG6, + GPG7, + GPG8, + GPG9, + GPG10, + GPG11, + GPG12, + GPG13, + GPG14, + GPG15, + + GPH0 = 224, + GPH1, + GPH2, + GPH3, + GPH4, + GPH5, + GPH6, + GPH7, + GPH8, + GPH9, + GPH10, + + GPJ0 = 256, + GPJ1, + GPJ2, + GPJ3, + GPJ4, + GPJ5, + GPJ6, + GPJ7, + GPJ8, + GPJ9, + GPJ10, + GPJ11, + GPJ12, +}; + +#endif diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h new file mode 100644 index 0000000..cc22de7 --- /dev/null +++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2012 + * + * Gabriel Huau <contact@huau-gabriel.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _S3C24X0_IOMUX_H_ +#define _S3C24X0_IOMUX_H_ + +enum s3c2440_iomux_func { + /* PORT A */ + IOMUXA_ADDR0 = 1, + IOMUXA_ADDR16 = (1 << 1), + IOMUXA_ADDR17 = (1 << 2), + IOMUXA_ADDR18 = (1 << 3), + IOMUXA_ADDR19 = (1 << 4), + IOMUXA_ADDR20 = (1 << 5), + IOMUXA_ADDR21 = (1 << 6), + IOMUXA_ADDR22 = (1 << 7), + IOMUXA_ADDR23 = (1 << 8), + IOMUXA_ADDR24 = (1 << 9), + IOMUXA_ADDR25 = (1 << 10), + IOMUXA_ADDR26 = (1 << 11), + IOMUXA_nGCS1 = (1 << 12), + IOMUXA_nGCS2 = (1 << 13), + IOMUXA_nGCS3 = (1 << 14), + IOMUXA_nGCS4 = (1 << 15), + IOMUXA_nGCS5 = (1 << 16), + IOMUXA_CLE = (1 << 17), + IOMUXA_ALE = (1 << 18), + IOMUXA_nFWE = (1 << 19), + IOMUXA_nFRE = (1 << 20), + IOMUXA_nRSTOUT = (1 << 21), + IOMUXA_nFCE = (1 << 22), + + /* PORT B */ + IOMUXB_nXDREQ0 = (2 << 20), + IOMUXB_nXDACK0 = (2 << 18), + IOMUXB_nXDREQ1 = (2 << 16), + IOMUXB_nXDACK1 = (2 << 14), + IOMUXB_nXBREQ = (2 << 12), + IOMUXB_nXBACK = (2 << 10), + IOMUXB_TCLK0 = (2 << 8), + IOMUXB_TOUT3 = (2 << 6), + IOMUXB_TOUT2 = (2 << 4), + IOMUXB_TOUT1 = (2 << 2), + IOMUXB_TOUT0 = 2, + + /* PORT C */ + IOMUXC_VS7 = (2 << 30), + IOMUXC_VS6 = (2 << 28), + IOMUXC_VS5 = (2 << 26), + IOMUXC_VS4 = (2 << 24), + IOMUXC_VS3 = (2 << 22), + IOMUXC_VS2 = (2 << 20), + IOMUXC_VS1 = (2 << 18), + IOMUXC_VS0 = (2 << 16), + IOMUXC_LCD_LPCREVB = (2 << 14), + IOMUXC_LCD_LPCREV = (2 << 12), + IOMUXC_LCD_LPCOE = (2 << 10), + IOMUXC_VM = (2 << 8), + IOMUXC_VFRAME = (2 << 6), + IOMUXC_VLINE = (2 << 4), + IOMUXC_VCLK = (2 << 2), + IOMUXC_LEND = 2, + IOMUXC_I2SSDI = (3 << 8), + + /* PORT D */ + IOMUXD_VS23 = (2 << 30), + IOMUXD_VS22 = (2 << 28), + IOMUXD_VS21 = (2 << 26), + IOMUXD_VS20 = (2 << 24), + IOMUXD_VS19 = (2 << 22), + IOMUXD_VS18 = (2 << 20), + IOMUXD_VS17 = (2 << 18), + IOMUXD_VS16 = (2 << 16), + IOMUXD_VS15 = (2 << 14), + IOMUXD_VS14 = (2 << 12), + IOMUXD_VS13 = (2 << 10), + IOMUXD_VS12 = (2 << 8), + IOMUXD_VS11 = (2 << 6), + IOMUXD_VS10 = (2 << 4), + IOMUXD_VS9 = (2 << 2), + IOMUXD_VS8 = 2, + IOMUXD_nSS0 = (3 << 30), + IOMUXD_nSS1 = (3 << 28), + IOMUXD_SPICLK1 = (3 << 20), + IOMUXD_SPIMOSI1 = (3 << 18), + IOMUXD_SPIMISO1 = (3 << 16), + + /* PORT E */ + IOMUXE_IICSDA = (2 << 30), + IOMUXE_IICSCL = (2 << 28), + IOMUXE_SPICLK0 = (2 << 26), + IOMUXE_SPIMOSI0 = (2 << 24), + IOMUXE_SPIMISO0 = (2 << 22), + IOMUXE_SDDAT3 = (2 << 20), + IOMUXE_SDDAT2 = (2 << 18), + IOMUXE_SDDAT1 = (2 << 16), + IOMUXE_SDDAT0 = (2 << 14), + IOMUXE_SDCMD = (2 << 12), + IOMUXE_SDCLK = (2 << 10), + IOMUXE_I2SDO = (2 << 8), + IOMUXE_I2SDI = (2 << 6), + IOMUXE_CDCLK = (2 << 4), + IOMUXE_I2SSCLK = (2 << 2), + IOMUXE_I2SLRCK = 2, + IOMUXE_AC_SDATA_OUT = (3 << 8), + IOMUXE_AC_SDATA_IN = (3 << 6), + IOMUXE_AC_nRESET = (3 << 4), + IOMUXE_AC_BIT_CLK = (3 << 2), + IOMUXE_AC_SYNC = 3, + + /* PORT F */ + IOMUXF_EINT7 = (2 << 14), + IOMUXF_EINT6 = (2 << 12), + IOMUXF_EINT5 = (2 << 10), + IOMUXF_EINT4 = (2 << 8), + IOMUXF_EINT3 = (2 << 6), + IOMUXF_EINT2 = (2 << 4), + IOMUXF_EINT1 = (2 << 2), + IOMUXF_EINT0 = 2, + + /* PORT G */ + IOMUXG_EINT23 = (2 << 30), + IOMUXG_EINT22 = (2 << 28), + IOMUXG_EINT21 = (2 << 26), + IOMUXG_EINT20 = (2 << 24), + IOMUXG_EINT19 = (2 << 22), + IOMUXG_EINT18 = (2 << 20), + IOMUXG_EINT17 = (2 << 18), + IOMUXG_EINT16 = (2 << 16), + IOMUXG_EINT15 = (2 << 14), + IOMUXG_EINT14 = (2 << 12), + IOMUXG_EINT13 = (2 << 10), + IOMUXG_EINT12 = (2 << 8), + IOMUXG_EINT11 = (2 << 6), + IOMUXG_EINT10 = (2 << 4), + IOMUXG_EINT9 = (2 << 2), + IOMUXG_EINT8 = 2, + IOMUXG_TCLK1 = (3 << 22), + IOMUXG_nCTS1 = (3 << 20), + IOMUXG_nRTS1 = (3 << 18), + IOMUXG_SPICLK1 = (3 << 14), + IOMUXG_SPIMOSI1 = (3 << 12), + IOMUXG_SPIMISO1 = (3 << 10), + IOMUXG_LCD_PWRDN = (3 << 8), + IOMUXG_nSS1 = (3 << 6), + IOMUXG_nSS0 = (3 << 4), + + /* PORT H */ + IOMUXH_CLKOUT1 = (2 << 20), + IOMUXH_CLKOUT0 = (2 << 18), + IOMUXH_UEXTCLK = (2 << 16), + IOMUXH_RXD2 = (2 << 14), + IOMUXH_TXD2 = (2 << 12), + IOMUXH_RXD1 = (2 << 10), + IOMUXH_TXD1 = (2 << 8), + IOMUXH_RXD0 = (2 << 6), + IOMUXH_TXD0 = (2 << 4), + IOMUXH_nRTS0 = (2 << 2), + IOMUXH_nCTS0 = 2, + IOMUXH_nCTS1 = (3 << 14), + IOMUXH_nRTS1 = (3 << 12), + + /* PORT J */ + IOMUXJ_CAMRESET = (2 << 24), + IOMUXJ_CAMCLKOUT = (2 << 22), + IOMUXJ_CAMHREF = (2 << 20), + IOMUXJ_CAMVSYNC = (2 << 18), + IOMUXJ_CAMPCLK = (2 << 16), + IOMUXJ_CAMDATA7 = (2 << 14), + IOMUXJ_CAMDATA6 = (2 << 12), + IOMUXJ_CAMDATA5 = (2 << 10), + IOMUXJ_CAMDATA4 = (2 << 8), + IOMUXJ_CAMDATA3 = (2 << 6), + IOMUXJ_CAMDATA2 = (2 << 4), + IOMUXJ_CAMDATA1 = (2 << 2), + IOMUXJ_CAMDATA0 = 2 +}; + +#endif diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h new file mode 100644 index 0000000..d9d2c1c --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _RESET_MANAGER_H_ +#define _RESET_MANAGER_H_ + +void reset_cpu(ulong addr); +void reset_deassert_peripherals_handoff(void); + +struct socfpga_reset_manager { + u32 padding1; + u32 ctrl; + u32 padding2; + u32 padding3; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; +}; + +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 + +#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h new file mode 100644 index 0000000..f353eb2 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_BASE_ADDRS_H_ +#define _SOCFPGA_BASE_ADDRS_H_ + +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 + +#endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h new file mode 100644 index 0000000..efd0c06 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/spl.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2012 Pavel Machek <pavel@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_SPL_H_ +#define _SOCFPGA_SPL_H_ + +/* Symbols from linker script */ +extern char __malloc_start, __malloc_end, __stack_start; + +#define BOOT_DEVICE_RAM 1 + +#endif diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h new file mode 100644 index 0000000..830c94a --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/timer.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_TIMER_H_ +#define _SOCFPGA_TIMER_H_ + +struct socfpga_timer { + u32 load_val; + u32 curr_val; + u32 ctrl; + u32 eoi; + u32 int_stat; +}; + +#endif diff --git a/arch/arm/include/asm/arch-tegra20/ap20.h b/arch/arm/include/asm/arch-tegra/ap.h index 70d94c5..70d94c5 100644 --- a/arch/arm/include/asm/arch-tegra20/ap20.h +++ b/arch/arm/include/asm/arch-tegra/ap.h diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h new file mode 100644 index 0000000..be6bf25 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_BOARD_H_ +#define _TEGRA_BOARD_H_ + +/* Set up pinmux to make UART usable */ +void gpio_config_uart(void); /* CONFIG_SPI_UART_SWITCH */ +void gpio_early_init_uart(void); /*!CONFIG_SPI_UART_SWITCH */ + +/* Set up early UART output */ +void board_init_uart_f(void); + +/* Set up any early GPIOs the board might need for proper operation */ +void gpio_early_init(void); /* overrideable GPIO config */ + +/* + * Hooks to allow boards to set up the pinmux for a specific function. + * Has to be implemented in the board files as we don't yet support pinmux + * setup from FTD. If a board file does not implement one of those functions + * an empty stub function will be called. + */ + +void pin_mux_usb(void); /* overrideable USB pinmux setup */ +void pin_mux_spi(void); /* overrideable SPI pinmux setup */ +void pin_mux_nand(void); /* overrideable NAND pinmux setup */ + +#endif diff --git a/arch/arm/include/asm/arch-tegra20/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 8c3be91..7b548c2 100644 --- a/arch/arm/include/asm/arch-tegra20/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -27,8 +27,7 @@ /* PLL registers - there are several PLLs in the clock controller */ struct clk_pll { uint pll_base; /* the control register */ - uint pll_out; /* output control */ - uint reserved; + uint pll_out[2]; /* output control */ uint pll_misc; /* other misc things */ }; @@ -112,6 +111,14 @@ struct clk_rst_ctlr { #define PLL_DIVM_SHIFT 0 #define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT) +/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ +#define PLL_OUT_RSTN (1 << 0) +#define PLL_OUT_CLKEN (1 << 1) +#define PLL_OUT_OVRRIDE (1 << 2) + +#define PLL_OUT_RATIO_SHIFT 8 +#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) + /* CLK_RST_CONTROLLER_PLLx_MISC_0 */ #define PLL_CPCON_SHIFT 8 #define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h new file mode 100644 index 0000000..eac1dc2 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Tegra clock control functions */ + +#ifndef _CLOCK_H +#define _CLOCK_H + +/* Set of oscillator frequencies supported in the internal API. */ +enum clock_osc_freq { + /* All in MHz, so 13_0 is 13.0MHz */ + CLOCK_OSC_FREQ_13_0, + CLOCK_OSC_FREQ_19_2, + CLOCK_OSC_FREQ_12_0, + CLOCK_OSC_FREQ_26_0, + + CLOCK_OSC_FREQ_COUNT, +}; + +#include <asm/arch/clock-tables.h> +/* PLL stabilization delay in usec */ +#define CLOCK_PLL_STABLE_DELAY_US 300 + +/* return the current oscillator clock frequency */ +enum clock_osc_freq clock_get_osc_freq(void); + +/** + * Start PLL using the provided configuration parameters. + * + * @param id clock id + * @param divm input divider + * @param divn feedback divider + * @param divp post divider 2^n + * @param cpcon charge pump setup control + * @param lfcon loop filter setup control + * + * @returns monotonic time in us that the PLL will be stable + */ +unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, + u32 divp, u32 cpcon, u32 lfcon); + +/** + * Set PLL output frequency + * + * @param clkid clock id + * @param pllout pll output id + * @param rate desired output rate + * + * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) + */ +int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, + unsigned rate); + +/** + * Read low-level parameters of a PLL. + * + * @param id clock id to read (note: USB is not supported) + * @param divm returns input divider + * @param divn returns feedback divider + * @param divp returns post divider 2^n + * @param cpcon returns charge pump setup control + * @param lfcon returns loop filter setup control + * + * @returns 0 if ok, -1 on error (invalid clock id) + */ +int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, + u32 *divp, u32 *cpcon, u32 *lfcon); + +/* + * Enable a clock + * + * @param id clock id + */ +void clock_enable(enum periph_id clkid); + +/* + * Disable a clock + * + * @param id clock id + */ +void clock_disable(enum periph_id clkid); + +/* + * Set whether a clock is enabled or disabled. + * + * @param id clock id + * @param enable 1 to enable, 0 to disable + */ +void clock_set_enable(enum periph_id clkid, int enable); + +/** + * Reset a peripheral. This puts it in reset, waits for a delay, then takes + * it out of reset and waits for th delay again. + * + * @param periph_id peripheral to reset + * @param us_delay time to delay in microseconds + */ +void reset_periph(enum periph_id periph_id, int us_delay); + +/** + * Put a peripheral into or out of reset. + * + * @param periph_id peripheral to reset + * @param enable 1 to put into reset, 0 to take out of reset + */ +void reset_set_enable(enum periph_id periph_id, int enable); + + +/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ +enum crc_reset_id { + /* Things we can hold in reset for each CPU */ + crc_rst_cpu = 1, + crc_rst_de = 1 << 2, /* What is de? */ + crc_rst_watchdog = 1 << 3, + crc_rst_debug = 1 << 4, +}; + +/** + * Put parts of the CPU complex into or out of reset.\ + * + * @param cpu cpu number (0 or 1 on Tegra2) + * @param which which parts of the complex to affect (OR of crc_reset_id) + * @param reset 1 to assert reset, 0 to de-assert + */ +void reset_cmplx_set_enable(int cpu, int which, int reset); + +/** + * Set the source for a peripheral clock. This plus the divisor sets the + * clock rate. You need to look up the datasheet to see the meaning of the + * source parameter as it changes for each peripheral. + * + * Warning: This function is only for use pre-relocation. Please use + * clock_start_periph_pll() instead. + * + * @param periph_id peripheral to adjust + * @param source source clock (0, 1, 2 or 3) + */ +void clock_ll_set_source(enum periph_id periph_id, unsigned source); + +/** + * Set the source and divisor for a peripheral clock. This sets the + * clock rate. You need to look up the datasheet to see the meaning of the + * source parameter as it changes for each peripheral. + * + * Warning: This function is only for use pre-relocation. Please use + * clock_start_periph_pll() instead. + * + * @param periph_id peripheral to adjust + * @param source source clock (0, 1, 2 or 3) + * @param divisor divisor value to use + */ +void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, + unsigned divisor); + +/** + * Start a peripheral PLL clock at the given rate. This also resets the + * peripheral. + * + * @param periph_id peripheral to start + * @param parent PLL id of required parent clock + * @param rate Required clock rate in Hz + * @return rate selected in Hz, or -1U if something went wrong + */ +unsigned clock_start_periph_pll(enum periph_id periph_id, + enum clock_id parent, unsigned rate); + +/** + * Returns the rate of a peripheral clock in Hz. Since the caller almost + * certainly knows the parent clock (having just set it) we require that + * this be passed in so we don't need to work it out. + * + * @param periph_id peripheral to start + * @param parent PLL id of parent clock (used to calculate rate, you + * must know this!) + * @return clock rate of peripheral in Hz + */ +unsigned long clock_get_periph_rate(enum periph_id periph_id, + enum clock_id parent); + +/** + * Adjust peripheral PLL clock to the given rate. This does not reset the + * peripheral. If a second stage divisor is not available, pass NULL for + * extra_div. If it is available, then this parameter will return the + * divisor selected (which will be a power of 2 from 1 to 256). + * + * @param periph_id peripheral to start + * @param parent PLL id of required parent clock + * @param rate Required clock rate in Hz + * @param extra_div value for the second-stage divisor (NULL if one is + not available) + * @return rate selected in Hz, or -1U if something went wrong + */ +unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, + enum clock_id parent, unsigned rate, int *extra_div); + +/** + * Returns the clock rate of a specified clock, in Hz. + * + * @param parent PLL id of clock to check + * @return rate of clock in Hz + */ +unsigned clock_get_rate(enum clock_id clkid); + +/** + * Start up a UART using low-level calls + * + * Prior to relocation clock_start_periph_pll() cannot be called. This + * function provides a way to set up a UART using low-level calls which + * do not require BSS. + * + * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) + */ +void clock_ll_start_uart(enum periph_id periph_id); + +/** + * Decode a peripheral ID from a device tree node. + * + * This works by looking up the peripheral's 'clocks' node and reading out + * the second cell, which is the clock number / peripheral ID. + * + * @param blob FDT blob to use + * @param node Node to look at + * @return peripheral ID, or PERIPH_ID_NONE if none + */ +enum periph_id clock_decode_periph_id(const void *blob, int node); + +/** + * Checks if the oscillator bypass is enabled (XOBP bit) + * + * @return 1 if bypass is enabled, 0 if not + */ +int clock_get_osc_bypass(void); + +/* + * Checks that clocks are valid and prints a warning if not + * + * @return 0 if ok, -1 on error + */ +int clock_verify(void); + +/* Initialize the clocks */ +void clock_init(void); + +/* Initialize the PLLs */ +void clock_early_init(void); + +#endif /* _CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/fuse.h b/arch/arm/include/asm/arch-tegra/fuse.h index b7e3808..b7e3808 100644 --- a/arch/arm/include/asm/arch-tegra20/fuse.h +++ b/arch/arm/include/asm/arch-tegra/fuse.h diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h new file mode 100644 index 0000000..0a972d5 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2011, Google Inc. All rights reserved. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_GPIO_H_ +#define _TEGRA_GPIO_H_ + +#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) +#define GPIO_NAME_SIZE 20 /* gpio_request max label len */ + +#define GPIO_BANK(x) ((x) >> 5) +#define GPIO_PORT(x) (((x) >> 3) & 0x3) +#define GPIO_FULLPORT(x) ((x) >> 3) +#define GPIO_BIT(x) ((x) & 0x7) + +/* + * Tegra-specific GPIO API + */ + +void gpio_info(void); + +#define gpio_status() gpio_info() +#endif /* TEGRA_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/mmc.h b/arch/arm/include/asm/arch-tegra/mmc.h index 5c95047..5c95047 100644 --- a/arch/arm/include/asm/arch-tegra20/mmc.h +++ b/arch/arm/include/asm/arch-tegra/mmc.h diff --git a/arch/arm/include/asm/arch-tegra20/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h index b1d47cd..b1d47cd 100644 --- a/arch/arm/include/asm/arch-tegra20/pmc.h +++ b/arch/arm/include/asm/arch-tegra/pmc.h diff --git a/arch/arm/include/asm/arch-tegra20/scu.h b/arch/arm/include/asm/arch-tegra/scu.h index 787ded0..787ded0 100644 --- a/arch/arm/include/asm/arch-tegra20/scu.h +++ b/arch/arm/include/asm/arch-tegra/scu.h diff --git a/arch/arm/include/asm/arch-tegra20/sys_proto.h b/arch/arm/include/asm/arch-tegra/sys_proto.h index 919aec7..919aec7 100644 --- a/arch/arm/include/asm/arch-tegra20/sys_proto.h +++ b/arch/arm/include/asm/arch-tegra/sys_proto.h diff --git a/arch/arm/include/asm/arch-tegra20/tegra20.h b/arch/arm/include/asm/arch-tegra/tegra.h index c9485a1..6d2e62f 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra20.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -21,10 +21,9 @@ * MA 02111-1307 USA */ -#ifndef _TEGRA20_H_ -#define _TEGRA20_H_ +#ifndef _TEGRA_H_ +#define _TEGRA_H_ -#define NV_PA_SDRAM_BASE 0x00000000 #define NV_PA_ARM_PERIPHBASE 0x50040000 #define NV_PA_PG_UP_BASE 0x60000000 #define NV_PA_TMRUS_BASE 0x60005010 @@ -41,11 +40,11 @@ #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) #define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) #define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) +#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) +#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) #define NV_PA_CSITE_BASE 0x70040000 -#define TEGRA_USB1_BASE 0xC5000000 -#define TEGRA_USB3_BASE 0xC5008000 #define TEGRA_USB_ADDR_MASK 0xFFFFC000 #define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE @@ -60,11 +59,10 @@ struct timerus { }; /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ -#define AP20_WB_RUN_ADDRESS 0x40020000 +#define NV_WB_RUN_ADDRESS 0x40020000 #define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ #define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ -#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ /* These are the available SKUs (product types) for Tegra */ enum { @@ -89,4 +87,4 @@ enum { #define PRM_RSTCTRL NV_PA_PMC_BASE #endif -#endif /* TEGRA20_H */ +#endif /* TEGRA_H */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index 6abfe4e..2650744 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -1,5 +1,5 @@ /* - * NVIDIA Tegra20 I2C controller + * NVIDIA Tegra I2C controller * * Copyright 2010-2011 NVIDIA Corporation * @@ -161,4 +161,4 @@ struct i2c_ctlr { */ int tegra_i2c_get_dvc_bus_num(void); -#endif +#endif /* _TEGRA_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index dd746ca..dd746ca 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h diff --git a/arch/arm/include/asm/arch-tegra20/tegra_spi.h b/arch/arm/include/asm/arch-tegra/tegra_spi.h index d53a93f..d53a93f 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra_spi.h +++ b/arch/arm/include/asm/arch-tegra/tegra_spi.h diff --git a/arch/arm/include/asm/arch-tegra20/timer.h b/arch/arm/include/asm/arch-tegra/timer.h index fdb99a7..fdb99a7 100644 --- a/arch/arm/include/asm/arch-tegra20/timer.h +++ b/arch/arm/include/asm/arch-tegra/timer.h diff --git a/arch/arm/include/asm/arch-tegra20/uart.h b/arch/arm/include/asm/arch-tegra/uart.h index aea29a7..aea29a7 100644 --- a/arch/arm/include/asm/arch-tegra20/uart.h +++ b/arch/arm/include/asm/arch-tegra/uart.h diff --git a/arch/arm/include/asm/arch-tegra20/warmboot.h b/arch/arm/include/asm/arch-tegra/warmboot.h index 99ac2e7..99ac2e7 100644 --- a/arch/arm/include/asm/arch-tegra20/warmboot.h +++ b/arch/arm/include/asm/arch-tegra/warmboot.h diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h new file mode 100644 index 0000000..53708e0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com> + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Tegra20 clock PLL tables */ + +#ifndef _CLOCK_TABLES_H_ +#define _CLOCK_TABLES_H_ + +/* The PLLs supported by the hardware */ +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + + /* These are the base clocks (inputs to the Tegra SOC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, + + CLOCK_ID_COUNT, /* number of clocks */ + CLOCK_ID_NONE = -1, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_RESERVED1, + PERIPH_ID_RESERVED2, + PERIPH_ID_AC97, + PERIPH_ID_RTC, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S1, + PERIPH_ID_I2C1, + PERIPH_ID_NDFLASH, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_TWC, + PERIPH_ID_PWM, + PERIPH_ID_I2S2, + PERIPH_ID_EPP, + PERIPH_ID_VI, + PERIPH_ID_2D, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_3D, + PERIPH_ID_IDE, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_RESERVED30, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_KBC, + PERIPH_ID_STAT_MON, + PERIPH_ID_PMC, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_SPI1, + PERIPH_ID_SBC2, + PERIPH_ID_XIO, + PERIPH_ID_SBC3, + PERIPH_ID_DVC_I2C, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_TVO, + PERIPH_ID_MIPI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_TVDAC, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_RESERVED56, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_MPE, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 */ + PERIPH_ID_SPEEDO, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_RESERVED74, + PERIPH_ID_AVPUCQ, + PERIPH_ID_RESERVED76, + PERIPH_ID_RESERVED77, + PERIPH_ID_RESERVED78, + PERIPH_ID_RESERVED79, + + /* 80 */ + PERIPH_ID_RESERVED80, + PERIPH_ID_RESERVED81, + PERIPH_ID_RESERVED82, + PERIPH_ID_RESERVED83, + PERIPH_ID_IRAMA, + PERIPH_ID_IRAMB, + PERIPH_ID_IRAMC, + PERIPH_ID_IRAMD, + + /* 88 */ + PERIPH_ID_CRAM2, + PERIPH_ID_SYNC_CLK_DOUBLER, + PERIPH_ID_CLK_M_DOUBLER, + PERIPH_ID_RESERVED91, + PERIPH_ID_SUS_OUT, + PERIPH_ID_DEV2_OUT, + PERIPH_ID_DEV1_OUT, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +enum pll_out_id { + PLL_OUT1, + PLL_OUT2, + PLL_OUT3, + PLL_OUT4 +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ +#define PERIPH_REG(id) ((id) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range, and not a simple PLL */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ + (id) < CLOCK_ID_FIRST_SIMPLE) + +#endif /* _CLOCK_TABLES_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h index ff83bbf..f592b95 100644 --- a/arch/arm/include/asm/arch-tegra20/clock.h +++ b/arch/arm/include/asm/arch-tegra20/clock.h @@ -19,389 +19,11 @@ * MA 02111-1307 USA */ -/* Tegra2 clock control functions */ +/* Tegra20 clock control functions */ -#ifndef _CLOCK_H -#define _CLOCK_H +#ifndef _TEGRA20_CLOCK_H +#define _TEGRA20_CLOCK_H -/* Set of oscillator frequencies supported in the internal API. */ -enum clock_osc_freq { - /* All in MHz, so 13_0 is 13.0MHz */ - CLOCK_OSC_FREQ_13_0, - CLOCK_OSC_FREQ_19_2, - CLOCK_OSC_FREQ_12_0, - CLOCK_OSC_FREQ_26_0, +#include <asm/arch-tegra/clock.h> - CLOCK_OSC_FREQ_COUNT, -}; - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - - /* These are the base clocks (inputs to the Tegra SOC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - - CLOCK_ID_COUNT, /* number of clocks */ - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_RESERVED1, - PERIPH_ID_RESERVED2, - PERIPH_ID_AC97, - PERIPH_ID_RTC, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S1, - PERIPH_ID_I2C1, - PERIPH_ID_NDFLASH, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_TWC, - PERIPH_ID_PWM, - PERIPH_ID_I2S2, - PERIPH_ID_EPP, - PERIPH_ID_VI, - PERIPH_ID_2D, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_3D, - PERIPH_ID_IDE, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_RESERVED30, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, - PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_SPI1, - PERIPH_ID_SBC2, - PERIPH_ID_XIO, - PERIPH_ID_SBC3, - PERIPH_ID_DVC_I2C, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_TVDAC, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_RESERVED56, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_MPE, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 */ - PERIPH_ID_SPEEDO, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_RESERVED74, - PERIPH_ID_AVPUCQ, - PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, - PERIPH_ID_RESERVED79, - - /* 80 */ - PERIPH_ID_RESERVED80, - PERIPH_ID_RESERVED81, - PERIPH_ID_RESERVED82, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, - - /* 88 */ - PERIPH_ID_CRAM2, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ -#define PERIPH_REG(id) ((id) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range, and not a simple PLL */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ - (id) < CLOCK_ID_FIRST_SIMPLE) - -/* PLL stabilization delay in usec */ -#define CLOCK_PLL_STABLE_DELAY_US 300 - -/* return the current oscillator clock frequency */ -enum clock_osc_freq clock_get_osc_freq(void); - -/** - * Start PLL using the provided configuration parameters. - * - * @param id clock id - * @param divm input divider - * @param divn feedback divider - * @param divp post divider 2^n - * @param cpcon charge pump setup control - * @param lfcon loop filter setup control - * - * @returns monotonic time in us that the PLL will be stable - */ -unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, - u32 divp, u32 cpcon, u32 lfcon); - -/** - * Read low-level parameters of a PLL. - * - * @param id clock id to read (note: USB is not supported) - * @param divm returns input divider - * @param divn returns feedback divider - * @param divp returns post divider 2^n - * @param cpcon returns charge pump setup control - * @param lfcon returns loop filter setup control - * - * @returns 0 if ok, -1 on error (invalid clock id) - */ -int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, - u32 *divp, u32 *cpcon, u32 *lfcon); - -/* - * Enable a clock - * - * @param id clock id - */ -void clock_enable(enum periph_id clkid); - -/* - * Disable a clock - * - * @param id clock id - */ -void clock_disable(enum periph_id clkid); - -/* - * Set whether a clock is enabled or disabled. - * - * @param id clock id - * @param enable 1 to enable, 0 to disable - */ -void clock_set_enable(enum periph_id clkid, int enable); - -/** - * Reset a peripheral. This puts it in reset, waits for a delay, then takes - * it out of reset and waits for th delay again. - * - * @param periph_id peripheral to reset - * @param us_delay time to delay in microseconds - */ -void reset_periph(enum periph_id periph_id, int us_delay); - -/** - * Put a peripheral into or out of reset. - * - * @param periph_id peripheral to reset - * @param enable 1 to put into reset, 0 to take out of reset - */ -void reset_set_enable(enum periph_id periph_id, int enable); - - -/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ -enum crc_reset_id { - /* Things we can hold in reset for each CPU */ - crc_rst_cpu = 1, - crc_rst_de = 1 << 2, /* What is de? */ - crc_rst_watchdog = 1 << 3, - crc_rst_debug = 1 << 4, -}; - -/** - * Put parts of the CPU complex into or out of reset.\ - * - * @param cpu cpu number (0 or 1 on Tegra2) - * @param which which parts of the complex to affect (OR of crc_reset_id) - * @param reset 1 to assert reset, 0 to de-assert - */ -void reset_cmplx_set_enable(int cpu, int which, int reset); - -/** - * Set the source for a peripheral clock. This plus the divisor sets the - * clock rate. You need to look up the datasheet to see the meaning of the - * source parameter as it changes for each peripheral. - * - * Warning: This function is only for use pre-relocation. Please use - * clock_start_periph_pll() instead. - * - * @param periph_id peripheral to adjust - * @param source source clock (0, 1, 2 or 3) - */ -void clock_ll_set_source(enum periph_id periph_id, unsigned source); - -/** - * Set the source and divisor for a peripheral clock. This sets the - * clock rate. You need to look up the datasheet to see the meaning of the - * source parameter as it changes for each peripheral. - * - * Warning: This function is only for use pre-relocation. Please use - * clock_start_periph_pll() instead. - * - * @param periph_id peripheral to adjust - * @param source source clock (0, 1, 2 or 3) - * @param divisor divisor value to use - */ -void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, - unsigned divisor); - -/** - * Start a peripheral PLL clock at the given rate. This also resets the - * peripheral. - * - * @param periph_id peripheral to start - * @param parent PLL id of required parent clock - * @param rate Required clock rate in Hz - * @return rate selected in Hz, or -1U if something went wrong - */ -unsigned clock_start_periph_pll(enum periph_id periph_id, - enum clock_id parent, unsigned rate); - -/** - * Returns the rate of a peripheral clock in Hz. Since the caller almost - * certainly knows the parent clock (having just set it) we require that - * this be passed in so we don't need to work it out. - * - * @param periph_id peripheral to start - * @param parent PLL id of parent clock (used to calculate rate, you - * must know this!) - * @return clock rate of peripheral in Hz - */ -unsigned long clock_get_periph_rate(enum periph_id periph_id, - enum clock_id parent); - -/** - * Adjust peripheral PLL clock to the given rate. This does not reset the - * peripheral. If a second stage divisor is not available, pass NULL for - * extra_div. If it is available, then this parameter will return the - * divisor selected (which will be a power of 2 from 1 to 256). - * - * @param periph_id peripheral to start - * @param parent PLL id of required parent clock - * @param rate Required clock rate in Hz - * @param extra_div value for the second-stage divisor (NULL if one is - not available) - * @return rate selected in Hz, or -1U if something went wrong - */ -unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, - enum clock_id parent, unsigned rate, int *extra_div); - -/** - * Returns the clock rate of a specified clock, in Hz. - * - * @param parent PLL id of clock to check - * @return rate of clock in Hz - */ -unsigned clock_get_rate(enum clock_id clkid); - -/** - * Start up a UART using low-level calls - * - * Prior to relocation clock_start_periph_pll() cannot be called. This - * function provides a way to set up a UART using low-level calls which - * do not require BSS. - * - * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) - */ -void clock_ll_start_uart(enum periph_id periph_id); - -/** - * Decode a peripheral ID from a device tree node. - * - * This works by looking up the peripheral's 'clocks' node and reading out - * the second cell, which is the clock number / peripheral ID. - * - * @param blob FDT blob to use - * @param node Node to look at - * @return peripheral ID, or PERIPH_ID_NONE if none - */ -enum periph_id clock_decode_periph_id(const void *blob, int node); - -/** - * Checks if the oscillator bypass is enabled (XOBP bit) - * - * @return 1 if bypass is enabled, 0 if not - */ -int clock_get_osc_bypass(void); - -/* - * Checks that clocks are valid and prints a warning if not - * - * @return 0 if ok, -1 on error - */ -int clock_verify(void); - -/* Initialize the clocks */ -void clock_init(void); - -/* Initialize the PLLs */ -void clock_early_init(void); - -#endif +#endif /* _TEGRA20_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h index bd511db..c986b93 100644 --- a/arch/arm/include/asm/arch-tegra20/funcmux.h +++ b/arch/arm/include/asm/arch-tegra20/funcmux.h @@ -60,6 +60,7 @@ enum { /* NAND flags */ FUNCMUX_NDFLASH_ATC = 0, + FUNCMUX_NDFLASH_KBC_8_BIT, }; /** diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h index 06be4c2..e2848fe 100644 --- a/arch/arm/include/asm/arch-tegra20/gpio.h +++ b/arch/arm/include/asm/arch-tegra20/gpio.h @@ -20,8 +20,8 @@ * MA 02111-1307 USA */ -#ifndef _TEGRA_GPIO_H_ -#define _TEGRA_GPIO_H_ +#ifndef _TEGRA20_GPIO_H_ +#define _TEGRA20_GPIO_H_ /* * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, @@ -29,8 +29,8 @@ */ #define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ #define TEGRA_GPIO_BANKS 7 /* number of banks */ -#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) -#define GPIO_NAME_SIZE 20 /* gpio_request max label len */ + +#include <asm/arch-tegra/gpio.h> /* GPIO Controller registers for a single bank */ struct gpio_ctlr_bank { @@ -48,11 +48,6 @@ struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; }; -#define GPIO_BANK(x) ((x) >> 5) -#define GPIO_PORT(x) (((x) >> 3) & 0x3) -#define GPIO_FULLPORT(x) ((x) >> 3) -#define GPIO_BIT(x) ((x) & 0x7) - enum gpio_pin { GPIO_PA0 = 0, /* pin 0 */ GPIO_PA1, @@ -280,11 +275,4 @@ enum gpio_pin { GPIO_PBB7, /* pin 223 */ }; -/* - * Tegra20-specific GPIO API - */ - -void gpio_info(void); - -#define gpio_status() gpio_info() -#endif /* TEGRA_GPIO_H_ */ +#endif /* TEGRA20_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h new file mode 100644 index 0000000..ca98733 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/tegra.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA20_H_ +#define _TEGRA20_H_ + +#define NV_PA_SDRAM_BASE 0x00000000 + +#include <asm/arch-tegra/tegra.h> + +#define TEGRA_USB1_BASE 0xC5000000 +#define TEGRA_USB3_BASE 0xC5008000 + +#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ + +#endif /* TEGRA20_H */ diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h index 638033b..fdbd127 100644 --- a/arch/arm/include/asm/arch-tegra20/usb.h +++ b/arch/arm/include/asm/arch-tegra20/usb.h @@ -100,10 +100,12 @@ struct usb_ctlr { /* 0x410 */ uint usb1_legacy_ctrl; - uint reserved12[3]; + uint reserved12[4]; - /* 0x420 */ - uint reserved13[56]; + /* 0x424 */ + uint ulpi_timing_ctrl_0; + uint ulpi_timing_ctrl_1; + uint reserved13[53]; /* 0x500 */ uint reserved14[64 * 3]; @@ -144,10 +146,24 @@ struct usb_ctlr { #define VBUS_SENSE_CTL_AB_SESS_VLD 2 #define VBUS_SENSE_CTL_A_SESS_VLD 3 +/* USB2_IF_ULPI_TIMING_CTRL_0 */ +#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) +#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) + +/* USB2_IF_ULPI_TIMING_CTRL_1 */ +#define ULPI_DATA_TRIMMER_LOAD (1 << 0) +#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) +#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) +#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) +#define ULPI_DIR_TRIMMER_LOAD (1 << 24) +#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) + /* USBx_IF_USB_SUSP_CTRL_0 */ +#define ULPI_PHY_ENB (1 << 13) #define UTMIP_PHY_ENB (1 << 12) #define UTMIP_RESET (1 << 11) #define USB_PHY_CLK_VALID (1 << 7) +#define USB_SUSP_CLR (1 << 5) /* USBx_UTMIP_MISC_CFG1 */ #define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 @@ -203,12 +219,15 @@ struct usb_ctlr { /* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ #define PTS_SHIFT 30 #define PTS_MASK (3U << PTS_SHIFT) -#define PTS_UTMI 0 +#define PTS_UTMI 0 #define PTS_RESERVED 1 -#define PTS_ULP 2 +#define PTS_ULPI 2 #define PTS_ICUSB_SER 3 #define STS (1 << 29) +#define WKOC (1 << 22) +#define WKDS (1 << 21) +#define WKCN (1 << 20) /* USBx_UTMIP_XCVR_CFG0_0 */ #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) @@ -240,13 +259,13 @@ int board_usb_init(const void *blob); * @param hcor returns start address of EHCI HCOR registers * @return 0 if ok, -1 on error (generally invalid port number) */ -int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor); +int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor); /** * Stop the current port * * @return 0 if ok, -1 if no port was active */ -int tegrausb_stop_port(void); +int tegrausb_stop_port(int portnum); #endif /* _TEGRA_USB_H_ */ diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h index e72c5df..77e8170 100644 --- a/arch/arm/include/asm/ehci-omap.h +++ b/arch/arm/include/asm/ehci-omap.h @@ -136,7 +136,15 @@ struct omap_ehci { u32 insreg08; /* 0xb0 */ }; -int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata); +/* + * FIXME: forward declaration of this structs needed because omap got the + * ehci implementation backwards. move out ehci_hcd_x from board files + */ +struct ehci_hccr; +struct ehci_hcor; + +int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, + struct ehci_hccr **hccr, struct ehci_hcor **hcor); int omap_ehci_hcd_stop(void); #endif /* _OMAP_COMMON_EHCI_H_ */ diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 2d5c3bc..a676b6d 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1105,6 +1105,8 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_UBISYS_P9D_EVP 3493 #define MACH_TYPE_ATDGP318 3494 #define MACH_TYPE_OMAP5_SEVM 3777 +#define MACH_TYPE_ARMADILLO_800EVA 3863 +#define MACH_TYPE_KZM9G 4140 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14222,6 +14224,30 @@ extern unsigned int __machine_arch_type; # define machine_is_omap5_sevm() (0) #endif +#ifdef CONFIG_MACH_ARMADILLO800EVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO800EVA +# endif +# define machine_is_armadillo800eva() (machine_arch_type == MACH_TYPE_ARMADILLO800EVA) +#else +# define machine_is_armadillo800eva() (0) +#endif + +#ifdef CONFIG_MACH_KZM9G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KZM9G +# endif +# define machine_is_kzm9g() (machine_arch_type == MACH_TYPE_KZM9G) +#else +# define machine_is_kzm9g() (0) +#endif + /* * These have not yet been registered */ |