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-rw-r--r--arch/arm/include/asm/arch-bcm235xx/boot0.h8
-rw-r--r--arch/arm/include/asm/arch-bcm281xx/boot0.h8
-rw-r--r--arch/arm/include/asm/arch-sunxi/boot0.h37
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h1
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu.h3
-rw-r--r--arch/arm/include/asm/arch-sunxi/dram.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h53
-rw-r--r--arch/arm/include/asm/armv8/mmu.h8
8 files changed, 69 insertions, 51 deletions
diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h b/arch/arm/include/asm/arch-bcm235xx/boot0.h
index 7e72882..a747bd3 100644
--- a/arch/arm/include/asm/arch-bcm235xx/boot0.h
+++ b/arch/arm/include/asm/arch-bcm235xx/boot0.h
@@ -4,12 +4,6 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
/* BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
- .word 0xbabeface; \
+ .word 0xbabeface
.word _end - _start
-
-#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h b/arch/arm/include/asm/arch-bcm281xx/boot0.h
index 7e72882..a747bd3 100644
--- a/arch/arm/include/asm/arch-bcm281xx/boot0.h
+++ b/arch/arm/include/asm/arch-bcm281xx/boot0.h
@@ -4,12 +4,6 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
/* BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
- .word 0xbabeface; \
+ .word 0xbabeface
.word _end - _start
-
-#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index ea5675e..9c6d82d 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -4,11 +4,36 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
+#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
/* reserve space for BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
+ b reset
.space 1532
-
-#endif /* __BOOT0_H */
+#elif defined(CONFIG_ARM_BOOT_HOOK_RMR)
+/*
+ * Switch into AArch64 if needed.
+ * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source.
+ */
+ tst x0, x0 // this is "b #0x84" in ARM
+ b reset
+ .space 0x7c
+ .word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0
+ .word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE
+ .word 0xe5810000 // str r0, [r1]
+ .word 0xf57ff04f // dsb sy
+ .word 0xf57ff06f // isb sy
+ .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR
+ .word 0xe3800003 // orr r0, r0, #3
+ .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR
+ .word 0xf57ff06f // isb sy
+ .word 0xe320f003 // wfi
+ .word 0xeafffffd // b @wfi
+ .word 0x017000a0 // writeable RVBAR mapping address
+#ifdef CONFIG_SPL_BUILD
+ .word CONFIG_SPL_TEXT_BASE
+#else
+ .word CONFIG_SYS_TEXT_BASE
+#endif
+#else
+/* normal execution */
+ b reset
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index be9fcfd..3f87672 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -322,6 +322,7 @@ struct sunxi_ccm_reg {
#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20)
#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20)
+#define CCM_DRAMCLK_CFG_SRC_PLL11 (0x1 << 20) /* A64 only */
#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20)
#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index 73583ed..6f96a97 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -13,4 +13,7 @@
#include <asm/arch/cpu_sun4i.h>
#endif
+#define SOCID_A64 0x1689
+#define SOCID_H3 0x1680
+
#endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index e0be744..53e6d47 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -24,7 +24,7 @@
#include <asm/arch/dram_sun8i_a33.h>
#elif defined(CONFIG_MACH_SUN8I_A83T)
#include <asm/arch/dram_sun8i_a83t.h>
-#elif defined(CONFIG_MACH_SUN8I_H3)
+#elif defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
#include <asm/arch/dram_sun8i_h3.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/dram_sun9i.h>
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
index d0f2b8a..25d07d9 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
@@ -15,7 +15,8 @@
struct sunxi_mctl_com_reg {
u32 cr; /* 0x00 control register */
- u8 res0[0xc]; /* 0x04 */
+ u8 res0[0x8]; /* 0x04 */
+ u32 tmr; /* 0x0c (unused on H3) */
u32 mcr[16][2]; /* 0x10 */
u32 bwcr; /* 0x90 bandwidth control register */
u32 maer; /* 0x94 master enable register */
@@ -32,7 +33,9 @@ struct sunxi_mctl_com_reg {
u32 swoffr; /* 0xc4 */
u8 res2[0x8]; /* 0xc8 */
u32 cccr; /* 0xd0 */
- u8 res3[0x72c]; /* 0xd4 */
+ u8 res3[0x54]; /* 0xd4 */
+ u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */
+ u8 res4[0x6cc]; /* 0x134 */
u32 protect; /* 0x800 */
};
@@ -81,7 +84,8 @@ struct sunxi_mctl_ctl_reg {
u32 rfshtmg; /* 0x90 refresh timing */
u32 rfshctl1; /* 0x94 */
u32 pwrtmg; /* 0x98 */
- u8 res3[0x20]; /* 0x9c */
+ u8 res3[0x1c]; /* 0x9c */
+ u32 vtfcr; /* 0xb8 (unused on H3) */
u32 dqsgmr; /* 0xbc */
u32 dtcr; /* 0xc0 */
u32 dtar[4]; /* 0xc4 */
@@ -106,20 +110,23 @@ struct sunxi_mctl_ctl_reg {
u32 perfhpr[2]; /* 0x1c4 */
u32 perflpr[2]; /* 0x1cc */
u32 perfwr[2]; /* 0x1d4 */
- u8 res8[0x2c]; /* 0x1dc */
- u32 aciocr; /* 0x208 */
- u8 res9[0xf4]; /* 0x20c */
+ u8 res8[0x24]; /* 0x1dc */
+ u32 acmdlr; /* 0x200 AC master delay line register */
+ u32 aclcdlr; /* 0x204 AC local calibrated delay line register */
+ u32 aciocr; /* 0x208 AC I/O configuration register */
+ u8 res9[0x4]; /* 0x20c */
+ u32 acbdlr[31]; /* 0x210 AC bit delay line registers */
+ u8 res10[0x74]; /* 0x28c */
struct { /* 0x300 DATX8 modules*/
- u32 mdlr; /* 0x00 */
- u32 lcdlr[3]; /* 0x04 */
- u32 iocr[11]; /* 0x10 IO configuration register */
- u32 bdlr6; /* 0x3c */
- u32 gtr; /* 0x40 */
- u32 gcr; /* 0x44 */
- u32 gsr[3]; /* 0x48 */
+ u32 mdlr; /* 0x00 master delay line register */
+ u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */
+ u32 bdlr[12]; /* 0x10 bit delay line registers */
+ u32 gtr; /* 0x40 general timing register */
+ u32 gcr; /* 0x44 general configuration register */
+ u32 gsr[3]; /* 0x48 general status registers */
u8 res0[0x2c]; /* 0x54 */
- } datx[4];
- u8 res10[0x388]; /* 0x500 */
+ } dx[4];
+ u8 res11[0x388]; /* 0x500 */
u32 upd2; /* 0x888 */
};
@@ -172,14 +179,16 @@ struct sunxi_mctl_ctl_reg {
#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */
-#define ZQCR_PWRDOWN (0x1 << 31) /* ZQ power down */
+#define ZQCR_PWRDOWN (1U << 31) /* ZQ power down */
-#define DATX_IOCR_DQ(x) (x) /* DQ0-7 IOCR index */
-#define DATX_IOCR_DM (8) /* DM IOCR index */
-#define DATX_IOCR_DQS (9) /* DQS IOCR index */
-#define DATX_IOCR_DQSN (10) /* DQSN IOCR index */
+#define ACBDLR_WRITE_DELAY(x) ((x) << 8)
-#define DATX_IOCR_WRITE_DELAY(x) ((x) << 8)
-#define DATX_IOCR_READ_DELAY(x) ((x) << 0)
+#define DXBDLR_DQ(x) (x) /* DQ0-7 BDLR index */
+#define DXBDLR_DM 8 /* DM BDLR index */
+#define DXBDLR_DQS 9 /* DQS BDLR index */
+#define DXBDLR_DQSN 10 /* DQSN BDLR index */
+
+#define DXBDLR_WRITE_DELAY(x) ((x) << 8)
+#define DXBDLR_READ_DELAY(x) ((x) << 0)
#endif /* _SUNXI_DRAM_SUN8I_H3_H */
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index aa0f3c4..e9b4cdb 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -8,14 +8,6 @@
#ifndef _ASM_ARMV8_MMU_H_
#define _ASM_ARMV8_MMU_H_
-#ifdef __ASSEMBLY__
-#define _AC(X, Y) X
-#else
-#define _AC(X, Y) (X##Y)
-#endif
-
-#define UL(x) _AC(x, UL)
-
/***************************************************************/
/*
* The following definitions are related each other, shoud be
generated by cgit v1.1 at 2024-11-05 20:59:26 +0000