diff options
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-davinci/davinci_misc.h | 69 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-davinci/hardware.h | 37 |
2 files changed, 104 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h new file mode 100644 index 0000000..347aa89 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/davinci_misc.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MISC_H +#define __MISC_H + +/* pin muxer definitions */ +#define PIN_MUX_NUM_FIELDS 8 /* Per register */ +#define PIN_MUX_FIELD_SIZE 4 /* n in bits */ +#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1) + +/* pin definition */ +struct pinmux_config { + dv_reg *mux; /* Address of mux register */ + unsigned char value; /* Value to set in field */ + unsigned char field; /* field number */ +}; + +/* pin table definition */ +struct pinmux_resource { + const struct pinmux_config *pins; + const int n_pins; +}; + +#define PINMUX_ITEM(item) { \ + .pins = item, \ + .n_pins = ARRAY_SIZE(item) \ + } + +#define HAWKBOARD_KICK0_UNLOCK 0x83e70b13 +#define HAWKBOARD_KICK1_UNLOCK 0x95a4f1e0 + +struct lpsc_resource { + const int lpsc_no; +}; + +int dvevm_read_mac_address(uint8_t *buf); +void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); +int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); +int davinci_configure_pin_mux_items(const struct pinmux_resource *item, + int n_items); +#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM) +void davinci_emac_mii_mode_sel(int mode_sel); +#endif +#if defined(CONFIG_SOC_DA8XX) +void irq_init(void); +int da8xx_configure_lpsc_items(const struct lpsc_resource *item, + const int n_items); +#endif + +#endif /* __MISC_H */ diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 3520cf8..b95fa97 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -133,7 +133,8 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_PSC1_BASE 0x01e27000 #define DAVINCI_SPI0_BASE 0x01c41000 #define DAVINCI_USB_OTG_BASE 0x01e00000 -#define DAVINCI_SPI1_BASE 0x01e12000 +#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \ + 0x01e12000 : 0x01f0e000) #define DAVINCI_GPIO_BASE 0x01e26000 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 @@ -149,7 +150,12 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 #define DAVINCI_INTC_BASE 0xfffee000 #define DAVINCI_BOOTCFG_BASE 0x01c14000 +#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18) +#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) +#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) +#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) +#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44) #endif /* CONFIG_SOC_DA8XX */ /* Power and Sleep Controller (PSC) Domains */ @@ -363,6 +369,9 @@ struct davinci_pllc_regs { #define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) #define DAVINCI_PLLC_DIV_MASK 0x1f +#define ASYNC3 get_async3_src() +#define PLL1_SYSCLK2 ((1 << 16) | 0x2) +#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3) /* Clock IDs */ enum davinci_clk_ids { DAVINCI_SPI0_CLKID = 2, @@ -379,7 +388,10 @@ int clk_get(enum davinci_clk_ids id); /* Boot config */ struct davinci_syscfg_regs { dv_reg revid; - dv_reg rsvd[71]; + dv_reg rsvd[13]; + dv_reg kick0; + dv_reg kick1; + dv_reg rsvd1[56]; dv_reg pinmux[20]; dv_reg suspsrc; dv_reg chipsig; @@ -442,6 +454,27 @@ struct davinci_uart_ctrl_regs { #define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) #define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) +static inline int cpu_is_da830(void) +{ + unsigned int jtag_id = REG(JTAG_ID_REG); + unsigned short part_no = (jtag_id >> 12) & 0xffff; + + return ((part_no == 0xb7df) ? 1 : 0); +} +static inline int cpu_is_da850(void) +{ + unsigned int jtag_id = REG(JTAG_ID_REG); + unsigned short part_no = (jtag_id >> 12) & 0xffff; + + return ((part_no == 0xb7d1) ? 1 : 0); +} + +static inline int get_async3_src(void) +{ + return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? + PLL1_SYSCLK2 : 2; +} + #endif /* CONFIG_SOC_DA8XX */ #endif /* __ASM_ARCH_HARDWARE_H */ |