diff options
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r-- | arch/arm/include/asm/arch-stm32f1/stm32.h | 8 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f4/stm32.h | 10 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f4/stm32_periph.h | 11 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f7/gpio.h | 113 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f7/gpt.h | 53 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f7/rcc.h | 64 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f7/stm32.h | 63 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f7/stm32_defs.h | 15 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 38 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 22 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-zynqmp/hardware.h | 3 |
12 files changed, 405 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h index 4094a75..1af73c5 100644 --- a/arch/arm/include/asm/arch-stm32f1/stm32.h +++ b/arch/arm/include/asm/arch-stm32f1/stm32.h @@ -24,6 +24,14 @@ #define STM32_BUS_MASK 0xFFFF0000 +#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800) +#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00) +#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000) +#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400) +#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800) +#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00) +#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000) + /* * Register maps */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 6b64d03..7d6331b 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -23,6 +23,16 @@ #define STM32_BUS_MASK 0xFFFF0000 +#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) +#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) +#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) +#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00) +#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000) +#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400) +#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800) +#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00) +#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000) + /* * Register maps */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h index a1af25c..38adc4e 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h @@ -22,6 +22,17 @@ enum periph_id { enum periph_clock { USART1_CLOCK_CFG = 0, USART2_CLOCK_CFG, + GPIO_A_CLOCK_CFG, + GPIO_B_CLOCK_CFG, + GPIO_C_CLOCK_CFG, + GPIO_D_CLOCK_CFG, + GPIO_E_CLOCK_CFG, + GPIO_F_CLOCK_CFG, + GPIO_G_CLOCK_CFG, + GPIO_H_CLOCK_CFG, + GPIO_I_CLOCK_CFG, + GPIO_J_CLOCK_CFG, + GPIO_K_CLOCK_CFG, }; #endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-stm32f7/gpio.h b/arch/arm/include/asm/arch-stm32f7/gpio.h new file mode 100644 index 0000000..2942cd9 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/gpio.h @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STM32_GPIO_H_ +#define _STM32_GPIO_H_ + +enum stm32_gpio_port { + STM32_GPIO_PORT_A = 0, + STM32_GPIO_PORT_B, + STM32_GPIO_PORT_C, + STM32_GPIO_PORT_D, + STM32_GPIO_PORT_E, + STM32_GPIO_PORT_F, + STM32_GPIO_PORT_G, + STM32_GPIO_PORT_H, + STM32_GPIO_PORT_I +}; + +enum stm32_gpio_pin { + STM32_GPIO_PIN_0 = 0, + STM32_GPIO_PIN_1, + STM32_GPIO_PIN_2, + STM32_GPIO_PIN_3, + STM32_GPIO_PIN_4, + STM32_GPIO_PIN_5, + STM32_GPIO_PIN_6, + STM32_GPIO_PIN_7, + STM32_GPIO_PIN_8, + STM32_GPIO_PIN_9, + STM32_GPIO_PIN_10, + STM32_GPIO_PIN_11, + STM32_GPIO_PIN_12, + STM32_GPIO_PIN_13, + STM32_GPIO_PIN_14, + STM32_GPIO_PIN_15 +}; + +enum stm32_gpio_mode { + STM32_GPIO_MODE_IN = 0, + STM32_GPIO_MODE_OUT, + STM32_GPIO_MODE_AF, + STM32_GPIO_MODE_AN +}; + +enum stm32_gpio_otype { + STM32_GPIO_OTYPE_PP = 0, + STM32_GPIO_OTYPE_OD +}; + +enum stm32_gpio_speed { + STM32_GPIO_SPEED_2M = 0, + STM32_GPIO_SPEED_25M, + STM32_GPIO_SPEED_50M, + STM32_GPIO_SPEED_100M +}; + +enum stm32_gpio_pupd { + STM32_GPIO_PUPD_NO = 0, + STM32_GPIO_PUPD_UP, + STM32_GPIO_PUPD_DOWN +}; + +enum stm32_gpio_af { + STM32_GPIO_AF0 = 0, + STM32_GPIO_AF1, + STM32_GPIO_AF2, + STM32_GPIO_AF3, + STM32_GPIO_AF4, + STM32_GPIO_AF5, + STM32_GPIO_AF6, + STM32_GPIO_AF7, + STM32_GPIO_AF8, + STM32_GPIO_AF9, + STM32_GPIO_AF10, + STM32_GPIO_AF11, + STM32_GPIO_AF12, + STM32_GPIO_AF13, + STM32_GPIO_AF14, + STM32_GPIO_AF15 +}; + +struct stm32_gpio_dsc { + enum stm32_gpio_port port; + enum stm32_gpio_pin pin; +}; + +struct stm32_gpio_ctl { + enum stm32_gpio_mode mode; + enum stm32_gpio_otype otype; + enum stm32_gpio_speed speed; + enum stm32_gpio_pupd pupd; + enum stm32_gpio_af af; +}; + +static inline unsigned stm32_gpio_to_port(unsigned gpio) +{ + return gpio / 16; +} + +static inline unsigned stm32_gpio_to_pin(unsigned gpio) +{ + return gpio % 16; +} + +int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc, + const struct stm32_gpio_ctl *gpio_ctl); +int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state); + +#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f7/gpt.h b/arch/arm/include/asm/arch-stm32f7/gpt.h new file mode 100644 index 0000000..903bdf6 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/gpt.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STM32_GPT_H +#define _STM32_GPT_H + +#include <asm/arch/stm32.h> + +struct gpt_regs { + u32 cr1; + u32 cr2; + u32 smcr; + u32 dier; + u32 sr; + u32 egr; + u32 ccmr1; + u32 ccmr2; + u32 ccer; + u32 cnt; + u32 psc; + u32 arr; + u32 reserved; + u32 ccr1; + u32 ccr2; + u32 ccr3; + u32 ccr4; + u32 reserved1; + u32 dcr; + u32 dmar; + u32 tim2_5_or; +}; + +struct gpt_regs *const gpt1_regs_ptr = + (struct gpt_regs *)TIM2_BASE; + +/* Timer control1 register */ +#define GPT_CR1_CEN 0x0001 +#define GPT_MODE_AUTO_RELOAD (1 << 7) + +/* Auto reload register for free running config */ +#define GPT_FREE_RUNNING 0xFFFFFFFF + +/* Timer, HZ specific defines */ +#define CONFIG_STM32_HZ 1000 + +/* Timer Event Generation registers */ +#define TIM_EGR_UG (1 << 0) + +#endif diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h new file mode 100644 index 0000000..8bfb7b6 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/rcc.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STM32_RCC_H +#define _STM32_RCC_H + +#define RCC_CR 0x00 /* clock control */ +#define RCC_PLLCFGR 0x04 /* PLL configuration */ +#define RCC_CFGR 0x08 /* clock configuration */ +#define RCC_CIR 0x0C /* clock interrupt */ +#define RCC_AHB1RSTR 0x10 /* AHB1 peripheral reset */ +#define RCC_AHB2RSTR 0x14 /* AHB2 peripheral reset */ +#define RCC_AHB3RSTR 0x18 /* AHB3 peripheral reset */ +#define RCC_APB1RSTR 0x20 /* APB1 peripheral reset */ +#define RCC_APB2RSTR 0x24 /* APB2 peripheral reset */ +#define RCC_AHB1ENR 0x30 /* AHB1 peripheral clock enable */ +#define RCC_AHB2ENR 0x34 /* AHB2 peripheral clock enable */ +#define RCC_AHB3ENR 0x38 /* AHB3 peripheral clock enable */ +#define RCC_APB1ENR 0x40 /* APB1 peripheral clock enable */ +#define RCC_APB2ENR 0x44 /* APB2 peripheral clock enable */ +#define RCC_AHB1LPENR 0x50 /* periph clk enable in low pwr mode */ +#define RCC_AHB2LPENR 0x54 /* AHB2 periph clk enable in low pwr mode */ +#define RCC_AHB3LPENR 0x58 /* AHB3 periph clk enable in low pwr mode */ +#define RCC_APB1LPENR 0x60 /* APB1 periph clk enable in low pwr mode */ +#define RCC_APB2LPENR 0x64 /* APB2 periph clk enable in low pwr mode */ +#define RCC_BDCR 0x70 /* Backup domain control */ +#define RCC_CSR 0x74 /* clock control & status */ +#define RCC_SSCGR 0x80 /* spread spectrum clock generation */ +#define RCC_PLLI2SCFGR 0x84 /* PLLI2S configuration */ +#define RCC_PLLSAICFG 0x88 /* PLLSAI configuration */ +#define RCC_DCKCFG1 0x8C /* dedicated clocks configuration register */ +#define RCC_DCKCFG2 0x90 /* dedicated clocks configuration register */ + +#define RCC_APB1ENR_TIM2EN (1 << 0) +#define RCC_APB1ENR_PWREN (1 << 28) + +/* + * RCC USART specific definitions + */ +#define RCC_ENR_USART1EN (1 << 4) +#define RCC_ENR_USART2EN (1 << 17) +#define RCC_ENR_USART3EN (1 << 18) +#define RCC_ENR_USART6EN (1 << 5) + +/* + * RCC GPIO specific definitions + */ +#define RCC_ENR_GPIO_A_EN (1 << 0) +#define RCC_ENR_GPIO_B_EN (1 << 1) +#define RCC_ENR_GPIO_C_EN (1 << 2) +#define RCC_ENR_GPIO_D_EN (1 << 3) +#define RCC_ENR_GPIO_E_EN (1 << 4) +#define RCC_ENR_GPIO_F_EN (1 << 5) +#define RCC_ENR_GPIO_G_EN (1 << 6) +#define RCC_ENR_GPIO_H_EN (1 << 7) +#define RCC_ENR_GPIO_I_EN (1 << 8) +#define RCC_ENR_GPIO_J_EN (1 << 9) +#define RCC_ENR_GPIO_K_EN (1 << 10) + +#endif diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h new file mode 100644 index 0000000..713eb2e --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +/* STM32F746 */ +#define ITCM_FLASH_BASE 0x00200000UL +#define AXIM_FLASH_BASE 0x08000000UL + +#define ITCM_SRAM_BASE 0x00000000UL +#define DTCM_SRAM_BASE 0x20000000UL +#define SRAM1_BASE 0x20010000UL +#define SRAM2_BASE 0x2004C000UL + +#define PERIPH_BASE 0x40000000UL + +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000) + +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define USART2_BASE (APB1_PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1_PERIPH_BASE + 0x4800) +#define PWR_BASE (APB1_PERIPH_BASE + 0x7000) + +#define USART1_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x1400) + +#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000) +#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400) +#define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800) +#define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00) +#define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000) +#define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400) +#define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800) +#define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00) +#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000) +#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400) +#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800) +#define RCC_BASE (AHB1_PERIPH_BASE + 0x3800) +#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00) + + +#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A0000140) + +enum clock { + CLOCK_CORE, + CLOCK_AHB, + CLOCK_APB1, + CLOCK_APB2 +}; +#define STM32_BUS_MASK 0xFFFF0000 + +int configure_clocks(void); + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_defs.h b/arch/arm/include/asm/arch-stm32f7/stm32_defs.h new file mode 100644 index 0000000..29b98ae --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/stm32_defs.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_DEFS_H__ +#define __STM32_DEFS_H__ +#include <asm/arch/stm32_periph.h> + +int clock_setup(enum periph_clock); + +#endif + diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h new file mode 100644 index 0000000..38adc4e --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + UART1_GPIOA_9_10 = 0, + UART2_GPIOD_5_6, +}; + +enum periph_clock { + USART1_CLOCK_CFG = 0, + USART2_CLOCK_CFG, + GPIO_A_CLOCK_CFG, + GPIO_B_CLOCK_CFG, + GPIO_C_CLOCK_CFG, + GPIO_D_CLOCK_CFG, + GPIO_E_CLOCK_CFG, + GPIO_F_CLOCK_CFG, + GPIO_G_CLOCK_CFG, + GPIO_H_CLOCK_CFG, + GPIO_I_CLOCK_CFG, + GPIO_J_CLOCK_CFG, + GPIO_K_CLOCK_CFG, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 554d858..9de7754 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -229,8 +229,18 @@ struct sunxi_ccm_reg { /* ahb_gate0 offsets */ #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 +#ifdef CONFIG_MACH_SUN8I_H3 +/* + * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call + * them 0 - 2 like they were called on older SoCs. + */ +#define AHB_GATE_OFFSET_USB_EHCI2 27 +#define AHB_GATE_OFFSET_USB_EHCI1 26 +#define AHB_GATE_OFFSET_USB_EHCI0 25 +#else #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 +#endif #define AHB_GATE_OFFSET_USB0 24 #define AHB_GATE_OFFSET_MCTL 14 #define AHB_GATE_OFFSET_GMAC 17 @@ -263,13 +273,25 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) #define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +#define CCM_USB_CTRL_PHY3_RST (0x1 << 3) /* There is no global phy clk gate on sun6i, define as 0 */ #define CCM_USB_CTRL_PHYGATE 0 #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) +#ifdef CONFIG_MACH_SUN8I_H3 +/* + * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call + * them 0 - 2 like they were called on older SoCs. + */ +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) +#else #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#endif #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 0cdefdc..b6e11eb 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -52,10 +52,18 @@ #define SUNXI_USB2_BASE 0x01c1c000 #endif #ifdef CONFIG_SUNXI_GEN_SUN6I +#ifdef CONFIG_MACH_SUN8I_H3 +#define SUNXI_USBPHY_BASE 0x01c19000 +#define SUNXI_USB0_BASE 0x01c1a000 +#define SUNXI_USB1_BASE 0x01c1b000 +#define SUNXI_USB2_BASE 0x01c1c000 +#define SUNXI_USB3_BASE 0x01c1d000 +#else #define SUNXI_USB0_BASE 0x01c19000 #define SUNXI_USB1_BASE 0x01c1a000 #define SUNXI_USB2_BASE 0x01c1b000 #endif +#endif #define SUNXI_CSI1_BASE 0x01c1d000 #define SUNXI_TZASC_BASE 0x01c1e000 #define SUNXI_SPI3_BASE 0x01c1f000 diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index e223988..35964d6 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -13,9 +13,6 @@ #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 #define ZYNQ_GEM_BASEADDR3 0xFF0E0000 -#define ZYNQ_SPI_BASEADDR0 0xFF040000 -#define ZYNQ_SPI_BASEADDR1 0xFF050000 - #define ZYNQ_I2C_BASEADDR0 0xFF020000 #define ZYNQ_I2C_BASEADDR1 0xFF030000 |