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-rw-r--r--arch/arm/include/asm/armv7.h33
-rw-r--r--arch/arm/include/asm/gic.h19
2 files changed, 51 insertions, 1 deletions
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 392d6a2..395444e 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -7,7 +7,6 @@
*/
#ifndef ARMV7_H
#define ARMV7_H
-#include <linux/types.h>
/* Cortex-A9 revisions */
#define MIDR_CORTEX_A9_R0P1 0x410FC091
@@ -19,6 +18,22 @@
#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
+/* Cortex-A7 revisions */
+#define MIDR_CORTEX_A7_R0P0 0x410FC070
+
+#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0
+
+/* ID_PFR1 feature fields */
+#define CPUID_ARM_SEC_SHIFT 4
+#define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT)
+#define CPUID_ARM_VIRT_SHIFT 12
+#define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT)
+#define CPUID_ARM_GENTIMER_SHIFT 16
+#define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT)
+
+/* valid bits in CBAR register / PERIPHBASE value */
+#define CBAR_MASK 0xFFFF8000
+
/* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET 0
#define CCSIDR_LINE_SIZE_MASK 0x7
@@ -41,6 +56,9 @@
#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
#define ARMV7_CLIDR_CTYPE_UNIFIED 4
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
/*
* CP15 Barrier instructions
* Please note that we have separate barrier instructions in ARMv7
@@ -58,4 +76,17 @@ void v7_outer_cache_inval_all(void);
void v7_outer_cache_flush_range(u32 start, u32 end);
void v7_outer_cache_inval_range(u32 start, u32 end);
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+
+int armv7_switch_nonsec(void);
+int armv7_switch_hyp(void);
+
+/* defined in assembly file */
+unsigned int _nonsec_init(void);
+void _smp_pen(void);
+void _switch_to_hyp(void);
+#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+
+#endif /* ! __ASSEMBLY__ */
+
#endif
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
new file mode 100644
index 0000000..a0891cc
--- /dev/null
+++ b/arch/arm/include/asm/gic.h
@@ -0,0 +1,19 @@
+#ifndef __GIC_V2_H__
+#define __GIC_V2_H__
+
+/* register offsets for the ARM generic interrupt controller (GIC) */
+
+#define GIC_DIST_OFFSET 0x1000
+#define GICD_CTLR 0x0000
+#define GICD_TYPER 0x0004
+#define GICD_IGROUPRn 0x0080
+#define GICD_SGIR 0x0F00
+
+#define GIC_CPU_OFFSET_A9 0x0100
+#define GIC_CPU_OFFSET_A15 0x2000
+#define GICC_CTLR 0x0000
+#define GICC_PMR 0x0004
+#define GICC_IAR 0x000C
+#define GICC_EOIR 0x0010
+
+#endif