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-rw-r--r--arch/arm/include/asm/arch-omap4/cpu.h48
-rw-r--r--arch/arm/include/asm/arch-omap4/omap4.h2
-rw-r--r--arch/arm/include/asm/arch-omap4/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/mmc.h71
-rw-r--r--arch/arm/include/asm/io.h46
6 files changed, 163 insertions, 7 deletions
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index 7d8aa20..c056b95 100644
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -31,6 +31,51 @@
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
+struct gpmc_cs {
+ u32 config1; /* 0x00 */
+ u32 config2; /* 0x04 */
+ u32 config3; /* 0x08 */
+ u32 config4; /* 0x0C */
+ u32 config5; /* 0x10 */
+ u32 config6; /* 0x14 */
+ u32 config7; /* 0x18 */
+ u32 nand_cmd; /* 0x1C */
+ u32 nand_adr; /* 0x20 */
+ u32 nand_dat; /* 0x24 */
+ u8 res[8]; /* blow up to 0x30 byte */
+};
+
+struct gpmc {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u8 res2[0x4];
+ u32 irqstatus; /* 0x18 */
+ u32 irqenable; /* 0x1C */
+ u8 res3[0x20];
+ u32 timeout_control; /* 0x40 */
+ u8 res4[0xC];
+ u32 config; /* 0x50 */
+ u32 status; /* 0x54 */
+ u8 res5[0x8]; /* 0x58 */
+ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
+ u8 res6[0x14]; /* 0x1E0 */
+ u32 ecc_config; /* 0x1F4 */
+ u32 ecc_control; /* 0x1F8 */
+ u32 ecc_size_config; /* 0x1FC */
+ u32 ecc1_result; /* 0x200 */
+ u32 ecc2_result; /* 0x204 */
+ u32 ecc3_result; /* 0x208 */
+ u32 ecc4_result; /* 0x20C */
+ u32 ecc5_result; /* 0x210 */
+ u32 ecc6_result; /* 0x214 */
+ u32 ecc7_result; /* 0x218 */
+ u32 ecc8_result; /* 0x21C */
+ u32 ecc9_result; /* 0x220 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
struct gptimer {
u32 tidr; /* 0x00 r */
u8 res[0xc];
@@ -86,6 +131,9 @@ struct watchdog {
#define TCLR_AR (0x1 << 1)
#define TCLR_PRE (0x1 << 5)
+/* GPMC BASE */
+#define GPMC_BASE (OMAP44XX_GPMC_BASE)
+
/* I2C base */
#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index d123d6a..5243ea8 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -62,7 +62,7 @@
#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
/* GPMC */
-#define GPMC_BASE 0x50000000
+#define OMAP44XX_GPMC_BASE 0x50000000
/*
* Hardware Register Details
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 6f4d3d5..c6fab00 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -28,6 +28,7 @@ struct omap_sysinfo {
char *board_string;
};
+void gpmc_init(void);
void watchdog_init(void);
u32 get_device_type(void);
void invalidate_dcache(u32);
diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
index 90485aa..b3af8cc 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
@@ -38,6 +38,7 @@
#define S5PC100_PWMTIMER_BASE 0xEA000000
#define S5PC100_WATCHDOG_BASE 0xEA200000
#define S5PC100_UART_BASE 0xEC000000
+#define S5PC100_MMC_BASE 0xED800000
/* S5PC110 */
#define S5PC110_GPIO_BASE 0xE0200000
@@ -45,6 +46,7 @@
#define S5PC110_WATCHDOG_BASE 0xE2700000
#define S5PC110_UART_BASE 0xE2900000
#define S5PC110_SROMC_BASE 0xE8000000
+#define S5PC110_MMC_BASE 0xEB000000
#define S5PC110_DMC0_BASE 0xF0000000
#define S5PC110_DMC1_BASE 0xF1400000
#define S5PC110_VIC0_BASE 0xF2000000
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
new file mode 100644
index 0000000..ac560c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_MMC_H_
+#define __ASM_ARCH_MMC_H_
+
+#ifndef __ASSEMBLY__
+struct s5p_mmc {
+ unsigned int sysad;
+ unsigned short blksize;
+ unsigned short blkcnt;
+ unsigned int argument;
+ unsigned short trnmod;
+ unsigned short cmdreg;
+ unsigned int rspreg0;
+ unsigned int rspreg1;
+ unsigned int rspreg2;
+ unsigned int rspreg3;
+ unsigned int bdata;
+ unsigned int prnsts;
+ unsigned char hostctl;
+ unsigned char pwrcon;
+ unsigned char blkgap;
+ unsigned char wakcon;
+ unsigned short clkcon;
+ unsigned char timeoutcon;
+ unsigned char swrst;
+ unsigned int norintsts; /* errintsts */
+ unsigned int norintstsen; /* errintstsen */
+ unsigned int norintsigen; /* errintsigen */
+ unsigned short acmd12errsts;
+ unsigned char res1[2];
+ unsigned int capareg;
+ unsigned char res2[4];
+ unsigned int maxcurr;
+ unsigned char res3[0x34];
+ unsigned int control2;
+ unsigned int control3;
+ unsigned int control4;
+ unsigned char res4[0x6e];
+ unsigned short hcver;
+ unsigned char res5[0xFFF00];
+};
+
+struct mmc_host {
+ struct s5p_mmc *reg;
+ unsigned int version; /* SDHCI spec. version */
+ unsigned int clock; /* Current clock (MHz) */
+};
+
+int s5p_mmc_init(int dev_index);
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index e8f3eb1..ff1518e 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -75,13 +75,47 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
-extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
-extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
-extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)
+{
+ uint8_t *buf = (uint8_t *)data;
+ while(bytelen--)
+ __arch_putb(*buf++, addr);
+}
+
+extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)
+{
+ uint16_t *buf = (uint16_t *)data;
+ while(wordlen--)
+ __arch_putw(*buf++, addr);
+}
+
+extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen)
+{
+ uint32_t *buf = (uint32_t *)data;
+ while(longlen--)
+ __arch_putl(*buf++, addr);
+}
-extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
-extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
-extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen)
+{
+ uint8_t *buf = (uint8_t *)data;
+ while(bytelen--)
+ *buf++ = __arch_getb(addr);
+}
+
+extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen)
+{
+ uint16_t *buf = (uint16_t *)data;
+ while(wordlen--)
+ *buf++ = __arch_getw(addr);
+}
+
+extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
+{
+ uint32_t *buf = (uint32_t *)data;
+ while(longlen--)
+ *buf++ = __arch_getl(addr);
+}
#define __raw_writeb(v,a) __arch_putb(v,a)
#define __raw_writew(v,a) __arch_putw(v,a)