diff options
Diffstat (limited to 'arch/arm/include/asm/cache.h')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 16e65c3..5400cbe 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -43,14 +43,11 @@ void dram_bank_mmu_setup(int bank); #endif /* - * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We - * use that value for aligning DMA buffers unless the board config has specified - * an alternate cache line size. + * The value of the largest data cache relevant to DMA operations shall be set + * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger + * value than found in the L1 cache but this is OK to use in terms of + * alignment. */ -#ifdef CONFIG_SYS_CACHELINE_SIZE #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 64 -#endif #endif /* _ASM_CACHE_H */ |