diff options
Diffstat (limited to 'arch/arm/include/asm/arch-omap24xx')
| -rw-r--r-- | arch/arm/include/asm/arch-omap24xx/bits.h | 48 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap24xx/clocks.h | 112 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap24xx/i2c.h | 172 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap24xx/mem.h | 156 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap24xx/mux.h | 176 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap24xx/omap2420.h | 246 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap24xx/sizes.h | 49 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap24xx/sys_info.h | 82 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap24xx/sys_proto.h | 54 |
9 files changed, 1095 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap24xx/bits.h b/arch/arm/include/asm/arch-omap24xx/bits.h new file mode 100644 index 0000000..8522335 --- /dev/null +++ b/arch/arm/include/asm/arch-omap24xx/bits.h @@ -0,0 +1,48 @@ +/* bits.h + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif diff --git a/arch/arm/include/asm/arch-omap24xx/clocks.h b/arch/arm/include/asm/arch-omap24xx/clocks.h new file mode 100644 index 0000000..2e92569 --- /dev/null +++ b/arch/arm/include/asm/arch-omap24xx/clocks.h @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_CLOCKS_H_ +#define _OMAP24XX_CLOCKS_H_ + +#define COMMIT_DIVIDERS 0x1 + +#define MODE_BYPASS_FAST 0x2 +#define APLL_LOCK 0xc +#ifdef CONFIG_APTIX +#define DPLL_LOCK 0x1 /* stay in bypass mode */ +#else +#define DPLL_LOCK 0x3 /* DPLL lock */ +#endif + +/****************************************************************************; +; PRCM Scheme II +; +; Enable clocks and DPLL for: +; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 +; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] +; DSPI=100 6 CM_CLKSEL_DSP[6:5] +; DSP_S bypass CM_CLKSEL_DSP[7] +; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] +; IVAF=100 auto +; IVAI auto +; IVA_MPU auto +; IVA_S bypass CM_CLKSEL_DSP[13] +; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] +; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=100 auto +; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] +; L4=100Mhz 6 +; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define II_DPLL_OUT_X2 0x2 /* x2 core out */ +#define II_MPU_DIV 0x2 /* mpu = core/2 */ +#define II_DSP_DIV 0x343 /* dsp & iva divider */ +#define II_GFX_DIV 0x2 +#define II_BUS_DIV 0x04601026 +#define II_DPLL_300 0x01832100 + +/****************************************************************************; +; PRCM Scheme III +; +; Enable clocks and DPLL for: +; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 +; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] +; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] +; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] +; DSP_S ACTIVATED CM_CLKSEL_DSP[7] +; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] +; IVAF=88.67 auto +; IVAI auto +; IVA_MPU auto +; IVA_S ACTIVATED CM_CLKSEL_DSP[13] +; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: +; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=88.67 auto +; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] +; L4=66.5Mhz /8 +; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define III_DPLL_OUT_X2 0x2 /* x2 core out */ +#define III_MPU_DIV 0x2 /* mpu = core/2 */ +#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ +#define III_GFX_DIV 0x2 +#define III_BUS_DIV 0x08301044 +#define III_DPLL_266 0x01885500 + +/* set defaults for boot up */ +#ifdef PRCM_CONFIG_II +# define DPLL_OUT II_DPLL_OUT_X2 +# define MPU_DIV II_MPU_DIV +# define DSP_DIV II_DSP_DIV +# define GFX_DIV II_GFX_DIV +# define BUS_DIV II_BUS_DIV +# define DPLL_VAL II_DPLL_300 +#elif PRCM_CONFIG_III +# define DPLL_OUT III_DPLL_OUT_X2 +# define MPU_DIV III_MPU_DIV +# define DSP_DIV III_DSP_DIV +# define GFX_DIV III_GFX_DIV +# define BUS_DIV III_BUS_DIV +# define DPLL_VAL III_DPLL_266 +#endif + +/* lock delay time out */ +#define LDELAY 12000000 + +#endif diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h new file mode 100644 index 0000000..19046aa --- /dev/null +++ b/arch/arm/include/asm/arch-omap24xx/i2c.h @@ -0,0 +1,172 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_I2C_H_ +#define _OMAP24XX_I2C_H_ + +#define I2C_BASE1 0x48070000 +#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */ + +#define I2C_DEFAULT_BASE I2C_BASE1 + +struct i2c { + unsigned short rev; /* 0x00 */ + unsigned short res1; + unsigned short ie; /* 0x04 */ + unsigned short res2; + unsigned short stat; /* 0x08 */ + unsigned short res3; + unsigned short iv; /* 0x0C */ + unsigned short res4[3]; + unsigned short buf; /* 0x14 */ + unsigned short res5; + unsigned short cnt; /* 0x18 */ + unsigned short res6; + unsigned short data; /* 0x1C */ + unsigned short res7; + unsigned short sysc; /* 0x20 */ + unsigned short res8; + unsigned short con; /* 0x24 */ + unsigned short res9; + unsigned short oa; /* 0x28 */ + unsigned short res10; + unsigned short sa; /* 0x2C */ + unsigned short res11; + unsigned short psc; /* 0x30 */ + unsigned short res12; + unsigned short scll; /* 0x34 */ + unsigned short res13; + unsigned short sclh; /* 0x38 */ + unsigned short res14; + unsigned short systest; /* 0x3c */ + unsigned short res15; +}; + +#define I2C_BUS_MAX 2 + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_GC_IE (1 << 5) +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_GC (1 << 5) +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ + +/* I2C Buffer Configuration Register (I2C_BUF): */ + +#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ + +/* I2C System Test Register (I2C_SYSTEST): */ + +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ +#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ + +/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */ +#define OMAP_I2C_STANDARD 100000 +#define OMAP_I2C_FAST_MODE 400000 +#define OMAP_I2C_HIGH_SPEED 3400000 + +#define SYSTEM_CLOCK_12 12000000 +#define SYSTEM_CLOCK_13 13000000 +#define SYSTEM_CLOCK_192 19200000 +#define SYSTEM_CLOCK_96 96000000 + +#ifndef I2C_IP_CLK +#define I2C_IP_CLK SYSTEM_CLOCK_96 +#endif + +#ifndef I2C_INTERNAL_SAMPLING_CLK +#define I2C_INTERNAL_SAMPLING_CLK 19200000 +#endif + +/* These are the trim values for standard and fast speed */ +#ifndef I2C_FASTSPEED_SCLL_TRIM +#define I2C_FASTSPEED_SCLL_TRIM 6 +#endif +#ifndef I2C_FASTSPEED_SCLH_TRIM +#define I2C_FASTSPEED_SCLH_TRIM 6 +#endif + +/* These are the trim values for high speed */ +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM +#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM +#endif +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM +#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM +#endif +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM +#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM +#endif +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM +#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM +#endif + +#define I2C_PSC_MAX 0x0f +#define I2C_PSC_MIN 0x00 + + +#endif diff --git a/arch/arm/include/asm/arch-omap24xx/mem.h b/arch/arm/include/asm/arch-omap24xx/mem.h new file mode 100644 index 0000000..42e8ab2 --- /dev/null +++ b/arch/arm/include/asm/arch-omap24xx/mem.h @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP24XX_MEM_H_ +#define _OMAP24XX_MEM_H_ + +#define SDRC_CS0_OSET 0x0 +#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ + +#ifndef __ASSEMBLY__ +/* struct's for holding data tables for current boards, they are getting used + early in init when NO global access are there */ +struct sdrc_data_s { + u32 sdrc_sharing; + u32 sdrc_mdcfg_0_ddr; + u32 sdrc_mdcfg_0_sdr; + u32 sdrc_actim_ctrla_0; + u32 sdrc_actim_ctrlb_0; + u32 sdrc_rfr_ctrl; + u32 sdrc_mr_0_ddr; + u32 sdrc_mr_0_sdr; + u32 sdrc_dllab_ctrl; +} /*__attribute__ ((packed))*/; +typedef struct sdrc_data_s sdrc_data_t; + +typedef enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR = 3, +} mem_t; + +#endif + +/* Slower full frequency range default timings for x32 operation*/ +#define H4_2420_SDRC_SHARING 0x00000100 +#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ +#define H4_2420_SDRC_MR_0_SDR 0x00000031 +#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ +#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ +#define H4_2420_SDRC_MR_0_DDR 0x00000032 + +#define H4_2422_SDRC_SHARING 0x00004b00 +#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */ +#define H4_2422_SDRC_MR_0_DDR 0x00000032 + +/* ES1 work around timings */ +#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ +#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 +#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ + +/* optimized timings good for current shipping parts */ +#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 +#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e +#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ +#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ +#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 +#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/ +#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */ + +#ifdef PRCM_CONFIG_II +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz +#elif PRCM_CONFIG_III +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz +#endif + + +/* GPMC settings */ +#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ +# ifdef CONFIG_SYS_NAND_BOOT +# define H4_24XX_GPMC_CONFIG1_0 0x0 +# define H4_24XX_GPMC_CONFIG2_0 0x00141400 +# define H4_24XX_GPMC_CONFIG3_0 0x00141400 +# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 +# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 +# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 +# else /* else NOR */ +# define H4_24XX_GPMC_CONFIG1_0 0x3 +# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01 +# define H4_24XX_GPMC_CONFIG3_0 0x00050502 +# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06 +# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F +# endif /* endif CONFIG_SYS_NAND_BOOT */ +# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) +# define H4_24XX_GPMC_CONFIG1_1 0x00011000 +# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00 +# define H4_24XX_GPMC_CONFIG3_1 0x00080802 +# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 +# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F +# define H4_24XX_GPMC_CONFIG6_1 0x000003C2 +# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) +#endif /* endif PRCM_CONFIG_II */ + +#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ +# ifdef CONFIG_SYS_NAND_BOOT +# define H4_24XX_GPMC_CONFIG1_0 0x0 +# define H4_24XX_GPMC_CONFIG2_0 0x00141400 +# define H4_24XX_GPMC_CONFIG3_0 0x00141400 +# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 +# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 +# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 +# else /* NOR boot */ +# define H4_24XX_GPMC_CONFIG1_0 0x3 +# define H4_24XX_GPMC_CONFIG2_0 0x00151501 +# define H4_24XX_GPMC_CONFIG3_0 0x00060602 +# define H4_24XX_GPMC_CONFIG4_0 0x10081008 +# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F +# define H4_24XX_GPMC_CONFIG6_0 0x000004c4 +# endif /* endif CONFIG_SYS_NAND_BOOT */ +# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) +# define H4_24XX_GPMC_CONFIG1_1 0x00011000 +# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01 +# define H4_24XX_GPMC_CONFIG3_1 0x00080803 +# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 +# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F +# define H4_24XX_GPMC_CONFIG6_1 0x000004C4 +# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) +#endif /* endif CONFIG_SYS_PRCM_III */ + +#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap24xx/mux.h b/arch/arm/include/asm/arch-omap24xx/mux.h new file mode 100644 index 0000000..4fdb9c6 --- /dev/null +++ b/arch/arm/include/asm/arch-omap24xx/mux.h @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP2420_MUX_H_ +#define _OMAP2420_MUX_H_ + +#ifndef __ASSEMBLY__ +typedef unsigned char uint8; +typedef unsigned int uint32; + +void muxSetupSDRC(void); +void muxSetupGPMC(void); +void muxSetupUsb0(void); +void muxSetupUsbHost(void); +void muxSetupUart3(void); +void muxSetupI2C1(void); +void muxSetupUART1(void); +void muxSetupLCD(void); +void muxSetupCamera(void); +void muxSetupMMCSD(void) ; +void muxSetupTouchScreen(void) ; +void muxSetupHDQ(void); +#endif + +#define USB_OTG_CTRL ((volatile uint32 *)0x4805E30C) + +/* Pin Muxing registers used for HDQ (Smart battery) */ +#define CONTROL_PADCONF_HDQ_SIO ((volatile unsigned char *)0x48000115) + +/* Pin Muxing registers used for GPMC */ +#define CONTROL_PADCONF_GPMC_D2_BYTE0 ((volatile unsigned char *)0x48000088) +#define CONTROL_PADCONF_GPMC_D2_BYTE1 ((volatile unsigned char *)0x48000089) +#define CONTROL_PADCONF_GPMC_D2_BYTE2 ((volatile unsigned char *)0x4800008A) +#define CONTROL_PADCONF_GPMC_D2_BYTE3 ((volatile unsigned char *)0x4800008B) + +#define CONTROL_PADCONF_GPMC_NCS0_BYTE0 ((volatile unsigned char *)0x4800008C) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE1 ((volatile unsigned char *)0x4800008D) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE2 ((volatile unsigned char *)0x4800008E) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE3 ((volatile unsigned char *)0x4800008F) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE4 (0x48000090) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE5 (0x48000091) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE6 (0x48000092) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE7 (0x48000093) + +/* Pin Muxing registers used for SDRC */ +#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0) +#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1) +#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2) +#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3) + +#define CONTROL_PADCONF_SDRC_A14_BYTE0 ((volatile unsigned char *)0x48000030) +#define CONTROL_PADCONF_SDRC_A14_BYTE1 ((volatile unsigned char *)0x48000031) +#define CONTROL_PADCONF_SDRC_A14_BYTE2 ((volatile unsigned char *)0x48000032) +#define CONTROL_PADCONF_SDRC_A14_BYTE3 ((volatile unsigned char *)0x48000033) + +/* Pin Muxing registers used for Touch Screen (SPI) */ +#define CONTROL_PADCONF_SPI1_CLK ((volatile unsigned char *)0x480000FF) +#define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100) +#define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101) +#define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102) +#define CONTROL_PADCONF_SPI1_NCS1 (0x48000103) + +#define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B) + +/* Pin Muxing registers used for MMCSD */ +#define CONTROL_PADCONF_MMC_CLKI ((volatile unsigned char *)0x480000FE) +#define CONTROL_PADCONF_MMC_CLKO ((volatile unsigned char *)0x480000F3) +#define CONTROL_PADCONF_MMC_CMD ((volatile unsigned char *)0x480000F4) +#define CONTROL_PADCONF_MMC_DAT0 ((volatile unsigned char *)0x480000F5) +#define CONTROL_PADCONF_MMC_DAT1 ((volatile unsigned char *)0x480000F6) +#define CONTROL_PADCONF_MMC_DAT2 ((volatile unsigned char *)0x480000F7) +#define CONTROL_PADCONF_MMC_DAT3 ((volatile unsigned char *)0x480000F8) +#define CONTROL_PADCONF_MMC_DAT_DIR0 ((volatile unsigned char *)0x480000F9) +#define CONTROL_PADCONF_MMC_DAT_DIR1 ((volatile unsigned char *)0x480000FA) +#define CONTROL_PADCONF_MMC_DAT_DIR2 ((volatile unsigned char *)0x480000FB) +#define CONTROL_PADCONF_MMC_DAT_DIR3 ((volatile unsigned char *)0x480000FC) +#define CONTROL_PADCONF_MMC_CMD_DIR ((volatile unsigned char *)0x480000FD) + +#define CONTROL_PADCONF_SDRC_A14 ((volatile unsigned char *)0x48000030) +#define CONTROL_PADCONF_SDRC_A13 ((volatile unsigned char *)0x48000031) + +/* Pin Muxing registers used for CAMERA */ +#define CONTROL_PADCONF_SYS_NRESWARM ((volatile unsigned char *)0x4800012B) + +#define CONTROL_PADCONF_CAM_XCLK ((volatile unsigned char *)0x480000DC) +#define CONTROL_PADCONF_CAM_LCLK ((volatile unsigned char *)0x480000DB) +#define CONTROL_PADCONF_CAM_VS ((volatile unsigned char *)0x480000DA) +#define CONTROL_PADCONF_CAM_HS ((volatile unsigned char *)0x480000D9) +#define CONTROL_PADCONF_CAM_D0 ((volatile unsigned char *)0x480000D8) +#define CONTROL_PADCONF_CAM_D1 ((volatile unsigned char *)0x480000D7) +#define CONTROL_PADCONF_CAM_D2 ((volatile unsigned char *)0x480000D6) +#define CONTROL_PADCONF_CAM_D3 ((volatile unsigned char *)0x480000D5) +#define CONTROL_PADCONF_CAM_D4 ((volatile unsigned char *)0x480000D4) +#define CONTROL_PADCONF_CAM_D5 ((volatile unsigned char *)0x480000D3) +#define CONTROL_PADCONF_CAM_D6 ((volatile unsigned char *)0x480000D2) +#define CONTROL_PADCONF_CAM_D7 ((volatile unsigned char *)0x480000D1) +#define CONTROL_PADCONF_CAM_D8 ((volatile unsigned char *)0x480000D0) +#define CONTROL_PADCONF_CAM_D9 ((volatile unsigned char *)0x480000CF) + +/* Pin Muxing registers used for LCD */ +#define CONTROL_PADCONF_DSS_D0 ((volatile unsigned char *)0x480000B3) +#define CONTROL_PADCONF_DSS_D1 ((volatile unsigned char *)0x480000B4) +#define CONTROL_PADCONF_DSS_D2 ((volatile unsigned char *)0x480000B5) +#define CONTROL_PADCONF_DSS_D3 ((volatile unsigned char *)0x480000B6) +#define CONTROL_PADCONF_DSS_D4 ((volatile unsigned char *)0x480000B7) +#define CONTROL_PADCONF_DSS_D5 ((volatile unsigned char *)0x480000B8) +#define CONTROL_PADCONF_DSS_D6 ((volatile unsigned char *)0x480000B9) +#define CONTROL_PADCONF_DSS_D7 ((volatile unsigned char *)0x480000BA) +#define CONTROL_PADCONF_DSS_D8 ((volatile unsigned char *)0x480000BB) +#define CONTROL_PADCONF_DSS_D9 ((volatile unsigned char *)0x480000BC) +#define CONTROL_PADCONF_DSS_D10 ((volatile unsigned char *)0x480000BD) +#define CONTROL_PADCONF_DSS_D11 ((volatile unsigned char *)0x480000BE) +#define CONTROL_PADCONF_DSS_D12 ((volatile unsigned char *)0x480000BF) +#define CONTROL_PADCONF_DSS_D13 ((volatile unsigned char *)0x480000C0) +#define CONTROL_PADCONF_DSS_D14 ((volatile unsigned char *)0x480000C1) +#define CONTROL_PADCONF_DSS_D15 ((volatile unsigned char *)0x480000C2) +#define CONTROL_PADCONF_DSS_D16 ((volatile unsigned char *)0x480000C3) +#define CONTROL_PADCONF_DSS_D17 ((volatile unsigned char *)0x480000C4) +#define CONTROL_PADCONF_DSS_PCLK ((volatile unsigned char *)0x480000CB) +#define CONTROL_PADCONF_DSS_VSYNC ((volatile unsigned char *)0x480000CC) +#define CONTROL_PADCONF_DSS_HSYNC ((volatile unsigned char *)0x480000CD) +#define CONTROL_PADCONF_DSS_ACBIAS ((volatile unsigned char *)0x480000CE) + +/* Pin Muxing registers used for UART1 */ +#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5) +#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6) +#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7) +#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8) + +/* Pin Muxing registers used for I2C1 */ +#define CONTROL_PADCONF_I2C1_SCL ((volatile unsigned char *)0x48000111) +#define CONTROL_PADCONF_I2C1_SDA ((volatile unsigned char *)0x48000112) + +/* Pin Muxing registres used for USB0. */ +#define CONTROL_PADCONF_USB0_PUEN ((volatile uint8 *)0x4800011D) +#define CONTROL_PADCONF_USB0_VP ((volatile uint8 *)0x4800011E) +#define CONTROL_PADCONF_USB0_VM ((volatile uint8 *)0x4800011F) +#define CONTROL_PADCONF_USB0_RCV ((volatile uint8 *)0x48000120) +#define CONTROL_PADCONF_USB0_TXEN ((volatile uint8 *)0x48000121) +#define CONTROL_PADCONF_USB0_SE0 ((volatile uint8 *)0x48000122) +#define CONTROL_PADCONF_USB0_DAT ((volatile uint8 *)0x48000123) + +/* Pin Muxing registres used for USB1. */ +#define CONTROL_PADCONF_USB1_RCV (0x480000EB) +#define CONTROL_PADCONF_USB1_TXEN (0x480000EC) + +/* Pin Muxing registers used for UART3/IRDA */ +#define CONTROL_PADCONF_UART3_TX_IRTX ((volatile uint8 *)0x48000118) +#define CONTROL_PADCONF_UART3_RX_IRRX ((volatile uint8 *)0x48000119) + +/* Pin Muxing registers used for GPIO */ +#define CONTROL_PADCONF_GPIO69 (0x480000ED) +#define CONTROL_PADCONF_GPIO70 (0x480000EE) +#define CONTROL_PADCONF_GPIO102 (0x48000116) +#define CONTROL_PADCONF_GPIO103 (0x48000117) +#define CONTROL_PADCONF_GPIO104 (0x48000118) +#define CONTROL_PADCONF_GPIO105 (0x48000119) + +#endif diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h new file mode 100644 index 0000000..0c11bec --- /dev/null +++ b/arch/arm/include/asm/arch-omap24xx/omap2420.h @@ -0,0 +1,246 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP2420_SYS_H_ +#define _OMAP2420_SYS_H_ + +#include <asm/arch/sizes.h> + +/* + * 2420 specific Section + */ + +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 +/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */ + +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 + +/* CONTROL */ +#define OMAP2420_CTRL_BASE (0x48000000) +#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) + +/* device type */ +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* TAP information */ +#define OMAP2420_TAP_BASE (0x48014000) +#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) + +/* GPMC */ +#define OMAP2420_GPMC_BASE (0x6800A000) +#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) +#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) +#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) +#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) +#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) +#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) +#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) +#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) +#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) +#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) +#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) +#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) +#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) +#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) +#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) +#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) +#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) +#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) +#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) +#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) +#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) +#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) +#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) +#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) +#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) +#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) +#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) +#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) +#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) +#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) + +/* SMS */ +#define OMAP2420_SMS_BASE 0x68008000 +#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) +#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0) +# define BURSTCOMPLETE_GROUP7 BIT31 + +/* SDRC */ +#define OMAP2420_SDRC_BASE 0x68009000 +#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) +#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) +#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) +#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) +#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) +#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) +#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) +#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) +#define OMAP2420_SDRC_CS0 0x80000000 +#define OMAP2420_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + + +/* UART */ +#define OMAP2420_UART1 0x4806A000 +#define OMAP2420_UART2 0x4806C000 +#define OMAP2420_UART3 0x4806E000 + +/* General Purpose Timers */ +#define OMAP2420_GPT1 0x48028000 +#define OMAP2420_GPT2 0x4802A000 +#define OMAP2420_GPT3 0x48078000 +#define OMAP2420_GPT4 0x4807A000 +#define OMAP2420_GPT5 0x4807C000 +#define OMAP2420_GPT6 0x4807E000 +#define OMAP2420_GPT7 0x48080000 +#define OMAP2420_GPT8 0x48082000 +#define OMAP2420_GPT9 0x48084000 +#define OMAP2420_GPT10 0x48086000 +#define OMAP2420_GPT11 0x48088000 +#define OMAP2420_GPT12 0x4808A000 + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE 0x48020000 +#define WD2_BASE 0x48022000 +#define WD3_BASE 0x48024000 +#define WD4_BASE 0x48026000 +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define OMAP2420_CM_BASE 0x48008000 +#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) +#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) +#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) +#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) +#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) +#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) +#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) +#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) +#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) +#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) +#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) +#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) +#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) +#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) +#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) +#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) + +/* + * H4 specific Section + */ + +/* + * The 2420's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + */ +#if defined(CONFIG_OMAP2420H4) +/* GPMC */ +#ifdef CONFIG_VIRTIO_A /* Pre version B */ +# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x04000000 /* debug board */ +# define H4_CS2_BASE 0x0A000000 /* wifi board */ +#else +# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x08000000 /* debug board */ +# define H4_CS2_BASE 0x0A000000 /* wifi board */ +#endif + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +/* FPGA on Debug board.*/ +#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) +#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) +#endif /* endif CONFIG_2420H4 */ + +#if defined(CONFIG_APOLLON) +#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */ +#define APOLLON_CS1_BASE 0x08000000 /* ethernet */ +#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */ +#define APOLLON_CS3_BASE 0x18000000 /* NOR */ + +#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b) +#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c) +#endif /* endif CONFIG_APOLLON */ + +/* Common */ +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + +#endif diff --git a/arch/arm/include/asm/arch-omap24xx/sizes.h b/arch/arm/include/asm/arch-omap24xx/sizes.h new file mode 100644 index 0000000..aaba18f --- /dev/null +++ b/arch/arm/include/asm/arch-omap24xx/sizes.h @@ -0,0 +1,49 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_31M 0x01F00000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/arch/arm/include/asm/arch-omap24xx/sys_info.h b/arch/arm/include/asm/arch-omap24xx/sys_info.h new file mode 100644 index 0000000..53c231a --- /dev/null +++ b/arch/arm/include/asm/arch-omap24xx/sys_info.h @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP24XX_SYS_INFO_H_ +#define _OMAP24XX_SYS_INFO_H_ + +typedef struct h4_system_data { + /* base board info */ + u32 base_b_rev; /* rev from base board i2c */ + /* cpu board info */ + u32 cpu_b_rev; /* rev from cpu board i2c */ + u32 cpu_b_mux; /* mux type on daughter board */ + u32 cpu_b_ddr_type; /* mem type */ + u32 cpu_b_ddr_speed; /* ddr speed rating */ + u32 cpu_b_switches; /* boot ctrl switch settings */ + /* cpu info */ + u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ + u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ +} h4_sys_data; + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_2420 0x2420 +#define CPU_2422 0x2422 /* 2420 + 64M stacked */ +#define CPU_2423 0x2423 /* 2420 + 96M stacked */ + +#define CPU_2422_ES1 1 +#define CPU_2422_ES2 2 +#define CPU_2420_ES1 1 +#define CPU_2420_ES2 2 +#define CPU_2420_2422_ES1 1 + +#define CPU_2420_CHIPID 0x0B5D9000 +#define CPU_24XX_ID_MASK 0x0FFFF000 +#define CPU_242X_REV_MASK 0xF0000000 +#define CPU_242X_PID_MASK 0x000F0000 + +#define BOARD_H4_MENELAUS 1 +#define BOARD_H4_SDP 2 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ + +#endif diff --git a/arch/arm/include/asm/arch-omap24xx/sys_proto.h b/arch/arm/include/asm/arch-omap24xx/sys_proto.h new file mode 100644 index 0000000..9d8e5b2 --- /dev/null +++ b/arch/arm/include/asm/arch-omap24xx/sys_proto.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_SYS_PROTO_H_ +#define _OMAP24XX_SYS_PROTO_H_ + +void prcm_init(void); +void memif_init(void); +void sdrc_init(void); +void do_sdrc_init(u32,u32); +void gpmc_init(void); + +void ether_init(void); +void watchdog_init(void); +void set_muxconf_regs(void); +void peripheral_enable(void); + +u32 get_cpu_type(void); +u32 get_cpu_rev(void); +u32 get_mem_type(void); +u32 get_sysboot_value(void); +u32 get_gpmc0_base(void); +u32 is_gpmc_muxed(void); +u32 get_gpmc0_type(void); +u32 get_gpmc0_width(void); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); +u32 get_board_type(void); +void display_board_info(u32); +void update_mux(u32,u32); +u32 get_sdr_cs_size(u32 offset); + +u32 running_in_sdram(void); +u32 running_in_sram(void); +u32 running_in_flash(void); +u32 running_from_internal_boot(void); +u32 get_device_type(void); +#endif |