diff options
Diffstat (limited to 'arch/arm/include/asm/arch-exynos')
-rw-r--r-- | arch/arm/include/asm/arch-exynos/clk.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/clock.h | 237 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/cpu.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/dmc.h | 65 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/dp.h | 751 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/dp_info.h | 214 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/fb.h | 27 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/gpio.h | 7 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/mmc.h | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/power.h | 5 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/pwm_backlight.h | 34 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/spl.h | 97 |
12 files changed, 1333 insertions, 112 deletions
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 72dc655..5529025 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -27,6 +27,7 @@ #define EPLL 2 #define HPLL 3 #define VPLL 4 +#define BPLL 5 unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 50da958..fce38ef 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -273,8 +273,7 @@ struct exynos5_clock { unsigned int clkout_cmu_cpu_div_stat; unsigned char res8[0x5f8]; unsigned int armclk_stopctrl; - unsigned int atclk_stopctrl; - unsigned char res9[0x8]; + unsigned char res9[0x0c]; unsigned int parityfail_status; unsigned int parityfail_clear; unsigned char res10[0x8]; @@ -323,259 +322,283 @@ struct exynos5_clock { unsigned char res19[0xf8]; unsigned int div_core0; unsigned int div_core1; - unsigned char res20[0xf8]; + unsigned int div_sysrgt; + unsigned char res20[0xf4]; unsigned int div_stat_core0; unsigned int div_stat_core1; - unsigned char res21[0x2f8]; + unsigned int div_stat_sysrgt; + unsigned char res21[0x2f4]; unsigned int gate_ip_core; - unsigned char res22[0xfc]; + unsigned int gate_ip_sysrgt; + unsigned char res22[0x8]; + unsigned int c2c_monitor; + unsigned char res23[0xec]; unsigned int clkout_cmu_core; unsigned int clkout_cmu_core_div_stat; - unsigned char res23[0x5f8]; + unsigned char res24[0x5f8]; unsigned int dcgidx_map0; unsigned int dcgidx_map1; unsigned int dcgidx_map2; - unsigned char res24[0x14]; + unsigned char res25[0x14]; unsigned int dcgperf_map0; unsigned int dcgperf_map1; - unsigned char res25[0x18]; + unsigned char res26[0x18]; unsigned int dvcidx_map; - unsigned char res26[0x1c]; + unsigned char res27[0x1c]; unsigned int freq_cpu; unsigned int freq_dpm; - unsigned char res27[0x18]; + unsigned char res28[0x18]; unsigned int dvsemclk_en; unsigned int maxperf; - unsigned char res28[0x3478]; + unsigned char res29[0xf78]; + unsigned int c2c_config; + unsigned char res30[0x24fc]; unsigned int div_acp; - unsigned char res29[0xfc]; + unsigned char res31[0xfc]; unsigned int div_stat_acp; - unsigned char res30[0x1fc]; + unsigned char res32[0x1fc]; unsigned int gate_ip_acp; - unsigned char res31[0x1fc]; + unsigned char res33[0xfc]; + unsigned int div_syslft; + unsigned char res34[0xc]; + unsigned int div_stat_syslft; + unsigned char res35[0x1c]; + unsigned int gate_ip_syslft; + unsigned char res36[0xcc]; unsigned int clkout_cmu_acp; unsigned int clkout_cmu_acp_div_stat; - unsigned char res32[0x38f8]; + unsigned char res37[0x8]; + unsigned int ufmc_config; + unsigned char res38[0x38ec]; unsigned int div_isp0; unsigned int div_isp1; unsigned int div_isp2; - unsigned char res33[0xf4]; + unsigned char res39[0xf4]; unsigned int div_stat_isp0; unsigned int div_stat_isp1; unsigned int div_stat_isp2; - unsigned char res34[0x3f4]; + unsigned char res40[0x3f4]; unsigned int gate_ip_isp0; unsigned int gate_ip_isp1; - unsigned char res35[0xf8]; + unsigned char res41[0xf8]; unsigned int gate_sclk_isp; - unsigned char res36[0xc]; + unsigned char res42[0xc]; unsigned int mcuisp_pwr_ctrl; - unsigned char res37[0xec]; + unsigned char res43[0xec]; unsigned int clkout_cmu_isp; unsigned int clkout_cmu_isp_div_stat; - unsigned char res38[0x3618]; + unsigned char res44[0x3618]; unsigned int cpll_lock; - unsigned char res39[0xc]; + unsigned char res45[0xc]; unsigned int epll_lock; - unsigned char res40[0xc]; + unsigned char res46[0xc]; unsigned int vpll_lock; - unsigned char res41[0xdc]; + unsigned char res47[0xc]; + unsigned int gpll_lock; + unsigned char res48[0xcc]; unsigned int cpll_con0; unsigned int cpll_con1; - unsigned char res42[0x8]; + unsigned char res49[0x8]; unsigned int epll_con0; unsigned int epll_con1; unsigned int epll_con2; - unsigned char res43[0x4]; + unsigned char res50[0x4]; unsigned int vpll_con0; unsigned int vpll_con1; unsigned int vpll_con2; - unsigned char res44[0xc4]; + unsigned char res51[0x4]; + unsigned int gpll_con0; + unsigned int gpll_con1; + unsigned char res52[0xb8]; unsigned int src_top0; unsigned int src_top1; unsigned int src_top2; unsigned int src_top3; unsigned int src_gscl; - unsigned int src_disp0_0; - unsigned int src_disp0_1; + unsigned char res53[0x8]; unsigned int src_disp1_0; - unsigned int src_disp1_1; - unsigned char res46[0xc]; + unsigned char res54[0x10]; unsigned int src_mau; unsigned int src_fsys; - unsigned char res47[0x8]; + unsigned int src_gen; + unsigned char res55[0x4]; unsigned int src_peric0; unsigned int src_peric1; - unsigned char res48[0x18]; + unsigned char res56[0x18]; unsigned int sclk_src_isp; - unsigned char res49[0x9c]; + unsigned char res57[0x9c]; unsigned int src_mask_top; - unsigned char res50[0xc]; + unsigned char res58[0xc]; unsigned int src_mask_gscl; - unsigned int src_mask_disp0_0; - unsigned int src_mask_disp0_1; + unsigned char res59[0x8]; unsigned int src_mask_disp1_0; - unsigned int src_mask_disp1_1; - unsigned int src_mask_maudio; - unsigned char res52[0x8]; + unsigned char res60[0x4]; + unsigned int src_mask_mau; + unsigned char res61[0x8]; unsigned int src_mask_fsys; - unsigned char res53[0xc]; + unsigned int src_mask_gen; + unsigned char res62[0x8]; unsigned int src_mask_peric0; unsigned int src_mask_peric1; - unsigned char res54[0x18]; + unsigned char res63[0x18]; unsigned int src_mask_isp; - unsigned char res55[0x9c]; + unsigned char res67[0x9c]; unsigned int mux_stat_top0; unsigned int mux_stat_top1; unsigned int mux_stat_top2; unsigned int mux_stat_top3; - unsigned char res56[0xf0]; + unsigned char res68[0xf0]; unsigned int div_top0; unsigned int div_top1; - unsigned char res57[0x8]; + unsigned char res69[0x8]; unsigned int div_gscl; - unsigned int div_disp0_0; - unsigned int div_disp0_1; + unsigned char res70[0x8]; unsigned int div_disp1_0; - unsigned int div_disp1_1; - unsigned char res59[0x8]; + unsigned char res71[0xc]; unsigned int div_gen; - unsigned char res60[0x4]; + unsigned char res72[0x4]; unsigned int div_mau; unsigned int div_fsys0; unsigned int div_fsys1; unsigned int div_fsys2; - unsigned int div_fsys3; + unsigned char res73[0x4]; unsigned int div_peric0; unsigned int div_peric1; unsigned int div_peric2; unsigned int div_peric3; unsigned int div_peric4; unsigned int div_peric5; - unsigned char res61[0x10]; + unsigned char res74[0x10]; unsigned int sclk_div_isp; - unsigned char res62[0xc]; + unsigned char res75[0xc]; unsigned int div2_ratio0; unsigned int div2_ratio1; - unsigned char res63[0x8]; + unsigned char res76[0x8]; unsigned int div4_ratio; - unsigned char res64[0x6c]; + unsigned char res77[0x6c]; unsigned int div_stat_top0; unsigned int div_stat_top1; - unsigned char res65[0x8]; + unsigned char res78[0x8]; unsigned int div_stat_gscl; - unsigned int div_stat_disp0_0; - unsigned int div_stat_disp0_1; + unsigned char res79[0x8]; unsigned int div_stat_disp1_0; - unsigned int div_stat_disp1_1; - unsigned char res67[0x8]; + unsigned char res80[0xc]; unsigned int div_stat_gen; - unsigned char res68[0x4]; - unsigned int div_stat_maudio; + unsigned char res81[0x4]; + unsigned int div_stat_mau; unsigned int div_stat_fsys0; unsigned int div_stat_fsys1; unsigned int div_stat_fsys2; - unsigned int div_stat_fsys3; + unsigned char res82[0x4]; unsigned int div_stat_peric0; unsigned int div_stat_peric1; unsigned int div_stat_peric2; unsigned int div_stat_peric3; unsigned int div_stat_peric4; unsigned int div_stat_peric5; - unsigned char res69[0x10]; + unsigned char res83[0x10]; unsigned int sclk_div_stat_isp; - unsigned char res70[0xc]; + unsigned char res84[0xc]; unsigned int div2_stat0; unsigned int div2_stat1; - unsigned char res71[0x8]; + unsigned char res85[0x8]; unsigned int div4_stat; - unsigned char res72[0x180]; - unsigned int gate_top_sclk_disp0; + unsigned char res86[0x184]; unsigned int gate_top_sclk_disp1; unsigned int gate_top_sclk_gen; - unsigned char res74[0xc]; + unsigned char res87[0xc]; unsigned int gate_top_sclk_mau; unsigned int gate_top_sclk_fsys; - unsigned char res75[0xc]; + unsigned char res88[0xc]; unsigned int gate_top_sclk_peric; - unsigned char res76[0x1c]; + unsigned char res89[0x1c]; unsigned int gate_top_sclk_isp; - unsigned char res77[0xac]; + unsigned char res90[0xac]; unsigned int gate_ip_gscl; - unsigned int gate_ip_disp0; + unsigned char res91[0x4]; unsigned int gate_ip_disp1; unsigned int gate_ip_mfc; unsigned int gate_ip_g3d; unsigned int gate_ip_gen; - unsigned char res79[0xc]; + unsigned char res92[0xc]; unsigned int gate_ip_fsys; - unsigned char res80[0x4]; - unsigned int gate_ip_gps; + unsigned char res93[0x8]; unsigned int gate_ip_peric; - unsigned char res81[0xc]; + unsigned char res94[0xc]; unsigned int gate_ip_peris; - unsigned char res82[0x1c]; + unsigned char res95[0x1c]; unsigned int gate_block; - unsigned char res83[0x7c]; + unsigned char res96[0x1c]; + unsigned int mcuiop_pwr_ctrl; + unsigned char res97[0x5c]; unsigned int clkout_cmu_top; unsigned int clkout_cmu_top_div_stat; - unsigned char res84[0x37f8]; + unsigned char res98[0x37f8]; unsigned int src_lex; - unsigned char res85[0x2fc]; + unsigned char res99[0x1fc]; + unsigned int mux_stat_lex; + unsigned char res100[0xfc]; unsigned int div_lex; - unsigned char res86[0xfc]; + unsigned char res101[0xfc]; unsigned int div_stat_lex; - unsigned char res87[0x1fc]; + unsigned char res102[0x1fc]; unsigned int gate_ip_lex; - unsigned char res88[0x1fc]; + unsigned char res103[0x1fc]; unsigned int clkout_cmu_lex; unsigned int clkout_cmu_lex_div_stat; - unsigned char res89[0x3af8]; + unsigned char res104[0x3af8]; unsigned int div_r0x; - unsigned char res90[0xfc]; + unsigned char res105[0xfc]; unsigned int div_stat_r0x; - unsigned char res91[0x1fc]; + unsigned char res106[0x1fc]; unsigned int gate_ip_r0x; - unsigned char res92[0x1fc]; + unsigned char res107[0x1fc]; unsigned int clkout_cmu_r0x; unsigned int clkout_cmu_r0x_div_stat; - unsigned char res94[0x3af8]; + unsigned char res108[0x3af8]; unsigned int div_r1x; - unsigned char res95[0xfc]; + unsigned char res109[0xfc]; unsigned int div_stat_r1x; - unsigned char res96[0x1fc]; + unsigned char res110[0x1fc]; unsigned int gate_ip_r1x; - unsigned char res97[0x1fc]; + unsigned char res111[0x1fc]; unsigned int clkout_cmu_r1x; unsigned int clkout_cmu_r1x_div_stat; - unsigned char res98[0x3608]; + unsigned char res112[0x3608]; unsigned int bpll_lock; - unsigned char res99[0xfc]; + unsigned char res113[0xfc]; unsigned int bpll_con0; unsigned int bpll_con1; - unsigned char res100[0xe8]; + unsigned char res114[0xe8]; unsigned int src_cdrex; - unsigned char res101[0x1fc]; + unsigned char res115[0x1fc]; unsigned int mux_stat_cdrex; - unsigned char res102[0xfc]; + unsigned char res116[0xfc]; unsigned int div_cdrex; - unsigned int div_cdrex2; - unsigned char res103[0xf8]; + unsigned char res117[0xfc]; unsigned int div_stat_cdrex; - unsigned char res104[0x2fc]; + unsigned char res118[0x2fc]; unsigned int gate_ip_cdrex; - unsigned char res105[0xc]; - unsigned int c2c_monitor; - unsigned int dmc_pwr_ctrl; - unsigned char res106[0x4]; + unsigned char res119[0x10]; + unsigned int dmc_freq_ctrl; + unsigned char res120[0x4]; unsigned int drex2_pause; - unsigned char res107[0xe0]; + unsigned char res121[0xe0]; unsigned int clkout_cmu_cdrex; unsigned int clkout_cmu_cdrex_div_stat; - unsigned char res108[0x8]; + unsigned char res122[0x8]; unsigned int lpddr3phy_ctrl; - unsigned char res109[0xf5f8]; + unsigned int lpddr3phy_con0; + unsigned int lpddr3phy_con1; + unsigned int lpddr3phy_con2; + unsigned int lpddr3phy_con3; + unsigned int pll_div2_sel; + unsigned char res123[0xf5d8]; }; #endif +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 +#define BPLL_FOUT_SEL_SHIFT 0 +#define BPLL_FOUT_SEL_MASK 0x1 #endif diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 0e6ea87..2cd4ae1 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -56,6 +56,7 @@ #define EXYNOS4_USBPHY_CONTROL 0x10020704 #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE /* EXYNOS5 */ #define EXYNOS5_I2C_SPACING 0x10000 @@ -83,6 +84,7 @@ #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5_GPIO_PART2_BASE 0x13400000 #define EXYNOS5_FIMD_BASE 0x14400000 +#define EXYNOS5_DP_BASE 0x145B0000 #define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE @@ -150,6 +152,7 @@ static inline unsigned int samsung_get_base_##device(void) \ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) +SAMSUNG_BASE(dp, DP_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) SAMSUNG_BASE(fimd, FIMD_BASE) SAMSUNG_BASE(i2c, I2C_BASE) diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index bd52d16..f65c676 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -251,5 +251,70 @@ struct exynos5_phy_control { unsigned int phy_con41; unsigned int phy_con42; }; + +enum ddr_mode { + DDR_MODE_DDR2, + DDR_MODE_DDR3, + DDR_MODE_LPDDR2, + DDR_MODE_LPDDR3, + + DDR_MODE_COUNT, +}; + +enum mem_manuf { + MEM_MANUF_AUTODETECT, + MEM_MANUF_ELPIDA, + MEM_MANUF_SAMSUNG, + + MEM_MANUF_COUNT, +}; + +/* CONCONTROL register fields */ +#define CONCONTROL_DFI_INIT_START_SHIFT 28 +#define CONCONTROL_RD_FETCH_SHIFT 12 +#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) +#define CONCONTROL_AREF_EN_SHIFT 5 + +/* PRECHCONFIG register field */ +#define PRECHCONFIG_TP_CNT_SHIFT 24 + +/* PWRDNCONFIG register field */ +#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0 +#define PWRDNCONFIG_DSREF_CYC_SHIFT 16 + +/* PHY_CON0 register fields */ +#define PHY_CON0_T_WRRDCMD_SHIFT 17 +#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) +#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 + +/* PHY_CON1 register fields */ +#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 + +/* PHY_CON12 register fields */ +#define PHY_CON12_CTRL_START_POINT_SHIFT 24 +#define PHY_CON12_CTRL_INC_SHIFT 16 +#define PHY_CON12_CTRL_FORCE_SHIFT 8 +#define PHY_CON12_CTRL_START_SHIFT 6 +#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT) +#define PHY_CON12_CTRL_DLL_ON_SHIFT 5 +#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT) +#define PHY_CON12_CTRL_REF_SHIFT 1 + +/* PHY_CON16 register fields */ +#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24 +#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT) + +#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21 +#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT) + +#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19) + +/* PHY_CON42 register fields */ +#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 +#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT) + +#define PHY_CON42_CTRL_RDLAT_SHIFT 0 +#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT) + #endif #endif diff --git a/arch/arm/include/asm/arch-exynos/dp.h b/arch/arm/include/asm/arch-exynos/dp.h new file mode 100644 index 0000000..69c65f7 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dp.h @@ -0,0 +1,751 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_DP_H_ +#define __ASM_ARM_ARCH_DP_H_ + +#ifndef __ASSEMBLY__ + +struct exynos_dp { + unsigned char res1[0x10]; + unsigned int tx_version; + unsigned int tx_sw_reset; + unsigned int func_en1; + unsigned int func_en2; + unsigned int video_ctl1; + unsigned int video_ctl2; + unsigned int video_ctl3; + unsigned int video_ctl4; + unsigned int color_blue_cb; + unsigned int color_green_y; + unsigned int color_red_cr; + unsigned int video_ctl8; + unsigned char res2[0x4]; + unsigned int video_ctl10; + unsigned int total_ln_cfg_l; + unsigned int total_ln_cfg_h; + unsigned int active_ln_cfg_l; + unsigned int active_ln_cfg_h; + unsigned int vfp_cfg; + unsigned int vsw_cfg; + unsigned int vbp_cfg; + unsigned int total_pix_cfg_l; + unsigned int total_pix_cfg_h; + unsigned int active_pix_cfg_l; + unsigned int active_pix_cfg_h; + unsigned int hfp_cfg_l; + unsigned int hfp_cfg_h; + unsigned int hsw_cfg_l; + unsigned int hsw_cfg_h; + unsigned int hbp_cfg_l; + unsigned int hbp_cfg_h; + unsigned int video_status; + unsigned int total_ln_sta_l; + unsigned int total_ln_sta_h; + unsigned int active_ln_sta_l; + unsigned int active_ln_sta_h; + + unsigned int vfp_sta; + unsigned int vsw_sta; + unsigned int vbp_sta; + + unsigned int total_pix_sta_l; + unsigned int total_pix_sta_h; + unsigned int active_pix_sta_l; + unsigned int active_pix_sta_h; + + unsigned int hfp_sta_l; + unsigned int hfp_sta_h; + unsigned int hsw_sta_l; + unsigned int hsw_sta_h; + unsigned int hbp_sta_l; + unsigned int hbp_sta_h; + + unsigned char res3[0x288]; + + unsigned int lane_map; + unsigned char res4[0x10]; + unsigned int analog_ctl1; + unsigned int analog_ctl2; + unsigned int analog_ctl3; + + unsigned int pll_filter_ctl1; + unsigned int amp_tuning_ctl; + unsigned char res5[0xc]; + + unsigned int aux_hw_retry_ctl; + unsigned char res6[0x2c]; + unsigned int int_state; + unsigned int common_int_sta1; + unsigned int common_int_sta2; + unsigned int common_int_sta3; + unsigned int common_int_sta4; + unsigned char res7[0x8]; + + unsigned int int_sta; + unsigned char res8[0x1c]; + unsigned int int_ctl; + unsigned char res9[0x200]; + unsigned int sys_ctl1; + unsigned int sys_ctl2; + unsigned int sys_ctl3; + unsigned int sys_ctl4; + unsigned int vid_ctl; + unsigned char res10[0x2c]; + unsigned int pkt_send_ctl; + unsigned char res[0x4]; + unsigned int hdcp_ctl; + unsigned char res11[0x34]; + unsigned int link_bw_set; + + unsigned int lane_count_set; + unsigned int training_ptn_set; + unsigned int ln0_link_training_ctl; + unsigned int ln1_link_training_ctl; + unsigned int ln2_link_training_ctl; + unsigned int ln3_link_training_ctl; + unsigned int dn_spread_ctl; + unsigned int hw_link_training_ctl; + unsigned char res12[0x1c]; + + unsigned int debug_ctl; + unsigned int hpd_deglitch_l; + unsigned int hpd_deglitch_h; + + unsigned char res13[0x14]; + unsigned int link_debug_ctl; + + unsigned char res14[0x1c]; + + unsigned int m_vid0; + unsigned int m_vid1; + unsigned int m_vid2; + unsigned int n_vid0; + unsigned int n_vid1; + unsigned int n_vid2; + unsigned int m_vid_mon; + unsigned int pll_ctl; + unsigned int phy_pd; + unsigned int phy_test; + unsigned char res15[0x8]; + + unsigned int video_fifo_thrd; + unsigned char res16[0x8]; + unsigned int audio_margin; + + unsigned int dn_spread_ctl1; + unsigned int dn_spread_ctl2; + unsigned char res17[0x18]; + unsigned int m_cal_ctl; + unsigned int m_vid_gen_filter_th; + unsigned char res18[0x10]; + unsigned int m_aud_gen_filter_th; + unsigned char res50[0x4]; + + unsigned int aux_ch_sta; + unsigned int aux_err_num; + unsigned int aux_ch_defer_ctl; + unsigned int aux_rx_comm; + unsigned int buffer_data_ctl; + + unsigned int aux_ch_ctl1; + unsigned int aux_addr_7_0; + unsigned int aux_addr_15_8; + unsigned int aux_addr_19_16; + unsigned int aux_ch_ctl2; + unsigned char res19[0x18]; + unsigned int buf_data0; + unsigned char res20[0x3c]; + + unsigned int soc_general_ctl; + unsigned char res21[0x8c]; + unsigned int crc_con; + unsigned int crc_result; + unsigned char res22[0x8]; + + unsigned int common_int_mask1; + unsigned int common_int_mask2; + unsigned int common_int_mask3; + unsigned int common_int_mask4; + unsigned int int_sta_mask1; + unsigned int int_sta_mask2; + unsigned int int_sta_mask3; + unsigned int int_sta_mask4; + unsigned int int_sta_mask; + unsigned int crc_result2; + unsigned int scrambler_reset_cnt; + + unsigned int pn_inv; + unsigned int psr_config; + unsigned int psr_command0; + unsigned int psr_command1; + unsigned int psr_crc_mon0; + unsigned int psr_crc_mon1; + + unsigned char res24[0x30]; + unsigned int phy_bist_ctrl; + unsigned char res25[0xc]; + unsigned int phy_ctrl; + unsigned char res26[0x1c]; + unsigned int test_pattern_gen_en; + unsigned int test_pattern_gen_ctrl; +}; + +#endif /* __ASSEMBLY__ */ + +/* For DP VIDEO CTL 1 */ +#define VIDEO_EN_MASK (0x01 << 7) +#define VIDEO_MUTE_MASK (0x01 << 6) + +/* For DP VIDEO CTL 4 */ +#define VIDEO_BIST_MASK (0x1 << 3) + +/* EXYNOS_DP_ANALOG_CTL_1 */ +#define SEL_BG_NEW_BANDGAP (0x0 << 6) +#define SEL_BG_INTERNAL_RESISTOR (0x1 << 6) +#define TX_TERMINAL_CTRL_73_OHM (0x0 << 4) +#define TX_TERMINAL_CTRL_61_OHM (0x1 << 4) +#define TX_TERMINAL_CTRL_50_OHM (0x2 << 4) +#define TX_TERMINAL_CTRL_45_OHM (0x3 << 4) +#define SWING_A_30PER_G_INCREASE (0x1 << 3) +#define SWING_A_30PER_G_NORMAL (0x0 << 3) + +/* EXYNOS_DP_ANALOG_CTL_2 */ +#define CPREG_BLEED (0x1 << 4) +#define SEL_24M (0x1 << 3) +#define TX_DVDD_BIT_1_0000V (0x3 << 0) +#define TX_DVDD_BIT_1_0625V (0x4 << 0) +#define TX_DVDD_BIT_1_1250V (0x5 << 0) + +/* EXYNOS_DP_ANALOG_CTL_3 */ +#define DRIVE_DVDD_BIT_1_0000V (0x3 << 5) +#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) +#define DRIVE_DVDD_BIT_1_1250V (0x5 << 5) +#define SEL_CURRENT_DEFAULT (0x0 << 3) +#define VCO_BIT_000_MICRO (0x0 << 0) +#define VCO_BIT_200_MICRO (0x1 << 0) +#define VCO_BIT_300_MICRO (0x2 << 0) +#define VCO_BIT_400_MICRO (0x3 << 0) +#define VCO_BIT_500_MICRO (0x4 << 0) +#define VCO_BIT_600_MICRO (0x5 << 0) +#define VCO_BIT_700_MICRO (0x6 << 0) +#define VCO_BIT_900_MICRO (0x7 << 0) + +/* EXYNOS_DP_PLL_FILTER_CTL_1 */ +#define PD_RING_OSC (0x1 << 6) +#define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4) +#define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4) +#define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4) +#define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4) +#define TX_CUR1_1X (0x0 << 2) +#define TX_CUR1_2X (0x1 << 2) +#define TX_CUR1_3X (0x2 << 2) +#define TX_CUR_1_MA (0x0 << 0) +#define TX_CUR_2_MA (0x1 << 0) +#define TX_CUR_3_MA (0x2 << 0) +#define TX_CUR_4_MA (0x3 << 0) + +/* EXYNOS_DP_PLL_FILTER_CTL_2 */ +#define CH3_AMP_0_MV (0x3 << 12) +#define CH2_AMP_0_MV (0x3 << 8) +#define CH1_AMP_0_MV (0x3 << 4) +#define CH0_AMP_0_MV (0x3 << 0) + +/* EXYNOS_DP_PLL_CTL */ +#define DP_PLL_PD (0x1 << 7) +#define DP_PLL_RESET (0x1 << 6) +#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) +#define DP_PLL_REF_BIT_1_1250V (0x5 << 0) +#define DP_PLL_REF_BIT_1_2500V (0x7 << 0) + +/* EXYNOS_DP_INT_CTL */ +#define SOFT_INT_CTRL (0x1 << 2) +#define INT_POL (0x1 << 0) + +/* DP TX SW RESET */ +#define RESET_DP_TX (0x01 << 0) + +/* DP FUNC_EN_1 */ +#define MASTER_VID_FUNC_EN_N (0x1 << 7) +#define SLAVE_VID_FUNC_EN_N (0x1 << 5) +#define AUD_FIFO_FUNC_EN_N (0x1 << 4) +#define AUD_FUNC_EN_N (0x1 << 3) +#define HDCP_FUNC_EN_N (0x1 << 2) +#define CRC_FUNC_EN_N (0x1 << 1) +#define SW_FUNC_EN_N (0x1 << 0) + +/* DP FUNC_EN_2 */ +#define SSC_FUNC_EN_N (0x1 << 7) +#define AUX_FUNC_EN_N (0x1 << 2) +#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) +#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) + +/* EXYNOS_DP_PHY_PD */ +#define PHY_PD (0x1 << 5) +#define AUX_PD (0x1 << 4) +#define CH3_PD (0x1 << 3) +#define CH2_PD (0x1 << 2) +#define CH1_PD (0x1 << 1) +#define CH0_PD (0x1 << 0) + +/* EXYNOS_DP_COMMON_INT_STA_1 */ +#define VSYNC_DET (0x1 << 7) +#define PLL_LOCK_CHG (0x1 << 6) +#define SPDIF_ERR (0x1 << 5) +#define SPDIF_UNSTBL (0x1 << 4) +#define VID_FORMAT_CHG (0x1 << 3) +#define AUD_CLK_CHG (0x1 << 2) +#define VID_CLK_CHG (0x1 << 1) +#define SW_INT (0x1 << 0) + +/* EXYNOS_DP_DEBUG_CTL */ +#define PLL_LOCK (0x1 << 4) +#define F_PLL_LOCK (0x1 << 3) +#define PLL_LOCK_CTRL (0x1 << 2) + +/* EXYNOS_DP_FUNC_EN_2 */ +#define SSC_FUNC_EN_N (0x1 << 7) +#define AUX_FUNC_EN_N (0x1 << 2) +#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) +#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) + +/* EXYNOS_DP_COMMON_INT_STA_4 */ +#define PSR_ACTIVE (0x1 << 7) +#define PSR_INACTIVE (0x1 << 6) +#define SPDIF_BI_PHASE_ERR (0x1 << 5) +#define HOTPLUG_CHG (0x1 << 2) +#define HPD_LOST (0x1 << 1) +#define PLUG (0x1 << 0) + +/* EXYNOS_DP_INT_STA */ +#define INT_HPD (0x1 << 6) +#define HW_TRAINING_FINISH (0x1 << 5) +#define RPLY_RECEIV (0x1 << 1) +#define AUX_ERR (0x1 << 0) + +/* EXYNOS_DP_SYS_CTL_3 */ +#define HPD_STATUS (0x1 << 6) +#define F_HPD (0x1 << 5) +#define HPD_CTRL (0x1 << 4) +#define HDCP_RDY (0x1 << 3) +#define STRM_VALID (0x1 << 2) +#define F_VALID (0x1 << 1) +#define VALID_CTRL (0x1 << 0) + +/* EXYNOS_DP_AUX_HW_RETRY_CTL */ +#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) +#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) +#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) +#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) +#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) +#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) +#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) + +/* EXYNOS_DP_AUX_CH_DEFER_CTL */ +#define DEFER_CTRL_EN (0x1 << 7) +#define DEFER_COUNT(x) (((x) & 0x7f) << 0) + +#define COMMON_INT_MASK_1 (0) +#define COMMON_INT_MASK_2 (0) +#define COMMON_INT_MASK_3 (0) +#define COMMON_INT_MASK_4 (0) +#define INT_STA_MASK (0) + +/* EXYNOS_DP_BUFFER_DATA_CTL */ +#define BUF_CLR (0x1 << 7) +#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) + +/* EXYNOS_DP_AUX_ADDR_7_0 */ +#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) + +/* EXYNOS_DP_AUX_ADDR_15_8 */ +#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) + +/* EXYNOS_DP_AUX_ADDR_19_16 */ +#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) + +/* EXYNOS_DP_AUX_CH_CTL_1 */ +#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) +#define AUX_TX_COMM_MASK (0xf << 0) +#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) +#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) +#define AUX_TX_COMM_MOT (0x1 << 2) +#define AUX_TX_COMM_WRITE (0x0 << 0) +#define AUX_TX_COMM_READ (0x1 << 0) + +/* EXYNOS_DP_AUX_CH_CTL_2 */ +#define ADDR_ONLY (0x1 << 1) +#define AUX_EN (0x1 << 0) + +/* EXYNOS_DP_AUX_CH_STA */ +#define AUX_BUSY (0x1 << 4) +#define AUX_STATUS_MASK (0xf << 0) + +/* EXYNOS_DP_AUX_RX_COMM */ +#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) +#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) + +/* EXYNOS_DP_PHY_TEST */ +#define MACRO_RST (0x1 << 5) +#define CH1_TEST (0x1 << 1) +#define CH0_TEST (0x1 << 0) + +/* EXYNOS_DP_TRAINING_PTN_SET */ +#define SCRAMBLER_TYPE (0x1 << 9) +#define HW_LINK_TRAINING_PATTERN (0x1 << 8) +#define SCRAMBLING_DISABLE (0x1 << 5) +#define SCRAMBLING_ENABLE (0x0 << 5) +#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) +#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) +#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) +#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) +#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) +#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) +#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) +#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) + +/* EXYNOS_DP_TOTAL_LINE_CFG */ +#define TOTAL_LINE_CFG_L(x) ((x) & 0xff) +#define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff) +#define ACTIVE_LINE_CFG_L(x) ((x) & 0xff) +#define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff) +#define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff) +#define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff) +#define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff) +#define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff) + +#define H_F_PORCH_CFG_L(x) ((x) & 0xff) +#define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) +#define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff) +#define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) +#define H_B_PORCH_CFG_L(x) ((x) & 0xff) +#define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) + +/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */ +#define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5) +#define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3) +#define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3) +#define PRE_EMPHASIS_SET_0_MASK (0x3 << 3) +#define PRE_EMPHASIS_SET_0_SHIFT (3) +#define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3) +#define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3) +#define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3) +#define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3) +#define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2) +#define DRIVE_CURRENT_SET_0_MASK (0x3 << 0) +#define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0) +#define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3) +#define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0) +#define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0) +#define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0) +#define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0) + +/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */ +#define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5) +#define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3) +#define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3) +#define PRE_EMPHASIS_SET_1_MASK (0x3 << 3) +#define PRE_EMPHASIS_SET_1_SHIFT (3) +#define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3) +#define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3) +#define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3) +#define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3) +#define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2) +#define DRIVE_CURRENT_SET_1_MASK (0x3 << 0) +#define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0) +#define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3) +#define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0) +#define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0) +#define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0) +#define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0) + +/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */ +#define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5) +#define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3) +#define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3) +#define PRE_EMPHASIS_SET_2_MASK (0x3 << 3) +#define PRE_EMPHASIS_SET_2_SHIFT (3) +#define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3) +#define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3) +#define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3) +#define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3) +#define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2) +#define DRIVE_CURRENT_SET_2_MASK (0x3 << 0) +#define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0) +#define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3) +#define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0) +#define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0) +#define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0) +#define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0) + +/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */ +#define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5) +#define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3) +#define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3) +#define PRE_EMPHASIS_SET_3_MASK (0x3 << 3) +#define PRE_EMPHASIS_SET_3_SHIFT (3) +#define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3) +#define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3) +#define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3) +#define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3) +#define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2) +#define DRIVE_CURRENT_SET_3_MASK (0x3 << 0) +#define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0) +#define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3) +#define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0) +#define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0) +#define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0) +#define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0) + +/* EXYNOS_DP_VIDEO_CTL_10 */ +#define FORMAT_SEL (0x1 << 4) +#define INTERACE_SCAN_CFG (0x1 << 2) +#define INTERACE_SCAN_CFG_SHIFT (2) +#define VSYNC_POLARITY_CFG (0x1 << 1) +#define V_S_POLARITY_CFG_SHIFT (1) +#define HSYNC_POLARITY_CFG (0x1 << 0) +#define H_S_POLARITY_CFG_SHIFT (0) + +/* EXYNOS_DP_SOC_GENERAL_CTL */ +#define AUDIO_MODE_SPDIF_MODE (0x1 << 8) +#define AUDIO_MODE_MASTER_MODE (0x0 << 8) +#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) +#define VIDEO_MASTER_CLK_SEL (0x1 << 2) +#define VIDEO_MASTER_MODE_EN (0x1 << 1) +#define VIDEO_MODE_MASK (0x1 << 0) +#define VIDEO_MODE_SLAVE_MODE (0x1 << 0) +#define VIDEO_MODE_MASTER_MODE (0x0 << 0) + +/* EXYNOS_DP_VIDEO_CTL_1 */ +#define VIDEO_EN (0x1 << 7) +#define HDCP_VIDEO_MUTE (0x1 << 6) + +/* EXYNOS_DP_VIDEO_CTL_2 */ +#define IN_D_RANGE_MASK (0x1 << 7) +#define IN_D_RANGE_SHIFT (7) +#define IN_D_RANGE_CEA (0x1 << 7) +#define IN_D_RANGE_VESA (0x0 << 7) +#define IN_BPC_MASK (0x7 << 4) +#define IN_BPC_SHIFT (4) +#define IN_BPC_12_BITS (0x3 << 4) +#define IN_BPC_10_BITS (0x2 << 4) +#define IN_BPC_8_BITS (0x1 << 4) +#define IN_BPC_6_BITS (0x0 << 4) +#define IN_COLOR_F_MASK (0x3 << 0) +#define IN_COLOR_F_SHIFT (0) +#define IN_COLOR_F_YCBCR444 (0x2 << 0) +#define IN_COLOR_F_YCBCR422 (0x1 << 0) +#define IN_COLOR_F_RGB (0x0 << 0) + +/* EXYNOS_DP_VIDEO_CTL_3 */ +#define IN_YC_COEFFI_MASK (0x1 << 7) +#define IN_YC_COEFFI_SHIFT (7) +#define IN_YC_COEFFI_ITU709 (0x1 << 7) +#define IN_YC_COEFFI_ITU601 (0x0 << 7) +#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) +#define VID_CHK_UPDATE_TYPE_SHIFT (4) +#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) +#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) + +/* EXYNOS_DP_TEST_PATTERN_GEN_EN */ +#define TEST_PATTERN_GEN_EN (0x1 << 0) +#define TEST_PATTERN_GEN_DIS (0x0 << 0) + +/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */ +#define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0) +#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0) +#define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0) + +/* EXYNOS_DP_VIDEO_CTL_4 */ +#define BIST_EN (0x1 << 3) +#define BIST_WIDTH_MASK (0x1 << 2) +#define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2) +#define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2) +#define BIST_TYPE_MASK (0x3 << 0) +#define BIST_TYPE_COLOR_BAR (0x0 << 0) +#define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0) +#define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0) + +/* EXYNOS_DP_SYS_CTL_1 */ +#define DET_STA (0x1 << 2) +#define FORCE_DET (0x1 << 1) +#define DET_CTRL (0x1 << 0) + +/* EXYNOS_DP_SYS_CTL_2 */ +#define CHA_CRI(x) (((x) & 0xf) << 4) +#define CHA_STA (0x1 << 2) +#define FORCE_CHA (0x1 << 1) +#define CHA_CTRL (0x1 << 0) + +/* EXYNOS_DP_SYS_CTL_3 */ +#define HPD_STATUS (0x1 << 6) +#define F_HPD (0x1 << 5) +#define HPD_CTRL (0x1 << 4) +#define HDCP_RDY (0x1 << 3) +#define STRM_VALID (0x1 << 2) +#define F_VALID (0x1 << 1) +#define VALID_CTRL (0x1 << 0) + +/* EXYNOS_DP_SYS_CTL_4 */ +#define FIX_M_AUD (0x1 << 4) +#define ENHANCED (0x1 << 3) +#define FIX_M_VID (0x1 << 2) +#define M_VID_UPDATE_CTRL (0x3 << 0) + +/* EXYNOS_M_VID_X */ +#define M_VID0_CFG(x) ((x) & 0xff) +#define M_VID1_CFG(x) (((x) >> 8) & 0xff) +#define M_VID2_CFG(x) (((x) >> 16) & 0xff) + +/* EXYNOS_M_VID_X */ +#define N_VID0_CFG(x) ((x) & 0xff) +#define N_VID1_CFG(x) (((x) >> 8) & 0xff) +#define N_VID2_CFG(x) (((x) >> 16) & 0xff) + +/* DPCD_TRAINING_PATTERN_SET */ +#define DPCD_SCRAMBLING_DISABLED (0x1 << 5) +#define DPCD_SCRAMBLING_ENABLED (0x0 << 5) +#define DPCD_TRAINING_PATTERN_2 (0x2 << 0) +#define DPCD_TRAINING_PATTERN_1 (0x1 << 0) +#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0) + +/* Definition for DPCD Register */ +#define DPCD_DPCD_REV (0x0000) +#define DPCD_MAX_LINK_RATE (0x0001) +#define DPCD_MAX_LANE_COUNT (0x0002) +#define DPCD_LINK_BW_SET (0x0100) +#define DPCD_LANE_COUNT_SET (0x0101) +#define DPCD_TRAINING_PATTERN_SET (0x0102) +#define DPCD_TRAINING_LANE0_SET (0x0103) +#define DPCD_LANE0_1_STATUS (0x0202) +#define DPCD_LN_ALIGN_UPDATED (0x0204) +#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206) +#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207) +#define DPCD_TEST_REQUEST (0x0218) +#define DPCD_TEST_RESPONSE (0x0260) +#define DPCD_TEST_EDID_CHECKSUM (0x0261) +#define DPCD_SINK_POWER_STATE (0x0600) + +/* DPCD_TEST_REQUEST */ +#define DPCD_TEST_EDID_READ (0x1 << 2) + +/* DPCD_TEST_RESPONSE */ +#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2) + +/* DPCD_SINK_POWER_STATE */ +#define DPCD_SET_POWER_STATE_D0 (0x1 << 0) +#define DPCD_SET_POWER_STATE_D4 (0x2 << 0) + +/* I2C EDID Chip ID, Slave Address */ +#define I2C_EDID_DEVICE_ADDR (0x50) +#define I2C_E_EDID_DEVICE_ADDR (0x30) +#define EDID_BLOCK_LENGTH (0x80) +#define EDID_HEADER_PATTERN (0x00) +#define EDID_EXTENSION_FLAG (0x7e) +#define EDID_CHECKSUM (0x7f) + +/* DPCD_LANE0_1_STATUS */ +#define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6) +#define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5) +#define DPCD_LANE1_CR_DONE (0x1 << 4) +#define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2) +#define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1) +#define DPCD_LANE0_CR_DONE (0x1 << 0) + +/* DPCD_ADJUST_REQUEST_LANE0_1 */ +#define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6) +#define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3) +#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6) +#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6) +#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6) +#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6) +#define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4) +#define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3) +#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4) +#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4) +#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4) +#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4) +#define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2) +#define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3) +#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2) +#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2) +#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2) +#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2) +#define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0) +#define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3) +#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0) +#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0) +#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0) +#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0) + +/* DPCD_ADJUST_REQUEST_LANE2_3 */ +#define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6) +#define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3) +#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6) +#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6) +#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6) +#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6) +#define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4) +#define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3) +#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4) +#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4) +#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4) +#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4) +#define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2) +#define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3) +#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2) +#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2) +#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2) +#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2) +#define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0) +#define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3) +#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0) +#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0) +#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0) +#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0) + +/* DPCD_LANE_COUNT_SET */ +#define DPCD_ENHANCED_FRAME_EN (0x1 << 7) +#define DPCD_LN_COUNT_SET(x) ((x) & 0x1f) + +/* DPCD_LANE_ALIGN__STATUS_UPDATED */ +#define DPCD_LINK_STATUS_UPDATED (0x1 << 7) +#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6) +#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0) + +/* DPCD_TRAINING_LANE0_SET */ +#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3) +#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3) +#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3) +#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3) +#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0) +#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0) +#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0) +#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0) + +#define DPCD_REQ_ADJ_SWING (0x00) +#define DPCD_REQ_ADJ_EMPHASIS (0x01) + +#define DP_LANE_STAT_CR_DONE (0x01 << 0) +#define DP_LANE_STAT_CE_DONE (0x01 << 1) +#define DP_LANE_STAT_SYM_LOCK (0x01 << 2) + +#endif diff --git a/arch/arm/include/asm/arch-exynos/dp_info.h b/arch/arm/include/asm/arch-exynos/dp_info.h new file mode 100644 index 0000000..3569498 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dp_info.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DP_INFO_H +#define _DP_INFO_H + +#define msleep(a) udelay(a * 1000) + +#define DP_TIMEOUT_LOOP_COUNT 100 +#define MAX_CR_LOOP 5 +#define MAX_EQ_LOOP 4 + +#define EXYNOS_DP_SUCCESS 0 + +enum { + DP_DISABLE, + DP_ENABLE, +}; + +struct edp_disp_info { + char *name; + unsigned int h_total; + unsigned int h_res; + unsigned int h_sync_width; + unsigned int h_back_porch; + unsigned int h_front_porch; + unsigned int v_total; + unsigned int v_res; + unsigned int v_sync_width; + unsigned int v_back_porch; + unsigned int v_front_porch; + + unsigned int v_sync_rate; +}; + +struct edp_link_train_info { + unsigned int lt_status; + + unsigned int ep_loop; + unsigned int cr_loop[4]; + +}; + +struct edp_video_info { + unsigned int master_mode; + unsigned int bist_mode; + unsigned int bist_pattern; + + unsigned int h_sync_polarity; + unsigned int v_sync_polarity; + unsigned int interlaced; + + unsigned int color_space; + unsigned int dynamic_range; + unsigned int ycbcr_coeff; + unsigned int color_depth; +}; + +struct edp_device_info { + struct edp_disp_info disp_info; + struct edp_link_train_info lt_info; + struct edp_video_info video_info; + + /*below info get from panel during training*/ + unsigned char lane_bw; + unsigned char lane_cnt; + unsigned char dpcd_rev; + /*support enhanced frame cap */ + unsigned char dpcd_efc; +}; + +enum analog_power_block { + AUX_BLOCK, + CH0_BLOCK, + CH1_BLOCK, + CH2_BLOCK, + CH3_BLOCK, + ANALOG_TOTAL, + POWER_ALL +}; + +enum pll_status { + PLL_UNLOCKED = 0, + PLL_LOCKED +}; + +enum { + COLOR_RGB, + COLOR_YCBCR422, + COLOR_YCBCR444 +}; + +enum { + VESA, + CEA +}; + +enum { + COLOR_YCBCR601, + COLOR_YCBCR709 +}; + +enum { + COLOR_6, + COLOR_8, + COLOR_10, + COLOR_12 +}; + +enum { + DP_LANE_BW_1_62 = 0x06, + DP_LANE_BW_2_70 = 0x0a, +}; + +enum { + DP_LANE_CNT_1 = 1, + DP_LANE_CNT_2 = 2, + DP_LANE_CNT_4 = 4, +}; + +enum { + DP_DPCD_REV_10 = 0x10, + DP_DPCD_REV_11 = 0x11, +}; + +enum { + DP_LT_NONE, + DP_LT_START, + DP_LT_CR, + DP_LT_ET, + DP_LT_FINISHED, + DP_LT_FAIL, +}; + +enum { + PRE_EMPHASIS_LEVEL_0, + PRE_EMPHASIS_LEVEL_1, + PRE_EMPHASIS_LEVEL_2, + PRE_EMPHASIS_LEVEL_3, +}; + +enum { + PRBS7, + D10_2, + TRAINING_PTN1, + TRAINING_PTN2, + DP_NONE +}; + +enum { + VOLTAGE_LEVEL_0, + VOLTAGE_LEVEL_1, + VOLTAGE_LEVEL_2, + VOLTAGE_LEVEL_3, +}; + +enum pattern_type { + NO_PATTERN, + COLOR_RAMP, + BALCK_WHITE_V_LINES, + COLOR_SQUARE, + INVALID_PATTERN, + COLORBAR_32, + COLORBAR_64, + WHITE_GRAY_BALCKBAR_32, + WHITE_GRAY_BALCKBAR_64, + MOBILE_WHITEBAR_32, + MOBILE_WHITEBAR_64 +}; + +enum { + CALCULATED_M, + REGISTER_M +}; + +enum { + VIDEO_TIMING_FROM_CAPTURE, + VIDEO_TIMING_FROM_REGISTER +}; + + +struct exynos_dp_platform_data { + struct edp_device_info *edp_dev_info; + void (*phy_enable)(unsigned int); +}; + +#ifdef CONFIG_EXYNOS_DP +unsigned int exynos_init_dp(void); +#else +unsigned int exynos_init_dp(void) +{ + return 0; +} +#endif + +#endif /* _DP_INFO_H */ diff --git a/arch/arm/include/asm/arch-exynos/fb.h b/arch/arm/include/asm/arch-exynos/fb.h index b10b0da..01445af 100644 --- a/arch/arm/include/asm/arch-exynos/fb.h +++ b/arch/arm/include/asm/arch-exynos/fb.h @@ -23,7 +23,7 @@ #define __ASM_ARM_ARCH_FB_H_ #ifndef __ASSEMBLY__ -struct exynos4_fb { +struct exynos_fb { unsigned int vidcon0; unsigned int vidcon1; unsigned int vidcon2; @@ -151,9 +151,23 @@ struct exynos4_fb { unsigned char res15[156]; unsigned int dualrgb; + unsigned char res16[16]; + unsigned int dp_mie_clkcon; }; #endif +/* LCD IF register offset */ +#define EXYNOS4_LCD_IF_BASE_OFFSET 0x0 +#define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000 + +static inline unsigned int exynos_fimd_get_base_offset(void) +{ + if (cpu_is_exynos5()) + return EXYNOS5_LCD_IF_BASE_OFFSET; + else + return EXYNOS4_LCD_IF_BASE_OFFSET; +} + /* * Register offsets */ @@ -253,6 +267,8 @@ struct exynos4_fb { /* VIDTCON2 */ #define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11) #define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0) +#define EXYNOS_VIDTCON2_LINEVAL_E(x) ((((x) & 0x800) >> 11) << 23) +#define EXYNOS_VIDTCON2_HOZVAL_E(x) ((((x) & 0x800) >> 11) << 22) /* Window 0~4 Control - WINCONx */ #define EXYNOS_WINCON_DATAPATH_DMA (0 << 22) @@ -330,6 +346,8 @@ struct exynos4_fb { #define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0) #define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11) #define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0) +#define EXYNOS_VIDOSD_RIGHT_X_E(x) (((x) & 0x1) << 23) +#define EXYNOS_VIDOSD_BOTTOM_Y_E(x) (((x) & 0x1) << 22) /* VIDOSD0C, VIDOSDxD */ #define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0) @@ -354,6 +372,8 @@ struct exynos4_fb { /* Buffer Size */ #define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13) #define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0) +#define EXYNOS_VIDADDR_OFFSIZE_E(x) ((((x) & 0x2000) >> 13) << 27) +#define EXYNOS_VIDADDR_PAGEWIDTH_E(x) ((((x) & 0x2000) >> 13) << 26) /* WIN Color Map */ #define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff) @@ -443,4 +463,9 @@ struct exynos4_fb { #define EXYNOS_I80START_TRIG (1 << 1) #define EXYNOS_I80STATUS_TRIG_DONE (1 << 2) +/* DP_MIE_CLKCON */ +#define EXYNOS_DP_MIE_DISABLE (0 << 0) +#define EXYNOS_DP_CLK_ENABLE (1 << 1) +#define EXYNOS_MIE_CLK_ENABLE (3 << 0) + #endif /* _REGS_FB_H */ diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 7a9bb90..97be4ea 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -100,7 +100,9 @@ struct exynos5_gpio_part1 { struct s5p_gpio_bank y4; struct s5p_gpio_bank y5; struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[0x980]; + struct s5p_gpio_bank res1[0x3]; + struct s5p_gpio_bank c4; + struct s5p_gpio_bank res2[0x48]; struct s5p_gpio_bank x0; struct s5p_gpio_bank x1; struct s5p_gpio_bank x2; @@ -122,9 +124,10 @@ struct exynos5_gpio_part2 { struct exynos5_gpio_part3 { struct s5p_gpio_bank v0; struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[0x1]; struct s5p_gpio_bank v2; struct s5p_gpio_bank v3; - struct s5p_gpio_bank res1[0x20]; + struct s5p_gpio_bank res2[0x1]; struct s5p_gpio_bank v4; }; diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h index 0f701c9..afdfcf0 100644 --- a/arch/arm/include/asm/arch-exynos/mmc.h +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -64,11 +64,11 @@ #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) -int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); +int s5p_sdhci_init(u32 regbase, int index, int bus_width); static inline unsigned int s5p_mmc_init(int index, int bus_width) { unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return s5p_sdhci_init(base, 52000000, 400000, index); + return s5p_sdhci_init(base, index, bus_width); } #endif diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index e5467e2..d2fdb59 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -859,4 +859,9 @@ void set_usbhost_phy_ctrl(unsigned int enable); #define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) #define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) + +void set_dp_phy_ctrl(unsigned int enable); + +#define EXYNOS_DP_PHY_ENABLE (1 << 0) + #endif diff --git a/arch/arm/include/asm/arch-exynos/pwm_backlight.h b/arch/arm/include/asm/arch-exynos/pwm_backlight.h new file mode 100644 index 0000000..368ffc5 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/pwm_backlight.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PWM_BACKLIGHT_H_ +#define _PWM_BACKLIGHT_H_ + +struct pwm_backlight_data { + int pwm_id; + int period; + int max_brightness; + int brightness; +}; + +extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd); + +#endif /* _PWM_BACKLIGHT_H_ */ diff --git a/arch/arm/include/asm/arch-exynos/spl.h b/arch/arm/include/asm/arch-exynos/spl.h new file mode 100644 index 0000000..306b41d --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/spl.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_EXYNOS_SPL_H__ +#define __ASM_ARCH_EXYNOS_SPL_H__ + +#include <asm/arch-exynos/dmc.h> + +enum boot_mode { + /* + * Assign the OM pin values for respective boot modes. + * Exynos4 does not support spi boot and the mmc boot OM + * pin values are the same across Exynos4 and Exynos5. + */ + BOOT_MODE_MMC = 4, + BOOT_MODE_SERIAL = 20, + /* Boot based on Operating Mode pin settings */ + BOOT_MODE_OM = 32, + BOOT_MODE_USB, /* Boot using USB download */ +}; + +#ifndef __ASSEMBLY__ +/* Parameters of early board initialization in SPL */ +struct spl_machine_param { + /* Add fields as and when required */ + u32 signature; + u32 version; /* Version number */ + u32 size; /* Size of block */ + /** + * Parameters we expect, in order, terminated with \0. Each parameter + * is a single character representing one 32-bit word in this + * structure. + * + * Valid characters in this string are: + * + * Code Name + * v mem_iv_size + * m mem_type + * u uboot_size + * b boot_source + * f frequency_mhz (memory frequency in MHz) + * a ARM clock frequency in MHz + * s serial base address + * i i2c base address for early access (meant for PMIC) + * r board rev GPIO numbers used to read board revision + * (lower halfword=bit 0, upper=bit 1) + * M Memory Manufacturer name + * \0 termination + */ + char params[12]; /* Length must be word-aligned */ + u32 mem_iv_size; /* Memory channel interleaving size */ + enum ddr_mode mem_type; /* Type of on-board memory */ + /* + * U-boot size - The iROM mmc copy function used by the SPL takes a + * block count paramter to describe the u-boot size unlike the spi + * boot copy function which just uses the u-boot size directly. Align + * the u-boot size to block size (512 bytes) when populating the SPL + * table only for mmc boot. + */ + u32 uboot_size; + enum boot_mode boot_source; /* Boot device */ + enum mem_manuf mem_manuf; /* Memory Manufacturer */ + unsigned frequency_mhz; /* Frequency of memory in MHz */ + unsigned arm_freq_mhz; /* ARM Frequency in MHz */ + u32 serial_base; /* Serial base address */ + u32 i2c_base; /* i2c base address */ +} __attribute__((__packed__)); +#endif + +/** + * Validate signature and return a pointer to the parameter table. If the + * signature is invalid, call panic() and never return. + * + * @return pointer to the parameter table if signature matched or never return. + */ +struct spl_machine_param *spl_get_machine_params(void); + +#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */ |