diff options
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/clock.h | 24 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 55 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/cpu.h | 218 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 264 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/hardware.h | 81 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/sys_proto.h | 39 |
6 files changed, 681 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h new file mode 100644 index 0000000..872ff82 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -0,0 +1,24 @@ +/* + * clock.h + * + * clock header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CLOCKS_H_ +#define _CLOCKS_H_ + +#include <asm/arch/clocks_am33xx.h> + +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h new file mode 100644 index 0000000..abc5b6b --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -0,0 +1,55 @@ +/* + * clocks_am33xx.h + * + * AM33xx clock define + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CLOCKS_AM33XX_H_ +#define _CLOCKS_AM33XX_H_ + +#define OSC 24 + +/* MAIN PLL Fdll = 550 MHZ, */ +#define MPUPLL_M 550 +#define MPUPLL_N 23 +#define MPUPLL_M2 1 + +/* Core PLL Fdll = 1 GHZ, */ +#define COREPLL_M 1000 +#define COREPLL_N 23 + +#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ +#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ +#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */ + +/* + * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll + * frequency needs to be set to 960 MHZ. Hence, + * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below + */ +#define PERPLL_M 960 +#define PERPLL_N 23 +#define PERPLL_M2 5 + +/* DDR Freq is 266 MHZ for now */ +/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ +#define DDRPLL_M 266 +#define DDRPLL_N 23 +#define DDRPLL_M2 1 + +extern void pll_init(void); +extern void enable_emif_clocks(void); + +#endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h new file mode 100644 index 0000000..ad9156e --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -0,0 +1,218 @@ +/* + * cpu.h + * + * AM33xx specific header file + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _AM33XX_CPU_H +#define _AM33XX_CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include <asm/arch/hardware.h> + +#define BIT(x) (1 << x) +#define CL_BIT(x) (0 << x) + +/* Timer register bits */ +#define TCLR_ST BIT(0) /* Start=1 Stop=0 */ +#define TCLR_AR BIT(1) /* Auto reload */ +#define TCLR_PRE BIT(5) /* Pre-scaler enable */ +#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ +#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ + +/* device type */ +#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* cpu-id for AM33XX family */ +#define AM335X 0xB944 +#define DEVICE_ID 0x44E10600 + +/* This gives the status of the boot mode pins on the evm */ +#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ + | BIT(3) | BIT(4)) + +/* Reset control */ +#ifdef CONFIG_AM335X +#define PRM_RSTCTRL 0x44E00F00 +#endif +#define PRM_RSTCTRL_RESET 0x01 + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +/* Encapsulating core pll registers */ +struct cm_wkuppll { + unsigned int wkclkstctrl; /* offset 0x00 */ + unsigned int wkctrlclkctrl; /* offset 0x04 */ + unsigned int resv1[1]; + unsigned int wkl4wkclkctrl; /* offset 0x0c */ + unsigned int resv2[4]; + unsigned int idlestdpllmpu; /* offset 0x20 */ + unsigned int resv3[2]; + unsigned int clkseldpllmpu; /* offset 0x2c */ + unsigned int resv4[1]; + unsigned int idlestdpllddr; /* offset 0x34 */ + unsigned int resv5[2]; + unsigned int clkseldpllddr; /* offset 0x40 */ + unsigned int resv6[4]; + unsigned int clkseldplldisp; /* offset 0x54 */ + unsigned int resv7[1]; + unsigned int idlestdpllcore; /* offset 0x5c */ + unsigned int resv8[2]; + unsigned int clkseldpllcore; /* offset 0x68 */ + unsigned int resv9[1]; + unsigned int idlestdpllper; /* offset 0x70 */ + unsigned int resv10[3]; + unsigned int divm4dpllcore; /* offset 0x80 */ + unsigned int divm5dpllcore; /* offset 0x84 */ + unsigned int clkmoddpllmpu; /* offset 0x88 */ + unsigned int clkmoddpllper; /* offset 0x8c */ + unsigned int clkmoddpllcore; /* offset 0x90 */ + unsigned int clkmoddpllddr; /* offset 0x94 */ + unsigned int clkmoddplldisp; /* offset 0x98 */ + unsigned int clkseldpllper; /* offset 0x9c */ + unsigned int divm2dpllddr; /* offset 0xA0 */ + unsigned int divm2dplldisp; /* offset 0xA4 */ + unsigned int divm2dpllmpu; /* offset 0xA8 */ + unsigned int divm2dpllper; /* offset 0xAC */ + unsigned int resv11[1]; + unsigned int wkup_uart0ctrl; /* offset 0xB4 */ + unsigned int resv12[8]; + unsigned int divm6dpllcore; /* offset 0xD8 */ +}; + +/** + * Encapsulating peripheral functional clocks + * pll registers + */ +struct cm_perpll { + unsigned int l4lsclkstctrl; /* offset 0x00 */ + unsigned int l3sclkstctrl; /* offset 0x04 */ + unsigned int l4fwclkstctrl; /* offset 0x08 */ + unsigned int l3clkstctrl; /* offset 0x0c */ + unsigned int resv1[6]; + unsigned int emifclkctrl; /* offset 0x28 */ + unsigned int ocmcramclkctrl; /* offset 0x2c */ + unsigned int resv2[12]; + unsigned int l4lsclkctrl; /* offset 0x60 */ + unsigned int l4fwclkctrl; /* offset 0x64 */ + unsigned int resv3[6]; + unsigned int timer2clkctrl; /* offset 0x80 */ + unsigned int resv4[19]; + unsigned int emiffwclkctrl; /* offset 0xD0 */ + unsigned int resv5[2]; + unsigned int l3instrclkctrl; /* offset 0xDC */ + unsigned int l3clkctrl; /* Offset 0xE0 */ + unsigned int resv6[14]; + unsigned int l4hsclkstctrl; /* offset 0x11C */ + unsigned int l4hsclkctrl; /* offset 0x120 */ +}; + +/* Encapsulating Display pll registers */ +struct cm_dpll { + unsigned int resv1[2]; + unsigned int clktimer2clk; /* offset 0x08 */ +}; + +/* Watchdog timer registers */ +struct wd_timer { + unsigned int resv1[4]; + unsigned int wdtwdsc; /* offset 0x010 */ + unsigned int wdtwdst; /* offset 0x014 */ + unsigned int wdtwisr; /* offset 0x018 */ + unsigned int wdtwier; /* offset 0x01C */ + unsigned int wdtwwer; /* offset 0x020 */ + unsigned int wdtwclr; /* offset 0x024 */ + unsigned int wdtwcrr; /* offset 0x028 */ + unsigned int wdtwldr; /* offset 0x02C */ + unsigned int wdtwtgr; /* offset 0x030 */ + unsigned int wdtwwps; /* offset 0x034 */ + unsigned int resv2[3]; + unsigned int wdtwdly; /* offset 0x044 */ + unsigned int wdtwspr; /* offset 0x048 */ + unsigned int resv3[1]; + unsigned int wdtwqeoi; /* offset 0x050 */ + unsigned int wdtwqstar; /* offset 0x054 */ + unsigned int wdtwqsta; /* offset 0x058 */ + unsigned int wdtwqens; /* offset 0x05C */ + unsigned int wdtwqenc; /* offset 0x060 */ + unsigned int resv4[39]; + unsigned int wdt_unfr; /* offset 0x100 */ +}; + +/* Timer Registers */ +struct timer_reg { + unsigned int resv1[4]; + unsigned int tiocpcfgreg; /* offset 0x10 */ + unsigned int resv2[9]; + unsigned int tclrreg; /* offset 0x38 */ + unsigned int tcrrreg; /* offset 0x3C */ + unsigned int tldrreg; /* offset 0x40 */ + unsigned int resv3[4]; + unsigned int tsicrreg; /* offset 0x54 */ +}; + +/* Timer 32 bit registers */ +struct gptimer { + unsigned int tidr; /* offset 0x00 */ + unsigned int res1[0xc]; + unsigned int tiocp_cfg; /* offset 0x10 */ + unsigned int res2[0xc]; + unsigned int tier; /* offset 0x20 */ + unsigned int tistatr; /* offset 0x24 */ + unsigned int tistat; /* offset 0x28 */ + unsigned int tisr; /* offset 0x2c */ + unsigned int tcicr; /* offset 0x30 */ + unsigned int twer; /* offset 0x34 */ + unsigned int tclr; /* offset 0x38 */ + unsigned int tcrr; /* offset 0x3c */ + unsigned int tldr; /* offset 0x40 */ + unsigned int ttgr; /* offset 0x44 */ + unsigned int twpc; /* offset 0x48 */ + unsigned int tmar; /* offset 0x4c */ + unsigned int tcar1; /* offset 0x50 */ + unsigned int tscir; /* offset 0x54 */ + unsigned int tcar2; /* offset 0x58 */ +}; + +/* UART Registers */ +struct uart_sys { + unsigned int resv1[21]; + unsigned int uartsyscfg; /* offset 0x54 */ + unsigned int uartsyssts; /* offset 0x58 */ +}; + +/* VTP Registers */ +struct vtp_reg { + unsigned int vtp0ctrlreg; +}; + +/* Control Status Register */ +struct ctrl_stat { + unsigned int resv1[16]; + unsigned int statusreg; /* ofset 0x40 */ +}; + +void init_timer(void); +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#endif /* _AM33XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h new file mode 100644 index 0000000..9638b4c --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -0,0 +1,264 @@ +/* + * ddr_defs.h + * + * ddr specific header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DDR_DEFS_H +#define _DDR_DEFS_H + +#include <asm/arch/hardware.h> + +/* AM335X EMIF Register values */ +#define EMIF_SDMGT 0x80000000 +#define EMIF_SDRAM 0x00004650 +#define EMIF_PHYCFG 0x2 +#define DDR_PHY_RESET (0x1 << 10) +#define DDR_FUNCTIONAL_MODE_EN 0x1 +#define DDR_PHY_READY (0x1 << 2) +#define VTP_CTRL_READY (0x1 << 5) +#define VTP_CTRL_ENABLE (0x1 << 6) +#define VTP_CTRL_LOCK_EN (0x1 << 4) +#define VTP_CTRL_START_EN (0x1) +#define DDR2_RATIO 0x80 +#define CMD_FORCE 0x00 +#define CMD_DELAY 0x00 + +#define EMIF_READ_LATENCY 0x04 +#define EMIF_TIM1 0x0666B3D6 +#define EMIF_TIM2 0x143731DA +#define EMIF_TIM3 0x00000347 +#define EMIF_SDCFG 0x43805332 +#define EMIF_SDREF 0x0000081a +#define DDR2_DLL_LOCK_DIFF 0x0 +#define DDR2_RD_DQS 0x12 +#define DDR2_PHY_FIFO_WE 0x80 + +#define DDR2_INVERT_CLKOUT 0x00 +#define DDR2_WR_DQS 0x00 +#define DDR2_PHY_WRLVL 0x00 +#define DDR2_PHY_GATELVL 0x00 +#define DDR2_PHY_WR_DATA 0x40 +#define PHY_RANK0_DELAY 0x01 +#define PHY_DLL_LOCK_DIFF 0x0 +#define DDR_IOCTRL_VALUE 0x18B + +/** + * This structure represents the EMIF registers on AM33XX devices. + */ +struct emif_regs { + unsigned int sdrrev; /* offset 0x00 */ + unsigned int sdrstat; /* offset 0x04 */ + unsigned int sdrcr; /* offset 0x08 */ + unsigned int sdrcr2; /* offset 0x0C */ + unsigned int sdrrcr; /* offset 0x10 */ + unsigned int sdrrcsr; /* offset 0x14 */ + unsigned int sdrtim1; /* offset 0x18 */ + unsigned int sdrtim1sr; /* offset 0x1C */ + unsigned int sdrtim2; /* offset 0x20 */ + unsigned int sdrtim2sr; /* offset 0x24 */ + unsigned int sdrtim3; /* offset 0x28 */ + unsigned int sdrtim3sr; /* offset 0x2C */ + unsigned int res1[2]; + unsigned int sdrmcr; /* offset 0x38 */ + unsigned int sdrmcsr; /* offset 0x3C */ + unsigned int res2[8]; + unsigned int sdritr; /* offset 0x60 */ + unsigned int res3[20]; + unsigned int ddrphycr; /* offset 0xE4 */ + unsigned int ddrphycsr; /* offset 0xE8 */ + unsigned int ddrphycr2; /* offset 0xEC */ +}; + +/** + * Encapsulates DDR PHY control and corresponding shadow registers. + */ +struct ddr_phy_control { + unsigned long reg; + unsigned long reg_sh; + unsigned long reg2; +}; + +/** + * Encapsulates SDRAM timing and corresponding shadow registers. + */ +struct sdram_timing { + unsigned long time1; + unsigned long time1_sh; + unsigned long time2; + unsigned long time2_sh; + unsigned long time3; + unsigned long time3_sh; +}; + +/** + * Encapsulates SDRAM configuration. + * (Includes refresh control registers) */ +struct sdram_config { + unsigned long sdrcr; + unsigned long sdrcr2; + unsigned long refresh; + unsigned long refresh_sh; +}; + +/** + * Configure SDRAM + */ +int config_sdram(struct sdram_config *cfg); + +/** + * Set SDRAM timings + */ +int set_sdram_timings(struct sdram_timing *val); + +/** + * Configure DDR PHY + */ +int config_ddr_phy(struct ddr_phy_control *cfg); + +/** + * This structure represents the DDR registers on AM33XX devices. + */ +struct ddr_regs { + unsigned int resv0[7]; + unsigned int cm0csratio; /* offset 0x01C */ + unsigned int cm0csforce; /* offset 0x020 */ + unsigned int cm0csdelay; /* offset 0x024 */ + unsigned int cm0dldiff; /* offset 0x028 */ + unsigned int cm0iclkout; /* offset 0x02C */ + unsigned int resv1[8]; + unsigned int cm1csratio; /* offset 0x050 */ + unsigned int cm1csforce; /* offset 0x054 */ + unsigned int cm1csdelay; /* offset 0x058 */ + unsigned int cm1dldiff; /* offset 0x05C */ + unsigned int cm1iclkout; /* offset 0x060 */ + unsigned int resv2[8]; + unsigned int cm2csratio; /* offset 0x084 */ + unsigned int cm2csforce; /* offset 0x088 */ + unsigned int cm2csdelay; /* offset 0x08C */ + unsigned int cm2dldiff; /* offset 0x090 */ + unsigned int cm2iclkout; /* offset 0x094 */ + unsigned int resv3[12]; + unsigned int dt0rdsratio0; /* offset 0x0C8 */ + unsigned int dt0rdsratio1; /* offset 0x0CC */ + unsigned int resv4[3]; + unsigned int dt0wdsratio0; /* offset 0x0DC */ + unsigned int dt0wdsratio1; /* offset 0x0E0 */ + unsigned int resv5[3]; + unsigned int dt0wiratio0; /* offset 0x0F0 */ + unsigned int dt0wiratio1; /* offset 0x0F4 */ + unsigned int dt0giratio0; /* offset 0x0FC */ + unsigned int dt0giratio1; /* offset 0x100 */ + unsigned int resv6[2]; + unsigned int dt0fwsratio0; /* offset 0x108 */ + unsigned int dt0fwsratio1; /* offset 0x10C */ + unsigned int resv7[5]; + unsigned int dt0wrsratio0; /* offset 0x120 */ + unsigned int dt0wrsratio1; /* offset 0x124 */ + unsigned int resv8[3]; + unsigned int dt0rdelays0; /* offset 0x134 */ + unsigned int dt0dldiff0; /* offset 0x138 */ + unsigned int resv9[39]; + unsigned int dt1rdelays0; /* offset 0x1D8 */ +}; + +/** + * Encapsulates DDR CMD control registers. + */ +struct cmd_control { + unsigned long cmd0csratio; + unsigned long cmd0csforce; + unsigned long cmd0csdelay; + unsigned long cmd0dldiff; + unsigned long cmd0iclkout; + unsigned long cmd1csratio; + unsigned long cmd1csforce; + unsigned long cmd1csdelay; + unsigned long cmd1dldiff; + unsigned long cmd1iclkout; + unsigned long cmd2csratio; + unsigned long cmd2csforce; + unsigned long cmd2csdelay; + unsigned long cmd2dldiff; + unsigned long cmd2iclkout; +}; + +/** + * Encapsulates DDR DATA registers. + */ +struct ddr_data { + unsigned long datardsratio0; + unsigned long datardsratio1; + unsigned long datawdsratio0; + unsigned long datawdsratio1; + unsigned long datawiratio0; + unsigned long datawiratio1; + unsigned long datagiratio0; + unsigned long datagiratio1; + unsigned long datafwsratio0; + unsigned long datafwsratio1; + unsigned long datawrsratio0; + unsigned long datawrsratio1; + unsigned long datadldiff0; +}; + +/** + * Configure DDR CMD control registers + */ +int config_cmd_ctrl(struct cmd_control *cmd); + +/** + * Configure DDR DATA registers + */ +int config_ddr_data(int data_macrono, struct ddr_data *data); + +/** + * This structure represents the DDR io control on AM33XX devices. + */ +struct ddr_cmdtctrl { + unsigned int resv1[1]; + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int resv2[12]; + unsigned int dt0ioctl; + unsigned int dt1ioctl; +}; + +/** + * Encapsulates DDR CMD & DATA io control registers. + */ +struct ddr_ioctrl { + unsigned long cmd1ctl; + unsigned long cmd2ctl; + unsigned long cmd3ctl; + unsigned long data1ctl; + unsigned long data2ctl; +}; + +/** + * Configure DDR io control registers + */ +int config_io_ctrl(struct ddr_ioctrl *ioctrl); + +struct ddr_ctrl { + unsigned int ddrioctrl; + unsigned int resv1[325]; + unsigned int ddrckectrl; +}; + +void config_ddr(void); + +#endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h new file mode 100644 index 0000000..0ec22eb --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -0,0 +1,81 @@ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AM33XX_HARDWARE_H +#define __AM33XX_HARDWARE_H + +/* Module base addresses */ +#define LOW_LEVEL_SRAM_STACK 0x4030B7FC +#define UART0_BASE 0x44E09000 + +/* DM Timer base addresses */ +#define DM_TIMER0_BASE 0x4802C000 +#define DM_TIMER1_BASE 0x4802E000 +#define DM_TIMER2_BASE 0x48040000 +#define DM_TIMER3_BASE 0x48042000 +#define DM_TIMER4_BASE 0x48044000 +#define DM_TIMER5_BASE 0x48046000 +#define DM_TIMER6_BASE 0x48048000 +#define DM_TIMER7_BASE 0x4804A000 + +/* GPIO Base address */ +#define GPIO0_BASE 0x48032000 +#define GPIO1_BASE 0x4804C000 +#define GPIO2_BASE 0x481AC000 + +/* BCH Error Location Module */ +#define ELM_BASE 0x48080000 + +/* Watchdog Timer */ +#define WDT_BASE 0x44E35000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x44E10000 + +/* PRCM Base Address */ +#define PRCM_BASE 0x44E00000 + +/* EMIF Base address */ +#define EMIF4_0_CFG_BASE 0x4C000000 +#define EMIF4_1_CFG_BASE 0x4D000000 +#define DMM_BASE 0x4E000000 + +/* PLL related registers */ +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_DEVICE 0x44E00700 +#define CM_CEFUSE 0x44E00A00 +#define PRM_DEVICE 0x44E00F00 + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x44E10E0C + +/* DDR Base address */ +#define DDR_CTRL_ADDR 0x44E10E04 +#define DDR_CONTROL_BASE_ADDR 0x44E11404 +#define DDR_PHY_BASE_ADDR 0x44E12000 +#define DDR_PHY_BASE_ADDR2 0x44E120A4 + +/* UART */ +#define DEFAULT_UART_BASE UART0_BASE + +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + +#endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h new file mode 100644 index 0000000..1e265c6 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -0,0 +1,39 @@ +/* + * sys_proto.h + * + * System information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#define BOARD_REV_ID 0x0 +struct { + u32 board_type_v1; + u32 board_type_v2; + u32 mtype; + char *board_string; + char *nand_string; +} board_sysinfo; + +u32 get_cpu_rev(void); +u32 get_sysboot_value(void); + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void); +#endif + +u32 get_device_type(void); +#endif |