diff options
Diffstat (limited to 'arch/arm/imx-common')
| -rw-r--r-- | arch/arm/imx-common/cache.c | 17 | ||||
| -rw-r--r-- | arch/arm/imx-common/cpu.c | 2 | ||||
| -rw-r--r-- | arch/arm/imx-common/iomux-v3.c | 10 | ||||
| -rw-r--r-- | arch/arm/imx-common/spl.c | 6 | ||||
| -rw-r--r-- | arch/arm/imx-common/timer.c | 10 |
5 files changed, 26 insertions, 19 deletions
diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c index b775488..1c4a9a2 100644 --- a/arch/arm/imx-common/cache.c +++ b/arch/arm/imx-common/cache.c @@ -8,6 +8,7 @@ #include <asm/armv7.h> #include <asm/pl310.h> #include <asm/io.h> +#include <asm/imx-common/sys_proto.h> #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) @@ -39,6 +40,7 @@ void enable_caches(void) void v7_outer_cache_enable(void) { struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; unsigned int val; @@ -55,15 +57,14 @@ void v7_outer_cache_enable(void) */ setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); -#if defined CONFIG_MX6SL - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - val = readl(&iomux->gpr[11]); - if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { - /* L2 cache configured as OCRAM, reset it */ - val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; - writel(val, &iomux->gpr[11]); + if (is_mx6sl() || is_mx6sll()) { + val = readl(&iomux->gpr[11]); + if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { + /* L2 cache configured as OCRAM, reset it */ + val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; + writel(val, &iomux->gpr[11]); + } } -#endif writel(0x132, &pl310->pl310_tag_latency_ctrl); writel(0x132, &pl310->pl310_data_latency_ctrl); diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 632faca..40fe813 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -155,6 +155,8 @@ const char *get_imx_type(u32 imxtype) return "6SOLO"; /* Solo version of the mx6 */ case MXC_CPU_MX6SL: return "6SL"; /* Solo-Lite version of the mx6 */ + case MXC_CPU_MX6SLL: + return "6SLL"; /* SLL version of the mx6 */ case MXC_CPU_MX6SX: return "6SX"; /* SoloX version of the mx6 */ case MXC_CPU_MX6UL: diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 392f4bc..c9a3bf2 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -31,7 +31,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; -#if defined CONFIG_MX6SL +#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) /* Check whether LVE bit needs to be set */ if (pad_ctrl & PAD_CTL_LVE) { pad_ctrl &= ~PAD_CTL_LVE; @@ -51,7 +51,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS; } #else - if (is_mx6ull()) { + if (is_mx6ull() || is_mx6sll()) { if (lpsr == IOMUX_CONFIG_LPSR) { base = (void *)IOMUXC_SNVS_BASE_ADDR; mux_mode &= ~IOMUX_CONFIG_LPSR; @@ -60,7 +60,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #endif #endif - if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs) + if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); if (sel_input_ofs) @@ -73,6 +73,10 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #else if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); +#if defined(CONFIG_MX6SLL) + else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) + clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT); +#endif #endif #ifdef CONFIG_IOMUX_LPSR diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c index 325ba26..bdcda7d 100644 --- a/arch/arm/imx-common/spl.c +++ b/arch/arm/imx-common/spl.c @@ -14,9 +14,6 @@ #include <spl.h> #if defined(CONFIG_MX6) -#define MX6_MMC_PORT_MASK GENMASK(12, 11) -#define MX6_MMC_PORT_2 BIT(11) - /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */ u32 spl_boot_device(void) { @@ -58,11 +55,10 @@ u32 spl_boot_device(void) /* SD/eSD: 8.5.3, Table 8-15 */ case 0x4: case 0x5: + return BOOT_DEVICE_MMC1; /* MMC/eMMC: 8.5.3 */ case 0x6: case 0x7: - if ((reg & MX6_MMC_PORT_MASK) == MX6_MMC_PORT_2) - return BOOT_DEVICE_MMC2; return BOOT_DEVICE_MMC1; /* NAND Flash: 8.5.2 */ case 0x8 ... 0xf: diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index 1f7c671..ee6eff2 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -45,7 +45,7 @@ static inline int gpt_has_clk_source_osc(void) #if defined(CONFIG_MX6) if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() || - is_mx6ull()) + is_mx6ull() || is_mx6sll()) return 1; return 0; @@ -84,8 +84,12 @@ int timer_init(void) if (gpt_has_clk_source_osc()) { i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; - /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler */ - if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) { + /* + * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC + * Enable bit and prescaler + */ + if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() || + is_mx6sll()) { i |= GPTCR_24MEN; /* Produce 3Mhz clock */ |