diff options
Diffstat (limited to 'arch/arm/imx-common')
-rw-r--r-- | arch/arm/imx-common/Makefile | 11 | ||||
-rw-r--r-- | arch/arm/imx-common/syscounter.c | 126 | ||||
-rw-r--r-- | arch/arm/imx-common/timer.c | 8 |
3 files changed, 140 insertions, 5 deletions
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index a50b52c..70f22b2 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -2,7 +2,7 @@ # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -# (C) Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2011-2015 Freescale Semiconductor, Inc. # # SPDX-License-Identifier: GPL-2.0+ # @@ -11,12 +11,17 @@ ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610)) obj-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) -obj-y += timer.o cpu.o speed.o +obj-y += cpu.o speed.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif +ifeq ($(SOC),$(filter $(SOC),mx5)) +obj-y += timer.o +endif ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o +obj-$(CONFIG_GPT_TIMER) += timer.o +obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs)) obj-y += misc.o @@ -26,6 +31,8 @@ ifeq ($(SOC),$(filter $(SOC),mx6)) obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-$(CONFIG_MXC_RDC) += rdc-sema.o +obj-$(CONFIG_GPT_TIMER) += timer.o +obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o diff --git a/arch/arm/imx-common/syscounter.c b/arch/arm/imx-common/syscounter.c new file mode 100644 index 0000000..f5e5cdc --- /dev/null +++ b/arch/arm/imx-common/syscounter.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * The file use ls102xa/timer.c as a reference. + */ + +#include <common.h> +#include <asm/io.h> +#include <div64.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/syscounter.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * This function is intended for SHORT delays only. + * It will overflow at around 10 seconds @ 400MHz, + * or 20 seconds @ 200MHz. + */ +unsigned long usec2ticks(unsigned long usec) +{ + ulong ticks; + + if (usec < 1000) + ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; + else + ticks = ((usec / 10) * (get_tbclk() / 100000)); + + return ticks; +} + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + unsigned long freq; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); + + tick *= CONFIG_SYS_HZ; + do_div(tick, freq); + + return tick; +} + +static inline unsigned long long us_to_tick(unsigned long long usec) +{ + unsigned long freq; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); + + usec = usec * freq + 999999; + do_div(usec, 1000000); + + return usec; +} + +int timer_init(void) +{ + struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; + unsigned long val, freq; + + freq = CONFIG_SC_TIMER_CLK; + asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + + writel(freq, &sctr->cntfid0); + + /* Enable system counter */ + val = readl(&sctr->cntcr); + val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); + val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; + writel(val, &sctr->cntcr); + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + return 0; +} + +unsigned long long get_ticks(void) +{ + unsigned long long now; + + asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now)); + + gd->arch.tbl = (unsigned long)(now & 0xffffffff); + gd->arch.tbu = (unsigned long)(now >> 32); + + return now; +} + +ulong get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void __udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + unsigned long freq; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); + + return freq; +} diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index c9eb530..6fea6fe 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -45,7 +45,8 @@ static inline int gpt_has_clk_source_osc(void) #if defined(CONFIG_MX6) if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) && (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX)) + is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) || + is_cpu_type(MXC_CPU_MX6UL)) return 1; return 0; @@ -109,11 +110,12 @@ int timer_init(void) if (gpt_has_clk_source_osc()) { i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; - /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */ + /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */ if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) || - is_cpu_type(MXC_CPU_MX7D)) { + is_cpu_type(MXC_CPU_MX7D) || + is_cpu_type(MXC_CPU_MX6UL)) { i |= GPTCR_24MEN; /* Produce 3Mhz clock */ |